CN115242220A - Digital shaping filter with dynamically reconfigurable order folding circuit structure and design method - Google Patents
Digital shaping filter with dynamically reconfigurable order folding circuit structure and design method Download PDFInfo
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Abstract
The disclosure provides a digital shaping filter with an order dynamic reconfigurable folding circuit structure and a design method. The digital shaping filter includes: the data redefinition logic unit is used for carrying out bit width conversion; the data shift register unit is used for storing the output data of the data redefinition logic unit; a first adder unit for performing addition operation according to a folding circuit configuration; the shock response coefficient register unit is used for writing the shock response coefficient; a reconfiguration complete flag register unit for sending a reconfiguration complete signal; the multiplier unit is used for carrying out multiplication operation and receiving an output signal of the reconstruction completion flag register unit; a second adder unit for adding the output data of the multiplier unit; the order reconstruction register unit is used for writing the order of the digital shaping filter; a sequential control logic unit for selecting result data; and the selection output logic unit is used for outputting the result data.
Description
Technical Field
The disclosure relates to the technical field of digital signal processing, and more particularly to a digital shaping filter with an order dynamically reconfigurable folding circuit structure and a design method thereof.
Background
Digital signal processing techniques are widely used in the fields of radar signal processing, wireless transmission, satellite communication and the like, and digital filters are the main components of digital signal processing. In radar signal processing and wireless communication systems, the frequency bandwidth and power of signals are limited to a certain extent, the broadband, high-frequency spectrum utilization rate and low-loss modulation signal shaping filtering technology is one of key technologies for realizing a high-speed data transmission system, and the shaping filtering technology can improve the utilization rate of frequency bands on the premise of eliminating intersymbol interference and achieving optimal detection. With the development of digital signal processing technology and high-speed large-scale digital integrated circuit technology, digital shaping filters have the characteristics of high precision, high flexibility and convenience for large-scale integration compared with analog shaping filters, so digital shaping filters are mostly adopted by shaping filters.
In implementing the disclosed concept, the inventors found that there are at least the following problems in the related art: in the related art, after the digital shaping filter is designed, the hardware structure is determined, parameters need to be reselected to change the characteristics of the digital shaping filter, and then the hardware structure of the digital shaping filter is rearranged and wired, which wastes a lot of time and resources.
Disclosure of Invention
In view of this, the present disclosure provides a digital shaping filter with an order dynamically reconfigurable folding circuit structure and a design method thereof.
One aspect of the present disclosure provides a digital shaping filter with an order dynamically reconfigurable folding circuit structure, comprising:
the data redefinition logic unit is used for carrying out bit width conversion on the input data;
the data shift register unit is used for storing the output data of the data redefinition logic unit, wherein the data shift register unit comprises a plurality of data shift registers, and the output data of the data redefinition logic unit are sequentially stored in the plurality of data shift registers according to time sequence;
the first adder unit is used for performing addition operation on the output data of the data shift register unit according to the folding circuit structure;
the impulse response coefficient register file unit is used for writing the impulse response coefficient of the digital shaping filter;
the reconstruction completion flag register unit is used for sending a reconstruction completion signal under the condition that the order reconstruction register unit completes reconstruction;
the multiplier unit is used for multiplying the output data of the first adder unit according to the impulse response coefficient and receiving the output signal of the reconstruction completion flag register unit;
the second adder unit is used for adding the output data of the multiplier unit under the condition that the multiplier unit receives the reconstruction completion signal;
the order reconstruction register unit is used for writing the order of the digital shaping filter;
the sequential control logic unit is used for controlling the selection of the output logic unit selection result data according to the order reconstruction register unit;
and the selection output logic unit is used for outputting result data according to the control of the time sequence control logic unit.
According to the embodiment of the disclosure, the first adder unit is further configured to add data stored in an mth data shift register of the plurality of data shift registers and data stored in an nth data shift register according to a folding circuit structure in a case where an order is 2i, where i is an integer greater than 0, M ∈ [1,i ], N ∈ [ i +1,2i ], M, N are integers, and M + N =2i 1; and
and under the condition that the order is 2j-1, adding data stored in an X-th data shift register and data stored in a Y-th data shift register in the plurality of data shift registers according to a folding circuit structure, wherein j is an integer larger than 0, X belongs to [1,j-1], Y belongs to [ j +1,2j-1], X, Y is an integer, and X + Y =2j.
According to the embodiment of the disclosure, the multiplier unit is further configured to multiply data obtained by adding the first adder unit at an order of 2i and data of the impulse response coefficient register file unit; and
and respectively multiplying the data obtained by adding the first adder unit under the condition that the order is 2j-1 and the data in the j-th data shift register by the data in the shock response coefficient register file unit.
According to an embodiment of the present disclosure, the order reconstruction register unit is further configured to determine a reconstructed maximum order of the digital shaping filter according to a hardware structure of the digital shaping filter.
According to the embodiment of the present disclosure, a data transmission manner of the folding circuit structure adopts a multi-stage data pipeline manner, wherein the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all include a register structure, so that the digital shaping filter can output result data in each clock cycle.
According to an embodiment of the present disclosure, the above digital shaping filter further includes:
and carrying out fixed-point quantization on the impact response coefficient, and expressing the fixed-point quantization by using the following formula:
wherein D is 1 Representing the quantized impulse response coefficient, D 2 And C is a quantization base number, and K is the bit width of the quantization base number.
According to the embodiment of the disclosure, the data bit width stored by the order reconstruction register unit is configured to be determined according to the digital shaping filter;
a data bit width stored by the impulse response coefficient register file unit and configured to be determined according to the digital shaping filter;
the data bit width stored by the data shift register unit is configured to be the same as the data bit width output by the data redefinition logic unit;
the data bit width stored by the first adder unit is configured to be one bit more than the data bit width stored by the data shift register unit;
the data bit width stored by the multiplier unit is configured as the sum of the data bit width stored by the register in the first adder unit and the data bit width stored by the shock response coefficient register file unit;
the bit width of the data stored by the second adder unit is determined by the bit width of the output data of the multiplier unit.
According to an embodiment of the present disclosure, wherein the second adder unit stores a data bit width configured to add the bit width of the output data of the multiplier unit to the bit width of the output data of the first adder unit
Where H is the maximum order that the hardware structure of the shaping filter can support.
Another aspect of the present disclosure further provides a method for designing a digital shaping filter with an order dynamically reconfigurable folding circuit structure, including:
determining an impact response coefficient and a reconfigurable order according to the performance parameters of the digital shaping filter, and carrying out fixed-point quantization on the impact response coefficient;
inputting the impact response coefficient and the order after fixed point quantization into a digital shaping filter;
reconstructing and configuring an impact response coefficient register file unit and an order reconstruction register unit according to the bit width of a register in a digital shaping filter;
selecting a corresponding folding circuit structure according to the order, and calculating to obtain result data;
and outputting the result data.
According to the embodiment of the present disclosure, selecting a corresponding folding circuit structure according to the order to perform calculation to obtain result data includes:
under the condition that the order is 2i, a first adder unit adds data stored in an Mth data shift register and data stored in an Nth data shift register in a plurality of data shift registers according to a folding circuit structure, wherein i is an integer larger than 0, M belongs to [1,i ], N belongs to [ i +1,2i ], M, N is an integer, and M + N =2i +1; and
and under the condition that the order is 2j-1, the first adder unit adds data stored in an Xth data shift register in the plurality of data shift registers and data stored in a Yth data shift register according to a folding circuit structure, wherein j is an integer larger than 0, X belongs to [1,j-1], Y belongs to [ j +1,2j-1], X, Y is an integer, and X + Y =2j.
According to the embodiment of the disclosure, the order and the impulse response coefficient of the digital shaping filter are respectively written into the order reconstruction register unit and the impulse response coefficient register file unit, the digital shaping filter is reconstructed, and when the reconstruction is completed, the reconstruction completion flag register unit sends a signal to enable the digital shaping filter to start calculation and select and output result data to be output through the sequential control logic unit.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
figure 1 schematically illustrates a block diagram of an order dynamic reconfigurable folded circuit architecture digital shaping filter according to an embodiment of the present disclosure;
FIG. 2 schematically illustrates a flow diagram of a method of designing an order dynamically reconfigurable folded circuit architecture digital shaping filter according to an embodiment of the present disclosure; and
figure 3 schematically illustrates a flow diagram of a method for designing an order dynamically reconfigurable folded circuit architecture digital shaping filter according to yet another embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
Where a convention analogous to "A, B and at least one of C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B and C" would include, but not be limited to, systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a convention analogous to "A, B or at least one of C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B or C" would include, but not be limited to, systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).
In the related art, different systems need to design digital shaping filters with different filtering characteristics, and designers are often required to redesign and verify the digital shaping filters, which wastes a lot of time and energy. Particularly, in chip design of an Application Specific Integrated Chip (ASIC) or a System On Chip (SOC), reusability thereof as an important module is poor. Moreover, the digital shaping filter is designed by using a Field Programmable Gate Array (FPGA) more and more, and once the parameters of the digital shaping filter designed by the FPGA are selected, the circuit structure is fixed after synthesis, layout and wiring, and the parameters must be re-selected to change the characteristics of the digital shaping filter, so that a lot of time is wasted in re-synthesis, layout and wiring.
In view of the above, the present disclosure provides an order dynamically reconfigurable folding circuit structure digital shaping filter, in which an order and an impulse response coefficient of the digital shaping filter are written into an order reconfiguration register unit and an impulse response coefficient register file unit, respectively, the digital shaping filter is reconfigured, and when the reconfiguration is completed, a reconfiguration complete flag register unit sends a signal to start calculation of the digital shaping filter and select result data to be output through a sequential control logic unit.
Fig. 1 schematically illustrates a block diagram of an order dynamically reconfigurable folded circuit architecture digital shaping filter 100 according to an embodiment of the present disclosure.
As shown in fig. 1, the digital shaping filter 100 includes a data redefinition logic unit 101, a data shift register unit 102, a first adder unit 103, an impulse response coefficient register file unit 104, a reconstruction completion flag register unit 105, a multiplier unit 106, a second adder unit 107, an order reconstruction register unit 108, a timing control logic unit 109, and a selection output logic unit 110.
A data redefinition logic unit 101 for performing bit width conversion on the input data.
And a data shift register unit 102, configured to store the output data of the data redefinition logic unit, where the data shift register unit includes a plurality of data shift registers, and the output data of the data redefinition logic unit is sequentially stored in the plurality of data shift registers according to a time sequence.
And a first adder unit 103 for adding the output data of the data shift register unit according to the folding circuit structure.
And an impulse response coefficient register file unit 104 for writing the impulse response coefficients of the digital shaping filter.
And a reconstruction completion flag register unit 105, configured to send a reconstruction completion signal when the order reconstruction register unit completes reconstruction.
A multiplier unit 106, configured to perform multiplication operation on the output data of the first adder unit according to the impulse response coefficient and receive an output signal of the reconstructed flag register unit.
A second adder unit 107 for adding the output data of the multiplier unit when the multiplier unit receives the reconstruction completion signal.
And an order reconstruction register unit 108 for writing the order of the digital shaping filter.
And the time sequence control logic unit 109 is used for controlling and selecting the selection result data of the output logic unit according to the order reconstruction register unit.
The selection output logic unit 110 is used for outputting result data according to the control of the sequential control logic unit.
According to an embodiment of the present disclosure, the data redefinition logic unit 101 may perform a bit width transformation on the received data. For example, a received data "0" with a bit width of 1bit is converted into a data "11" with a bit width of 2bit by the data redefining logic unit 101; it is also possible to receive data "1" of 1bit width and convert the "1" into data "01" of 2bit width by the data redefinition logic unit 101.
According to the embodiment of the present disclosure, the input terminals of the data shift register unit 102 are connected to the output terminal of the data redefinition logic unit 101, the data shift register unit 102 may include a plurality of data shift registers, and the output data of the data redefinition logic unit may be output in time sequence and then stored in the corresponding data shift register in time sequence.
According to an embodiment of the present disclosure, an input of the first adder unit 103 is connected to an output of the data shift register unit 102, and the first adder unit 103 may add the output data of the data shift register unit.
According to an embodiment of the present disclosure, the first adder unit 103 may perform an addition operation by a folded circuit structure.
In accordance with an embodiment of the present disclosure, the impulse response coefficients of the digital shaping filter may be written by the processor to the impulse response coefficient register file unit 104.
According to an embodiment of the present disclosure, the reconstruction completion flag register unit 105 may send a reconstruction completion signal to the multiplier unit in case that the order reconstruction register unit of the digital shaping filter completes the reconstruction. The reconfiguration complete flag register unit may be invalid before the digital shaping filter is reconfigured, and the reconfiguration complete flag register unit is caused to issue a reconfiguration complete signal after the digital shaping filter is configured.
According to an embodiment of the present disclosure, an input of the multiplier unit 106 may be connected to the impulse response coefficient register file unit 104 and an output of the reconstruction completion flag register unit 105, and the multiplier unit 106 may receive an output signal of the reconstruction completion flag register unit 105.
According to an embodiment of the present disclosure, the multiplier unit 106 may multiply the output data of the first adder unit according to the impulse response coefficient, e.g., the impulse response coefficient may be multiplied by the output data of the first adder unit.
According to an embodiment of the present disclosure, an input of the second adder unit 107 may be connected with an output of the multiplier unit 106, and the second adder unit 107 may add the output data of the multiplier unit.
According to an embodiment of the present disclosure, the order of the digital shaping filter may be written into the order reconstruction register unit 108 by the processor.
According to the embodiment of the present disclosure, the input end of the timing control logic unit 109 is connected to the output end of the order reconstruction register unit 108, and the order of the digital shaping filter can be determined by the order reconstruction register unit 108, and then the selection output logic unit is controlled to select the result data at the corresponding timing.
According to an embodiment of the present disclosure, the selection output logic unit 110 is used for outputting result data according to the control of the timing control logic unit.
According to the embodiment of the disclosure, the order and the impulse response coefficient of the digital shaping filter are respectively written into the order reconstruction register unit and the impulse response coefficient register file unit, the digital shaping filter is reconstructed, and when the reconstruction is completed, the reconstruction completion flag register unit sends a signal to enable the digital shaping filter to start calculation and select and output result data to be output through the sequential control logic unit.
According to the embodiment of the disclosure, the first adder unit is further configured to add data stored in an mth data shift register and data stored in an nth data shift register of the plurality of data shift registers according to a folding circuit structure in a case where an order is 2i, where i is an integer greater than 0, M ∈ [1,i ], N ∈ [ i +1,2i ], M, N are integers, and M + N =2i 1.
And under the condition that the order is 2j-1, adding data stored in an X-th data shift register and data stored in a Y-th data shift register in the plurality of data shift registers according to a folding circuit structure, wherein j is an integer larger than 0, X belongs to [1,j-1], Y belongs to [ j +1,2j-1] and X, Y are integers, and X + Y =2j.
According to an embodiment of the present disclosure, for example, in the case that the order of the digital shaping filter is 6, three sets of data may be obtained by storing data in the data shift register unit through 6 data shift registers, and then adding data stored in the 1 st data shift register and data stored in the 6 th data shift register, adding data stored in the 2 nd data shift register and data stored in the 5 th data shift register, and adding data stored in the 3 rd data shift register and data stored in the 4 th data shift register through the first adder unit.
For another example, when the order of the digital shaping filter is 7, the data shift register unit may store data via 7 data shift registers, and then the first adder unit may add the data stored in the 1 st data shift register and the data stored in the 7 th data shift register, add the data stored in the 2 nd data shift register and the data stored in the 6 th data shift register, and add the data stored in the 3 rd data shift register and the data stored in the 5 th data shift register, thereby obtaining three sets of data.
According to the embodiment of the disclosure, the multiplier unit is further configured to multiply the data obtained by adding the first adder unit at the order of 2i and the data of the impulse response coefficient register file unit.
And respectively multiplying the data obtained by adding the first adder unit under the condition that the order is 2j-1 and the data in the j-th data shift register by the data in the shock response coefficient register file unit.
According to an embodiment of the present disclosure, the data of the impulse response coefficient register file cell may be an impulse response coefficient.
According to the embodiment of the present disclosure, for example, in the case where the order of the digital shaping filter is 6, three sets of data in the first adder are respectively multiplied by the impulse response coefficients, and three multiplication operations are required. If the data in the data shift register unit is directly multiplied by the impulse response coefficient without a folding circuit, six times of multiplication operation is needed.
For another example, in the case where the order of the digital shaping filter is 7, four multiplication operations are required to multiply the three sets of data in the first adder by the impulse response coefficients, respectively, and multiply the data stored in the 4 th data shift register by the impulse response coefficients, by the multiplier unit. If the data in the data shift register unit is directly multiplied by the impulse response coefficient without a folding circuit, seven times of multiplication operation are needed. Therefore, after the data shift register unit is subjected to addition operation through the folding circuit structure, half of multiplication operation logic resources are reduced, calculation resources are saved, and calculation efficiency is improved.
According to an embodiment of the present disclosure, the order reconstruction register unit is further configured to determine a reconstructed maximum order of the digital shaping filter according to a hardware structure of the digital shaping filter.
According to the embodiment of the disclosure, the hardware structure of the digital shaping filter determines the maximum order that the digital shaping filter can be reconfigured, and the hardware structure of the digital shaping filter can be designed into the maximum order and input to the order reconfiguration register unit, so that the order is dynamically reconfigurable in a range smaller than the maximum order, and theoretically, the greater the maximum order design of the digital shaping filter is, the greater the order selection range is in implementing.
According to the embodiment of the present disclosure, a data transmission manner of the folding circuit structure adopts a multi-stage data pipeline manner, wherein the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all include a register structure, so that the digital shaping filter can output result data in each clock cycle.
According to the embodiment of the disclosure, the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all comprise register structures, so that the digital shaping filter can store data in each unit, and a multistage data pipeline mode adopted by the digital shaping filter can enable each unit to perform calculation at the same time, so that a new operation result is output at each clock cycle. The calculation efficiency of the digital shaping filter and the subsequent working speed of signal processing are improved.
According to an embodiment of the present disclosure, the above digital shaping filter further includes:
the impulse response coefficients are quantized in fixed points and represented by the following equation:
wherein D is 1 Representing the quantized impulse response coefficient, D 2 And C is a quantization base number, and K is the bit width of the quantization base number.
According to the embodiment of the disclosure, when a hardware circuit of a digital shaping filter is designed in a fixed-point manner, an impulse response coefficient needs to be quantized in a fixed-point manner, and when the number of quantization bits is higher than 16 bits, the mean value of quantization errors in a passband of the digital shaping filter is less than 0.1, so that the design requirement can be met, unnecessary bit width waste can be avoided, and meanwhile, the requirement on precision can be guaranteed, and the impulse response coefficient can be quantized according to the following formula:
wherein D is 1 Representing the quantized impulse response coefficient, D 2 And C is a quantization base number, the quantization base number is the absolute value of the shock response coefficient with the minimum absolute value in the shock response coefficients, K is the bit width of the quantization base number, and the wider the bit number of the quantization base number is, the higher the precision is.
According to the embodiment of the disclosure, the data bit width stored by the order reconstruction register unit is configured to be determined according to the digital shaping filter.
The impulse response coefficient register file unit stores a data bit width configured to be determined according to the digital shaping filter.
The data shift register unit stores data bit width which is configured to be the same as the data bit width output by the data redefinition logic unit.
The first adder unit stores a data bit width configured to be one bit more than the data bit width stored by the data shift register unit.
The data bit width stored by the multiplier unit is configured to be the sum of the data bit width structure stored by the register in the first adder unit and the data bit width stored by the shock response coefficient register file unit.
The bit width of the data stored by the second adder unit is determined by the bit width of the output data of the multiplier unit.
According to the embodiment of the disclosure, the data bit width stored by the order reconstruction register unit and the data bit width stored by the impulse response coefficient register file unit can be set according to the characteristics and the precision requirement of the digital shaping filter.
According to the embodiment of the present disclosure, the data bit width stored in the data shift register unit may be the same as the data bit width output by the data redefinition logic unit, for example, the data bit width output by the data redefinition logic unit is 2 bits, and the data bit width stored in the data shift register unit is also 2 bits.
According to the embodiment of the present disclosure, the bit width of the data stored by the first adder unit may be one bit more than that of the data stored by the data shift register unit, for example, the bit width of the data stored by the data shift register unit is 2 bits, and the bit width of the data stored by the first adder unit may be 3 bits.
According to an embodiment of the present disclosure, the data bit width stored by the multiplier unit may be the sum of the data bit widths stored by the register structure and the impulse response coefficient register file unit in the first adder unit.
According to an embodiment of the present disclosure, wherein the second adder unit stores a data bit width configured to add the bit width of the output data of the multiplier unit to the bit width of the output data of the first adder unit
Where H is the maximum order that the hardware structure of the shaping filter can support.
Fig. 2 schematically illustrates a flow chart of a method of designing an order dynamically reconfigurable folded circuit architecture digital shaping filter according to an embodiment of the present disclosure.
As shown in fig. 2, the method includes operations S201 to S205.
In operation S201, impulse response coefficients and a reconfigurable order are determined according to performance parameters of a digital shaping filter, and the impulse response coefficients are quantized in a fixed point.
In operation S202, the impulse response coefficients after fixed-point quantization and the orders are input to a digital shaping filter.
In operation S203, the impulse response coefficient register file unit and the order reconstruction register unit are reconfigured according to the bit width of the register in the digital shaping filter.
In operation S204, a corresponding folded circuit structure is selected according to the order to perform calculation to obtain result data.
In operation S205, the result data is output.
According to the embodiment of the disclosure, the frequency response of the digital shaping filter satisfies raised cosine characteristics, matlab may be used to generate impulse response coefficients and orders of corresponding characteristics, the digital shaping filter may be implemented by a finite-length unit impulse response (FIR) digital filter, when Matlab is used to generate parameters, if the truncation length is L symbols, W samples (determined by a sampling rate) are taken in each symbol interval T, and at this time, LW samples are totally taken to represent the truncated filter impulse response. The truncation length L generated by the rcosine function of Matlab is generally 4-10 symbols, and it is necessary to make L meet the system performance requirement and make the order of the filter not too large, so as to save resources.
According to the embodiment of the disclosure, the order and the impulse response coefficient of the digital shaping filter can be written into the order reconstruction register unit and the impulse response coefficient register file unit by the processor, when the bit width of the written impulse response coefficient is smaller than the bit width of the designed impulse response coefficient register, the impulse response coefficient needs to be written into the high bit of the impulse response coefficient register file unit, and the remaining low bit needs to be written with 0.
According to the embodiment of the disclosure, the corresponding folding circuit structure can be selected by performing parity judgment on the data in the order reconstruction register.
According to the embodiment of the disclosure, the order and the impulse response coefficient of the digital shaping filter are respectively written into the order reconstruction register unit and the impulse response coefficient register file unit, the digital shaping filter is reconstructed, and when the reconstruction is completed, the reconstruction completion flag register unit sends a signal to enable the digital shaping filter to start calculation and select and output result data to be output through the sequential control logic unit.
According to the embodiment of the present disclosure, selecting a corresponding folding circuit structure according to the order to perform calculation to obtain result data includes:
under the condition that the order is 2i, the first adder unit adds data stored in an Mth data shift register and data stored in an Nth data shift register in the plurality of data shift registers according to a folding circuit structure, wherein i is an integer larger than 0, M belongs to [1,i ], N belongs to [ i +1,2i ], M, N is an integer, and M + N =2i +1.
And under the condition that the order is 2j-1, the first adder unit adds data stored in an Xth data shift register in the plurality of data shift registers and data stored in a Yth data shift register according to a folding circuit structure, wherein j is an integer larger than 0, X belongs to [1,j-1], Y belongs to [ j +1,2j-1], X, Y is an integer, and X + Y =2j.
According to the embodiments of the present disclosure, for example, in the case where the order of the digital shaping filter is 6, data may be stored in the data shift register unit through 6 data shift registers, and then data stored in the 1 st data shift register and data stored in the 6 th data shift register are added by the first adder unit, data stored in the 2 nd data shift register and data stored in the 5 th data shift register, and data stored in the 3 rd data shift register and data stored in the 4 th data shift register are added, resulting in three sets of data.
For another example, when the order of the digital shaping filter is 7, the data shift register unit may store data via 7 data shift registers, and then the first adder unit may add the data stored in the 1 st data shift register and the data stored in the 7 th data shift register, add the data stored in the 2 nd data shift register and the data stored in the 6 th data shift register, and add the data stored in the 3 rd data shift register and the data stored in the 5 th data shift register, thereby obtaining three sets of data.
Figure 3 schematically illustrates a flow diagram of a method for designing an order dynamically reconfigurable folded circuit architecture digital shaping filter according to yet another embodiment of the present disclosure.
As shown in fig. 3, the method may be applied to a signal processing system, a data transmission system, and the like, and includes operations S301 to S310.
In operation S301, characteristic parameters of the digital shaping filter are extracted according to the performance requirements of the system on the digital shaping filter.
In operation S302, an impulse response coefficient and an order corresponding to the characteristic parameter are generated by Matlab.
In operation S303, the impulse response coefficients are quantized in a fixed point according to the accuracy requirement of the system.
In operation S304, bit widths of respective units of the digital shaping filter are determined and a hardware system configuration design is performed.
In operation S305, an order register unit and an impulse response coefficient register file unit are configured.
In operation S306, it is determined whether the order is an even number, and in case that the order is determined to be an even number, operation S307 is performed, and in case that the order is determined to be an odd number, operation S308 is performed.
In operation S307, a calculation is performed by an even number corresponding to the folding circuit configuration.
In operation S308, a calculation is performed by an odd number of corresponding folding circuit structures.
In operation S309, it is determined whether the filter characteristic is changed after the parameter reconstruction is completed, and in the case where it is determined that the filter characteristic is changed, operation S305 is performed, and in the case where it is determined that the filter characteristic is not changed, operation S310 is performed.
In operation S310, the system outputs result data of the corresponding characteristic according to the configured parameter.
According to the embodiment of the disclosure, the characteristics of the digital shaping filter are changed by reconstructing the parameters of the digital shaping filter, the method is simple and flexible, the required digital shaping filter can be quickly generated on the basis of not changing a hardware circuit, the method can adapt to various systems with different frequencies and bandwidths, the repeated design is avoided, the resource waste is reduced, the design cost is saved, and the hardware module has reusability.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. A digital shaping filter of an order dynamically reconfigurable folded circuit architecture, comprising:
the data redefinition logic unit is used for carrying out bit width conversion on the input data;
the data shift register unit is used for storing the output data of the data redefinition logic unit, wherein the data shift register unit comprises a plurality of data shift registers, and the output data of the data redefinition logic unit are sequentially stored in the data shift registers according to a time sequence;
the first adder unit is used for adding the output data of the data shift register unit according to a folding circuit structure;
the impact response coefficient register file unit is used for writing the impact response coefficient of the digital shaping filter;
the reconstruction completion flag register unit is used for sending a reconstruction completion signal under the condition that the order reconstruction register unit completes reconstruction;
the multiplier unit is used for multiplying the output data of the first adder unit according to the order and receiving the output signal of the reconstruction completion flag register unit;
a second adder unit configured to add the output data of the multiplier unit when the multiplier unit receives the reconstruction completion signal;
the order reconstruction register unit is used for writing the order of the digital shaping filter;
the sequential control logic unit is used for controlling and selecting the selection result data of the output logic unit according to the order reconstruction register unit;
and the selection output logic unit is used for outputting the result data according to the control of the time sequence control logic unit.
2. The digital shaping filter according to claim 1,
the first adder unit is further configured to, when the order is 2i, add data stored in an mth data shift register and data stored in an nth data shift register of the plurality of data shift registers according to the folding circuit structure, where i is an integer greater than 0, M ∈ [1,i ], N ∈ [ i +1,2i ], M, N are integers, and M + N =2i +1; and
and under the condition that the order is 2j-1, adding data stored in an X-th data shift register and data stored in a Y-th data shift register in the plurality of data shift registers according to the folding circuit structure, wherein j is an integer larger than 0, X belongs to [1,j-1], Y belongs to [ j +1,2j-1], X, Y is an integer, and X + Y =2j.
3. The digital shaping filter according to claim 2,
the multiplier unit is further configured to multiply data obtained by adding the first adder unit in the case that the order is 2i, and data of the impulse response coefficient register file unit; and
and respectively multiplying the data obtained by adding the first adder unit under the condition that the order is 2j-1 and the data in the jth data shift register by the data in the shock response coefficient register file unit.
4. The digital shaping filter according to claim 1,
the order reconstruction register unit is further configured to determine a reconstructed maximum order of the digital shaping filter according to a hardware structure of the digital shaping filter.
5. The digital shaping filter of any one of claims 1 to 4,
the data transmission mode of the folding circuit structure adopts a multi-stage data pipeline mode, wherein the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all comprise register structures, so that the digital shaping filter can output the result data in each clock cycle.
6. The digital shaping filter of any of claims 1-4, further comprising:
performing fixed-point quantization on the impulse response coefficient, which is represented by the following formula:
wherein D is 1 Representing the quantized impulse response coefficient, D 2 And C is a quantization base number, and K is the bit width of the quantization base number.
7. The digital shaping filter of any one of claims 1 to 4,
the order reconstruction register unit stores data bit width which is configured to be determined according to the digital shaping filter;
the data bit width stored by the shock response coefficient register file unit is determined according to the digital shaping filter;
the data shift register unit stores data bit width which is configured to be the same as the data bit width output by the data redefinition logic unit;
the data bit width stored by the first adder unit is configured to be one bit more than the data bit width stored by the data shift register unit;
the data bit width stored by the multiplier unit is configured to be the sum of the data bit width stored by the register in the first adder unit and the data bit width stored by the shock response coefficient register file unit;
the data bit width stored by the second adder unit is determined by the bit width of the output data of the multiplier unit.
8. The digital shaping filter according to claim 7, wherein the second adder unit stores a data bit width configured to be added by a bit width of the output data of the multiplier unit
Wherein H is the maximum order that the hardware structure of the shaping filter can support.
9. A design method of a digital shaping filter with an order dynamic reconfigurable folding circuit structure comprises the following steps:
determining an impulse response coefficient and a reconfigurable order according to the performance parameters of the digital shaping filter, and carrying out fixed-point quantization on the impulse response coefficient;
inputting the impulse response coefficient after fixed point quantization and the order into the digital shaping filter;
reconstructing and configuring an impact response coefficient register file unit and an order reconstruction register unit according to the bit width of a register in the digital shaping filter;
selecting a corresponding folding circuit structure according to the order to calculate to obtain result data;
and outputting the result data.
10. The method of claim 9, wherein selecting the corresponding folding circuit structure according to the order for calculation to obtain result data comprises:
adding data stored in an Mth data shift register and data stored in an Nth data shift register among the plurality of data shift registers by using a first adder unit according to the folding circuit configuration in a case where the order is 2i,
i is an integer greater than 0, M is an integer of 1,i, N is an integer of i +1,2i and M, N, and
m + N =2i +1; and
in the case where the order is 2j-1, adding data stored in an X-th data shift register and data stored in a Y-th data shift register among the plurality of data shift registers by using a first adder unit according to the folding circuit configuration, wherein,
j is an integer greater than 0, X belongs to [1,j-1], Y belongs to [ j +1,2j-1], X, Y are integers, and
X+Y＝2j。
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