CN114647817A - FPGA-based acceleration method for replacing time domain cross correlation by frequency domain convolution - Google Patents
FPGA-based acceleration method for replacing time domain cross correlation by frequency domain convolution Download PDFInfo
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- CN114647817A CN114647817A CN202210232651.8A CN202210232651A CN114647817A CN 114647817 A CN114647817 A CN 114647817A CN 202210232651 A CN202210232651 A CN 202210232651A CN 114647817 A CN114647817 A CN 114647817A
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- G06F17/15—Correlation function computation including computation of convolution operations
- G06F17/156—Correlation function computation including computation of convolution operations using a domain transform, e.g. Fourier transform, polynomial transform, number theoretic transform
Abstract
The invention discloses an acceleration method for replacing time domain cross correlation by frequency domain convolution based on an FPGA (field programmable gate array), belonging to the technical field of signal processing. The invention respectively carries out FFT operation steps on two groups of arrays with the same number of points, carries out frequency domain window taking and IFFT operation steps according to requirements, carries out time domain sequence zero padding for correct calculation on hardware, carries out FFT operation steps, carries out conjugate multiplication on the arrays on the two groups of frequency domains, carries out IFFT operation steps, and finally searches the maximum value of a real part. The invention can greatly reduce the times of multiplication, accelerate the operation time and reduce the use amount of resources, and really realize low delay and high efficiency. And under the condition of multipoint number, the algorithm superiority can be better reflected compared with the time domain cross-correlation.
Description
Technical Field
The invention relates to the field of digital signal processing, in particular to an acceleration algorithm for replacing time domain cross correlation by frequency domain convolution based on an FPGA (field programmable gate array).
Background
The cross-correlation algorithm is easy to realize in the lower computer, but the calculation efficiency is greatly reduced along with the increase of the number of points. Although the conjugate convolution is performed in the frequency domain to replace the cross-correlation calculation in the time domain, and the calculation speed can be improved when the number of points is large, the FFT and the IFFT need to be used for many times when the problems of window selection in the frequency domain and the like are involved. When the method is realized on a lower computer, each FFT and IFFT is accompanied by certain precision loss, and the final result can be influenced after accumulation.
In the prior art, CN108089839A discloses a method for implementing cross-correlation operation based on FPGA, which has the following two main features: 1. the method has the advantages that the characteristic that FPGA hardware resources are rich and parallel computation is easy to realize is utilized, and a hardware circuit is adopted to realize cross-correlation operation of two paths of signals; 2. compared with the traditional method of taking single data from the RAM address of the FPGA to perform multiply-accumulate operation, the method has higher speed and efficiency, can fully utilize the characteristic of parallel operation of the FPGA, and reduces the operation time. However, the above method requires a large number of multiplication operations, occupies a large number of multiplier resources, causes a large time delay of the system, and has low efficiency. Therefore, a method capable of saving multiplier resources and optimizing time sequence is urgently needed, and the performance of the algorithm is improved.
CN 112597432A discloses an acceleration implementation method and system of complex sequence cross-correlation based on FFT algorithm on FPGA, which is equivalent to conjugate multiplication of corresponding frequency spectrum on frequency domain by cross-correlation calculation of two groups of arrays on time domain. The computation amount required by the latter to realize the hardware is far less than that of the former, so that the performance of the hardware realization can be greatly optimized. The method is feasible in software, and the implementation process in hardware needs to be improved. Due to the mathematical formula h (t) ═ f in its design1(t)*f2(-t)，H(ω)＝F1(ω)×Conj(F2(ω)) the cross-correlation operation is zero-padded by default for the parts without signal, and therefore changes are made in hardware as well.
Disclosure of Invention
The invention aims to provide an acceleration algorithm for replacing time domain cross-correlation by frequency domain convolution based on an FPGA (field programmable gate array), which is used for solving the problems of large time delay of a system and incomplete equivalence in hardware conversion caused by large number of multiplication operations occupied by the realization of the existing cross-correlation.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an acceleration method for replacing time domain cross-correlation by frequency domain convolution based on FPGA is characterized by comprising the following steps:
(1) an FFT operation step: converting two groups of signal arrays to be mutually correlated from a time domain to a frequency domain by utilizing an FFT algorithm in the FPGA device, and storing the two groups of signal arrays;
(2) a frequency domain windowing step: carrying out window selection on the frequency domain according to actual requirements to finish the filtering process;
(3) IFFT operation step: converting the windowed frequency domain array into a time domain by using an IFFT algorithm;
(4) time domain sequence zero padding: adding an equal number of 0 before the first group of time domain data and adding an equal number of 0 after the second group of time domain data so as to ensure the calculation correctness when the hardware is realized;
(5) an FFT operation step: converting the two groups of zero-padded arrays from a time domain to a frequency domain by using an FFT algorithm;
(6) conjugate multiplication step: conjugate multiplication is carried out on the array converted into the frequency domain;
(7) an IFFT operation step: converting the frequency domain array after conjugate multiplication into a time domain;
(8) finding the real part maximum: finding the subscript of the maximum value of the real part in the array for outputting;
(9) repeating the processes of the steps (2) to (8) until all the results needing to be windowed are obtained, and ending.
Preferably, in step (1), the two sets of signal arrays are equal in length and are an integer power of 2.
Preferably, in step (2), the windowing includes one or more of low-pass filtering, high-pass filtering, and band-pass filtering of the frequency domain signal.
Compared with the prior art, the invention has the following beneficial effects:
compared with the traditional direct time domain correlation operation, the invention greatly reduces the multiplication operation amount, reduces the use amount of logic resources, achieves low time delay and high efficiency, greatly reduces the occupation of multiplier resources for FPGA hardware, optimizes the FPGA time sequence, saves the hardware resources, solves the problem of overlarge multiplication operation amount in the existing correlation operation process, and can ensure that the hardware of the FPGA system exerts the best performance.
Compared with the prior method for realizing acceleration of complex sequence cross-correlation on FPGA of FFT algorithm, the invention not only increases the preprocessing link of window selection on frequency spectrum, but also ensures the correctness of operation on hardware by the method of zero filling on the original data, thereby really realizing the accurate transplantation of the algorithm.
The invention is suitable for all occasions needing to use hardware to realize the data signal processing of the cross-correlation calculation, greatly improves the performance of the system, and ensures that the FPGA uses less resources and realizes a lower clock period required by the algorithm.
Drawings
FIG. 1 is a flow chart of an acceleration method according to the present invention.
Fig. 2 is a schematic diagram of a specific implementation of the zero padding step of the time domain sequence.
FIG. 3 is a block diagram of modules deployed in an FPGA.
Detailed Description
The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
As shown in fig. 1, the method for accelerating the time-domain cross-correlation by frequency-domain convolution based on FPGA in this embodiment includes the following steps:
FFT operation step: and respectively converting the two groups of signal arrays from a time domain to a frequency domain by using an FFT algorithm, and storing data for later use for multiple times.
Frequency domain window taking: and carrying out window-taking operation on the frequency domain according to actual requirements to finish the filtering process.
IFFT operation step: and converting the windowed frequency domain array into a time domain by using an IFFT algorithm.
And (3) zero filling of a time domain sequence: and adding an equal number of 0 before the first group of time domain data and adding an equal number of 0 after the second group of time domain data so as to ensure the correctness of calculation when the method is implemented on hardware.
FFT operation step: and converting the two groups of zero-padded arrays into the frequency domain from the time domain by using an FFT algorithm.
Conjugate multiplication step: the array converted to the frequency domain is subjected to conjugate multiplication.
IFFT operation step: and converting the conjugate multiplied frequency domain array into a time domain.
Finding the maximum value of the real part: and finding the subscript of the maximum value of the real part in the array for outputting.
And repeating the process from the frequency domain window taking step to the real part maximum value searching step until all the results needing window taking are obtained, and finishing the process.
The following is a detailed description of the implementation of the present invention with specific examples.
Assume that a (n) and b (n) are two sets of AD data collected, each of which has a length of 8192.
FFT operation is performed on the two groups of numbers to obtain A (n) and B (n). Suppose that the data retained after the window is A1, A2, A3, A4, A5, A8187, A8188, A8189, A8190, A8191 and B1, B2, B3, B4, A5, B8187, B8188, B8189, B8190, B8191, and the rest are all set to 0.
The two groups of numbers after the window extraction are subjected to IFFT operation, and the obtained two groups of numbers are denoted as c (n) and d (n), and the lengths are 8192.
Zero padding is performed on c (n) and d (n), and the specific method is as shown in fig. 2, equal number of 0 is added before the first group of time domain data, equal number of 0 is added after the second group of time domain data, the arrays obtained after zero padding are marked as e (n) and f (n), and the lengths are 16384.
FFT operations are performed on the arrays e (n) and f (n) respectively to obtain E (n) and F (n).
Conjugate multiplying the elements corresponding to E (n) and F (n) to obtain G (n) with the length of 16384.
IFFT operation is performed on the array G (n) to obtain an array g (n) in the time domain, and the length is 16384.
And finding out subscripts of the maximum values of the real parts of g and n, and sending the subscripts to an upper computer through a serial port.
And repeating the process until all the results needing window extraction are obtained, and ending the process.
Taking this example as an example, for the FFT operation step, conjugate multiplication step, IFFT operation step, such as the calculation method using time domain cross-correlation, the required time complexity is O (n)2) However, the time complexity required by the method of the present invention is O (n × logn), and in the case where n (8192 in this example) is largeThe efficiency improvement is obvious. Therefore, the invention can greatly reduce the times of multiplication, accelerate the operation time and reduce the use amount of resources, and really achieves low time delay and high efficiency. And under the condition of multipoint number, the algorithm superiority can be better reflected compared with the time domain cross-correlation.
The foregoing lists merely illustrate specific embodiments of the invention. It is obvious that the invention is not limited to the above embodiments, but that many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the present invention are to be considered within the scope of the invention.
Claims (3)
1. An acceleration method for replacing time domain cross-correlation by frequency domain convolution based on FPGA is characterized by comprising the following steps:
(1) an FFT operation step: converting two groups of signal arrays to be mutually correlated from a time domain to a frequency domain by utilizing an FFT algorithm in the FPGA device, and storing the two groups of signal arrays;
(2) a frequency domain windowing step: carrying out window selection on the frequency domain according to actual requirements to finish the filtering process;
(3) IFFT operation step: converting the windowed frequency domain array into a time domain by using an IFFT algorithm;
(4) time domain sequence zero padding: adding an equal number of 0 before the first group of time domain data and adding an equal number of 0 after the second group of time domain data so as to ensure the calculation correctness when the hardware is realized;
(5) an FFT operation step: converting the two groups of zero-padded arrays from a time domain to a frequency domain by using an FFT algorithm;
(6) conjugate multiplication step: performing conjugate multiplication on the array converted into the frequency domain;
(7) IFFT operation step: converting the frequency domain array after conjugate multiplication into a time domain;
(8) finding the real part maximum: finding the subscript of the maximum value of the real part in the array for outputting;
(9) repeating the processes of the steps (2) to (8) until all the results needing window taking are obtained, and ending.
2. The method of claim 1, wherein in step (1), the two sets of signal arrays are equal in length and are an integer power of 2.
3. The method of claim 1, wherein in step (2), the windowing comprises one or more of low-pass filtering, high-pass filtering, and band-pass filtering of the frequency domain signal.
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