CN109743125B - Circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation - Google Patents
Circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation Download PDFInfo
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Abstract
The invention relates to a circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation, which comprises a large step delay module group, wherein the large step delay module group comprises a plurality of large step delay modules, and the output ends and the input ends of the large step delay modules are sequentially connected in series; the small step integer delay module group comprises a plurality of multi-phase shift registers, and the input ends of the shift registers are respectively connected with the output ends of the large step delay modules; the decimal time delay module group comprises a plurality of decimal time delay modules, and the input ends of the decimal time delay modules are respectively connected with the output ends of the plurality of shift registers. The circuit structure is adopted to carry out multiphase processing on the data so as to realize the processing of high-speed data under a low-speed clock, realize the multipath delay function of the channel simulator and the processing capacity of ultra-large bandwidth, and have higher delay resolution so as to meet the functional requirement of the channel simulator.
Description
Technical Field
The invention relates to the field of digital signal processing, in particular to the field of channel simulators and channel multipath delay, in particular to a circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation.
Background
With the evolution of wireless communication technology, the 5 th generation communication system enters a verification stage at the same time, the test and verification work of wireless communication equipment becomes more and more complex, and the channel simulator can simulate the physical characteristics and environmental characteristics of an actual wireless channel in a laboratory environment, so that the test efficiency of the wireless equipment and network facilities can be greatly improved by using the channel simulator.
In order to simulate the characteristics of a wireless channel, a channel simulator needs to simulate transmission paths of a plurality of spatial signals and impart different delays to the paths. Meanwhile, as the bandwidth of wireless communication is higher and higher, the capacity of realizing high-speed data processing is required to adapt to the increase of the bandwidth, but the processing rate of the FPGA chip is difficult to meet the current requirement due to the limitation of the physical condition of the FPGA chip, so that the data needs to be subjected to multiphase processing so as to realize the processing of the high-speed data under a low-speed clock.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a circuit structure which has high resolution, strong processing capacity and simple structure and realizes accurate delay processing aiming at ultra-large bandwidth wireless channel simulation.
In order to achieve the above purpose, the circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation of the invention is as follows:
The circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation is mainly characterized by comprising the following components:
The large step delay module group comprises a plurality of large step delay modules, and the output ends and the input ends of the large step delay modules are sequentially connected in series and are used for outputting data of different delay values;
The small step integer delay module group comprises a plurality of multi-phase shift registers, wherein the input ends of the shift registers are respectively connected with the output ends of the large step delay modules and are used for rearranging data of each phase;
the decimal delay module group comprises a plurality of decimal delay modules, and the input ends of the decimal delay modules are respectively connected with the output ends of the plurality of shift registers and are used for obtaining decimal delay with high precision.
Preferably, the large step delay module is a dual-port random access memory or a FIFO memory, and is used for storing data in the large step delay process.
Preferably, the large step delay module constructs a dual-port random access memory or a FIFO memory through a block random access memory.
Preferably, the output end of the large step delay module is connected with a register for dividing an overlong data transmission path.
Preferably, the shift register is connected in series by a plurality of registers.
Preferably, the fractional delay module comprises a Farrow filter for performing fractional delay on the data.
Preferably, the large step delay module group divides the data into n paths of parallel processing, wherein n is any integer not less than 2.
Preferably, the working clock of the large step delay module is one n times of the data rate.
Preferably, the small step integer delay module calculates a small step integer delay result through the length of the shift register and the delay value.
The circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation is adopted to carry out multiphase processing on data so as to realize the processing of high-speed data under a low-speed clock. The circuit structure of the technical scheme realizes the multipath delay function of the channel simulator and realizes random delay on data of each path; realizing the processing capacity of ultra-large bandwidth. The FPGA-based high-speed data processing method has the advantages that the high-speed data processing is realized based on the FPGA, and the high-speed data processing method has high delay resolution, so that the functional requirements of a channel simulator are met.
Drawings
Fig. 1 is a schematic diagram of parallel multipath processing of a circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation in the invention.
Fig. 2 is a block diagram of a multi-path delay structure of a circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to the present invention.
Fig. 3 is a schematic diagram of a shift register of a circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to the present invention.
Fig. 4 is a shift register delay schematic diagram of an embodiment of a circuit structure for implementing accurate delay processing for ultra-large bandwidth wireless channel emulation according to the present invention.
Fig. 5 is an integer delay actual measurement effect diagram of a circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation.
Fig. 6 is a diagram of simulation results of a Farrow filter of the circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation in the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
The circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation comprises the following components:
The large step delay module group comprises a plurality of large step delay modules, and the output ends and the input ends of the large step delay modules are sequentially connected in series and are used for outputting data of different delay values;
The small step integer delay module group comprises a plurality of multi-phase shift registers, wherein the input ends of the shift registers are respectively connected with the output ends of the large step delay modules and are used for rearranging data of each phase;
the decimal delay module group comprises a plurality of decimal delay modules, and the input ends of the decimal delay modules are respectively connected with the output ends of the plurality of shift registers and are used for obtaining decimal delay with high precision.
As a preferred embodiment of the present invention, the large step delay module is a dual-port random access memory or FIFO memory, and is used for data storage in the large step delay process.
As a preferred embodiment of the invention, the large step delay module constructs a dual-port random access memory or FIFO memory through a block random access memory.
As a preferred embodiment of the present invention, the output end of the large step delay module is connected to a register, so as to divide an excessively long data transmission path.
As a preferred embodiment of the present invention, the shift register is connected in series by a plurality of registers.
As a preferred embodiment of the present invention, the fractional delay module includes a Farrow filter for performing fractional delay on the data.
As a preferred embodiment of the invention, the large step delay module group divides data into n paths of parallel processing, wherein n is any integer not less than 2.
As a preferred embodiment of the present invention, the working clock of the large step delay module is one n times of the data rate.
As a preferred embodiment of the invention, the small step integer delay module calculates a small step integer delay result through the length of the shift register and the delay value.
In the specific embodiment of the invention, as shown in fig. 1, original high-speed data are converted into four paths of data with different phases, and the four paths of data are respectively processed, so that the internal processing speed of the FPGA can be reduced to one fourth of the original processing speed. The invention provides a multipath parallel data delay scheme of a channel simulator, which is shown in figure 2, and mainly comprises three parts, namely a large step delay module, a small step integer delay module and a decimal delay module.
The large step delay module is constructed by a dual-port RAM or FIFO based on a Block RAM, the output data of the upper stage module is used as the input of the lower stage module through the serial connection of a plurality of large step modules, so that longer data delay is realized, the output data of each stage module is used as each sub-path of a multipath channel model, and the output data is output to the small step delay module and the decimal delay module which are finer later.
The small-step integer delay module is composed of a multi-phase shift register set, is configured according to different delay time lengths, translates configured delay values into addresses, and rearranges data of each phase to realize delay precision of corresponding data rate.
The decimal delay module is based on a Farrow filter and can delay decimal with higher precision.
The invention provides a method for delay processing of digital signals, which realizes multipath delay processing of ultra-large bandwidth and high-speed data. Firstly, a single high-speed data stream is split into parallel multi-path data streams with multiple phases, so that the data processing rate is reduced, and the realizability on an FPGA is ensured.
Firstly, a Block RAM is used for constructing a dual-port RAM or FIFO (first in first out) for data storage in a large step delay process, for example, the storage depth of a single RAM/FIFO is set to 1024, the data bit width is 32 bits, the speed is 1105.92MHz, each data speed and the corresponding processing logic working clock thereof are 276.48MHz under the assumption that data are divided into 4 paths of parallel processing, and the data bit width stored in the corresponding RAM/FIFO is 4 multiplied by 32 and is 128 bits. The circuit structure of the scheme does not need to limit the number of data branches, the data can be divided into any number greater than or equal to 2, and the data can be divided into 2 paths and 8 paths in one case of the embodiment of the 4-path scheme. It is assumed that the data is divided into n paths, and accordingly, the data rate becomes one-n.
In order to realize multipath data and large delay data with different delays, a plurality of large step delay modules are exemplified, the modules are connected in series, the output data of the former stage module is used as the input data of the latter stage module, the output of each stage module is used as the data of each sub path of a multipath channel model, and the later logic performs more accurate delay and other calculation operations. Since the working clock of the delay module is only one fourth of the data rate, the data delay correspondingly changes by 4 when the delay value of the delay module changes by 1, namely the delay resolution of the module is one fourth of the data rate. Meanwhile, since the Block RAM in the FPGA chip is distributed more dispersedly, after the multi-stage Block RAM is connected in series, the data transfer path may be longer, resulting in timing violations, so that one stage or multi-stage register buffer needs to be added at the output end of each module to divide the overlong data transfer path, which brings extra limitation to multipath delay, namely, extra delay exists between two adjacent paths.
In order to compensate for the lower delay resolution of the large step delay module and the additional delay between adjacent paths, the data of each path is subjected to small step integer delay. As shown in fig. 3, a plurality of shift registers are constructed, and each phase data is input to each shift register. Each shift register is formed by connecting L registers in series, each digital clock period is that each register data moves rightwards once, the rightmost register is defined as '0 th column', the leftmost register is defined as 'L-1 st column', and the larger the serial number of the column is, the later the moment of representing the data in the register is. The current data is assumed to be divided into P phases, corresponding to P shift registers. The module can realize integer delay with any length in the range of 0 to P (L-1), the delay length required to be realized at present is assumed to be D, D= {0,1,2,3, … …, P (L-1) }, the sum of the delay length D and the current phase sequence number P is calculated for data (p= {0,1,2, … …, P-1 }) of any phase P, the total phase number P is divided, the remainder obtained by dividing is the new phase sequence number P 'corresponding to the path of data after delay, and the divided integer corresponds to the sequence number t' of the L column of the shift register. For each path of phase data, corresponding P ' and t ', P to P ' are obtained according to the delay value D, if the positions of the registers of the module are represented by coordinates (t, P), the P groups of new coordinates (t ', P ') obtained by calculation according to D correspond to the P registers, and the values of the registers are the results after the delay of D data periods.
For example, assume that the current data is divided into 3 phases of parallel data, i.e., p=3, shift register length l=4, delay number d=7, for three phases of current numbers 0, 1, 2:
when p=0, (7+0)/(3=2 by 1), p '=1, t' =2.
When p=1, (7+1)/(3=2 by 2), p '=2, t' =2.
When p=2, (7+2)/(3=3 by 0), p '=0, t' =3.
As shown in fig. 4, the three sets of (t ', p') coordinates obtained by the above calculation correspond to the register value which is the data after the delay 7, that is, the result of the small step integer delay.
The structure realizes integer delay of any value, and takes 1105.92MHz data as an example, the delay resolution reaches 0.9 nanoseconds. After that, a Farrow filter is constructed, and the data is subjected to decimal delay, so that higher-precision delay is realized. Taking fractional delay bit width of 8 bits as an example, after delay by a Farrow filter, the delay resolution can reach 0.0035 nanoseconds.
Fig. 5 shows the actual measurement effect of integer delay, the original data is a monopulse signal with 552.96MHz sampling rate, we realize three sub-paths, the delay is respectively set to 0, 7 and 8, and the amplitude ratio of the three sub-paths is 4:2:1, the result of superposition of three sub paths is shown in the figure, and it can be seen that the preset delay value is realized. The fractional delay Farrow filter is based on the interpolation principle, is not suitable for monopulse signals, and only integer delay is carried out in the above experiment. Fig. 6 shows simulation results of a Farrow filter, in which dark blue lines are original data, fractional delays of light blue lines are theoretical values, and black dotted lines are delay results of the Farrow filter.
The circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation is adopted to carry out multiphase processing on data so as to realize the processing of high-speed data under a low-speed clock. The circuit structure of the technical scheme realizes the multipath delay function of the channel simulator and realizes random delay on data of each path; realizing the processing capacity of ultra-large bandwidth. The FPGA-based high-speed data processing method has the advantages that the high-speed data processing is realized based on the FPGA, and the high-speed data processing method has high delay resolution, so that the functional requirements of a channel simulator are met.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (8)
1. A circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation is characterized in that the circuit structure comprises:
The large step delay module group comprises a plurality of large step delay modules, and the output ends and the input ends of the large step delay modules are sequentially connected in series and are used for outputting data of different delay values;
The small step integer delay module group comprises a plurality of multi-phase shift registers, wherein the input ends of the shift registers are respectively connected with the output ends of the large step delay modules and are used for rearranging data of each phase;
the decimal delay module group comprises a plurality of decimal delay modules, and the input ends of the decimal delay modules are respectively connected with the output ends of the plurality of shift registers and are used for obtaining decimal delay with high precision;
The large stepping delay modules are connected in series, the output data of the former stage module is used as the input data of the latter stage module, and the output of each stage module is used as the data of each sub-path of the multipath channel model; the output end of each large stepping delay module is added with one-level or multi-level register cache;
the large step delay module group divides data into n paths of parallel processing, wherein n is any integer not less than 2.
2. The circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation according to claim 1, wherein the large step delay module is a dual-port random access memory or a FIFO memory and is used for data storage in a large step delay process.
3. The circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to claim 1, wherein the large step delay module constructs a dual-port random access memory or a FIFO memory through a block random access memory.
4. The circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to claim 1, wherein the output end of the large step delay module is connected with a register for dividing an overlong data transmission path.
5. The circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to claim 1, wherein the shift register is connected in series by a plurality of registers.
6. The circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to claim 1, wherein the fractional delay module comprises a Farrow filter for performing fractional delay on data.
7. The circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to claim 1, wherein the working clock of the large step delay module is one-nth of the data rate.
8. The circuit structure for realizing accurate delay processing for ultra-large bandwidth wireless channel simulation according to claim 1, wherein the small step integer delay module calculates a small step integer delay result through a shift register length and a delay value.
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