JP2002050981A - Digital matched filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital matched filter of low power consumption type that is used at a reception equipment of direct spread spectrum communication method. SOLUTION: The digital matched filter composed of the following units is provided; a timing controller (48) which operates in synchronism with an external clock, a plurality of complex registers (52) of which storage operation for input signals is controlled by the timing controller, a selector (58) which receives signals from each of the plurality of registers with a timing controlled by the timing controller, and a complex computing element (37) which computes predetermined coefficients, and further is provided respectively with a plurality of delay circuits (46) arrayed in series bringing about prescribed delayed outputs, and a complex arithmetic device (38) which computes output signals from each delay circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal receiving apparatus used in a communication system based on, for example, a direct sequence code division multiple access (DS? CDMA) system, and more particularly, to a receiving apparatus in such a receiving apparatus. The present invention relates to a low power consumption digital matched filter to be used.

[0002]

2. Description of the Related Art Spread spectrum communication is a communication in which the spectrum of an information signal is spread over a wide band using a spreading code and transmitted. Separated. Of these, direct spreading is a method of performing spectrum spreading by multiplying an information signal to be transmitted by a spreading code. Direct spread spectrum communication has various features such as anti-jamming, anti-interference, low interception rate, anti-multifading, and multiple access. These properties are very favorable properties for mobile communication. As a connection method between a mobile station and a base station, a method of identifying a mobile station or a base station by a spreading code used for spread spectrum is adopted. This connection method is a code division multiple access (CDMA).
iple Access) method.

FIG. 1 shows a very simplified block diagram of a spread spectrum receiving apparatus. Antenna 2
The received RF signal is subjected to detection processing in the RF unit 4, and the signal dropped to the intermediate frequency in the IF unit 6 is despread by the despreader 8. Rake demodulator 1
Received data is obtained by rake demodulation with 0.

The digital matched filter according to the present invention can be used in the despreader 8.

Next, the spreading code will be described. Although the third generation mobile communication system is currently under development, an example of its specification has been released by the 3GPP organization, according to which the structure of the synchronization channel (SCH) is as shown in FIG.

[0006] As a first step, a mobile station transmits a signal to a base station (Base station).
Station) and reliably receive the synchronization channel (SCH) signal transmitted from the primary search code (PSC, Prima
ry Search Code) Cp must be detected to detect slot timing. Next, as a second step, a secondary search code (SSC, Secondary Search Code) Cs
To detect the frame timing and the scramble code group number. Finally, as a third step, the common pilot channel (CPICH, Common Pilot CHanne
l) to detect the scramble code number.
In FIG. 2, the coefficient a of Cp and Cs may be regarded as 1.

In the first stage, a matched filter is usually required to detect the primary search code. The slot timing can be detected using the absolute value of the output of the matched filter. In the prior art, the matched filter requires a large-scale circuit and consumes large power. In 3GPP, by using a hierarchical, so-called generalized hierarchical Golay code as a primary search code, the number of adders can be reduced, and the power consumption of a matched filter can be reduced.

In order to generate a primary search code, a sequence a and a Golay complementary sequence g are defined as follows.

[0009]

A = <x1, x2, x3,…, x16> = <1, 1, 1, 1, 1, 1, -1, -1, 1, -1, 1, -1, 1,- 1,
-1, 1>

[0010]

[Equation 2] g = <g1, g2, g3,…, g16> = <1, 1, 1, -1, -1, 1, -1, -1, 1, 1, 1, -1, 1, -1,
1, 1> The primary search code Cp is defined as follows.

[0011]

Cp = (1 + j) X <ag1, ag2, ag3, ag4, ag5, ag6, ag7, ag8, ag9, ag10, ag11, ag12, ag13, ag14, ag15, ag16> = (1 + j ) X <a, a, a, -a, -a, a, -a, -a, a, a, a, -a, a, -a, a, a> where X means complex multiplication . FIG. 3 shows an example of a conventional double matched filter for detecting such a primary search code in a despreader of a receiver.
In the matched filter 32 shown in FIG. 3, a product obtained by multiplying the received complex signal (I + jQ) by a coefficient x16, that is, 1 by a multiplying element 33 is sent to a complex adder 34, and at the same time, it is delayed by a delay 35 Is delayed by a time D (delay of one chip) by a complex delay element, and the result of multiplication by x15, that is, −1 by the multiplication element is sent to the adder. The output from the delay unit 35 is further delayed by the time D by the delay unit on the right side and processed similarly. The signal output from the last fifteenth delay is delayed by a total of 15D (15 chips), and x1
That is, it is multiplied by 1 and sent to the complex adder 34. Since the entire output signal added in the complex adder 34 corresponds to the above equation 1, it has a peak corresponding to the sequence (1 + j) xa.

Next, the output 01 from the matched filter 32
, The same processing as above is performed in the matched filter 36. However, the delay amount by one delay unit 39 is 16D
(A 16-chip complex delay element), and the coefficient to be multiplied is the g-sequence in Equation 2. The output from each delay unit 39 is g
The calculation is performed by the series of calculation elements 37 and sent to the complex calculator 38. The complex calculator 38 can add all inputs, add according to the magnitude of the carrier frequency offset, or selectively add according to the instruction of the external control signal. In this way, the output from the complex adder 38, which is a complex operation unit, corresponds to Expression 3, and therefore becomes a correlation output having a peak corresponding to Cp. This correlation output signal can be used in a subsequent rake demodulator or the like.

[0013]

Generally, the delay units 35, 3
No. 9 uses a shift register as a delay element, so that a register element and a shift operation are required by the amount of delay, and power consumption in each register element is proportional to the shift operation frequency (several megahertz). The delay unit 39 must be delayed by 16 chips, and the chip rate clock is fast, so that power consumption is remarkable. Therefore, an object of the present invention is to provide a digital matched filter with reduced power consumption.

[0014]

In order to achieve the above object, a matched filter according to the present invention comprises: a timing controller (48) operating in synchronization with an external clock; and a timing controller for storing an input signal. Multiple controlled complex registers (52)
A selector (58) for receiving a signal from each of the plurality of complex registers at a timing controlled by the timing controller, and a complex operation element (37) for calculating a predetermined coefficient. A plurality of delay circuits arranged in series to provide an output (46)
And an arithmetic unit (3) for calculating an output signal from each delay circuit
8) and;.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. A configuration corresponding to a combination of one complex delay unit 39 and a complex multiplier 37 in the matched filter 36 in FIG. 3 is shown by blocks 1 to 15 in FIG.
The function of each block is to delay the received complex signal by 16D, multiply the result by a coefficient g, and output the result to the complex adder 38. The delay operation of each block is controlled by the timing controller 48. The timing controller 48 receives the chip rate clock,
It operates in synchronization with this. By using an element other than the shift register as a delay element in each block, power consumption can be reduced. FIG. 5 shows an example of such a delay element.

FIG. 5 shows a block corresponding to block 1 in FIG. In the block, 17 registers 52 each corresponding to one chip and including two real parts and two imaginary parts are arranged in parallel. A signal 01 from the matched filter 32 is connected to each of the registers R1, R2, R3,..., R17, and is stored in each of the registers at a timing controlled by the timing controller 48. For example, at the first timing, the signal of the first chip is stored in the register R1, and at that time, all the other registers are in a non-storable state. At the next timing, the signal for the second one chip is stored in the register R2, and at that time, the other registers are in a non-storable state.

When the 16th one-chip signal is stored in the register R16, the output signal from the register R1 is received by the selector 58 controlled by the timing controller 48 at the next one-chip timing. On the other hand, the seventeenth signal from the matched filter 32 is stored in the register R17. At the next timing, the register R1 stores the input signal, and the selector 58 receives the signal from the register R2. As a result, the output from selector 58 is one input to each register.
That is, it is delayed by 6D. Each register R1 to R17
Requires only one input / output operation for 17 chip times, so that the power consumption of each register can be reduced to 1/17. A total of 15 blocks similar to the block 46 are arranged in series, and a desired correlation output is obtained. Since the present embodiment is configured as described above, power consumption can be reduced, and for example, the battery life of the mobile device can be extended.

The arrangement of each register 52 other than the above embodiment is possible, and other timing orders are possible.

[Brief description of the drawings]

FIG. 1 is a simplified block diagram showing a spread spectrum receiving apparatus to which the present invention can be applied.

FIG. 2 is a diagram illustrating a structure of a synchronization channel used in a third generation mobile communication system.

FIG. 3 is a block diagram of a conventional digital matched filter.

FIG. 4 is a block diagram of a digital matched filter according to one embodiment of the present invention.

FIG. 5 is a block diagram showing in detail the inside of the digital matched filter of FIG. 4;

[Explanation of symbols]

 46 Digital matched filter 48 Timing controller 52 Register 58 Selector 37 Complex operation element 46 Complex delay circuit 38 Complex operation unit

Claims (4)

[Claims] 1. A digital matched filter, comprising: a timing controller (48) operating in synchronization with an external clock; a plurality of complex registers (52) whose input signal storage operation is controlled by the timing controller; A selector (58) for receiving a signal from each of the plurality of complex registers at a timing controlled by the timing controller; and a complex operation element (37) for calculating a predetermined coefficient, each of which has a predetermined delay. A digital matched filter comprising: a plurality of serially arranged delay circuits (46) for providing an output; and a complex operator (38) for operating an output signal from each of the delay circuits. 2. The digital matched filter according to claim 1, wherein the complex operation unit is a complex operation unit that selectively adds an output signal from the delay circuit according to an instruction of an external control signal. A digital matched filter, characterized in that: 3. A correlation circuit comprising the digital matched filter according to claim 1. 4. A spread spectrum signal receiving apparatus comprising the correlation circuit according to claim 3.