JP2001044890A - Synchronization establishing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device that employs a parallel matching filter for reducing a processing time required for synchronization establishment. SOLUTION: This device includes a receiver 10, that extracts I data and Q data from a spread spectrum signal, a PN buffer section 30 that serially receives a PN code sequence, stores it to a buffer bank, and outputs the stored code sequence in parallel when the buffer bank is occupied, a parallel matching filter 50 that correlates the I and Q data with PN-I and PN-Q code sequences respectively in parallel to generate correlated I and Q data, a phase component eliminating section 70 that processes the correlated I and Q data and provides an output of the result as phase elimination data, and a position detecting section 80 that compares the current phase elimination data with the frequency data and updates the preceding phase elimination data with the current phase elimination data or bypasses the preceding phase elimination data, as they are.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication system, and more particularly, to a synchronization establishing apparatus used in a wideband code division multiple access (CDMA) communication system.

[0002]

[Prior Art] Direct Sequence Spread Spectrum (DS-SS)
Communication techniques combine an information signal with a PN sequence of a random bit stream generated by a random sequence generator or pseudo-noise (PN) generator to generate and transmit a modulated signal.

[0003] At the receiver, a random sequence generator identical to that at the transmitter generates a random bit stream that reflects the original PN sequence used during modulation at the transmitter. For proper operation to take place, the random sequence generator of the receiver must be synchronized with the incoming PN sequence of the received signal after modulation of the carrier frequency. The despread signal is entered from the received signal
It is obtained by removing the sequence and integrating it for the symbol period. Ideally, this despread signal represents exactly the original information signal.

[0004] The primary function of synchronization in such a spread spectrum communication system is to despread the received PN sequence and demodulate the received signal. Such a function is performed by generating a local replica of the PN sequence at the receiver and synchronizing the local PN sequence with the PN signal superimposed on the received signal.

[0005] Normally, synchronization is an acquisition.
And tracking. For acquisition (establishment of synchronization), many techniques using various types of detectors and determination methods have been proposed. One of the common features of conventional synchronization technology is that
Correlating the received PN signal with the locally generated PN signal and calculating the similarity between these two signals. To be specific, receive
The chip data of the PN signal is sequentially correlated with the corresponding data of the locally generated PN signal. Such a sequential correlation procedure is performed when each chip of the chip clock Tc from the communication system is generated. When the correlation procedure is completed, each correlation data is integrated into one.

Thereafter, the similarity as a calculation result is compared with a predetermined threshold value to detect whether these two signals are synchronized. If so, a closed loop tracking system is activated to maintain the synchronization. However, if not synchronized, the synchronization establishment procedure changes the phase of the received PN signal and tries the correlation procedure again.

Normally, the processing time required for establishing synchronization depends on the time required for the above-described series of correlation and integration procedures, and corresponds to the number of chips of the chip clock Tc. When the search window size is N and the detection probability is 1 and the false alarm probability is 0, it takes at least N'Tc of processing time to perform the correlation and integration procedure,
The processing time is considerably longer. The detection probability indicates the detectability of the synchronization when synchronization is achieved, and the false alarm probability indicates the detectability of the synchronization when synchronization is not performed. Therefore, in order for synchronization to be established at a higher speed, it is necessary to reduce the time for the correlation and integration procedure.

[0008]

SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a synchronization establishing apparatus which can reduce the processing time required for establishing synchronization by using a parallel matching filtering technique.

[0009]

According to the present invention, there is provided, in accordance with the present invention, a broadband code division multiple access (CDMA) system.
The spread-spectrum signal transmitted through a given channel and the pseudo-noise (P
N) a synchronization establishing device for synchronizing a code sequence, a data extracting means for extracting phase (I) data and quadrature (Q) data from the spread spectrum signal, and serially receiving the PN code sequence A data output means for storing the storage data in parallel when the storage element is stored in the storage element and the storage element is clogged with the PN code sequence; and the I data and the Q data are each included in the PN code sequence. PN_I code sequence and PN_Q
Correlation means for correlating in parallel with a code sequence to generate correlation I data and correlation Q data, and processing for processing the correlation I data and the correlation Q data and outputting processing result data as current phase removal data Means for determining whether the current phase elimination data is greater than the previous phase elimination data, and selectively updating the previous phase elimination data with the current phase elimination data according to the determination result. An establishing device is provided.

[0010]

Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a novel synchronization establishing apparatus according to the present invention. According to the synchronization establishing procedure of the present invention, the spread spectrum signal transmitted through the channel is synchronized with the PN code sequence generated from the PN code generator of the receiver, so that the spread spectrum signal is despread and restored. Can be restored. The device of the present invention comprises a receiver 10, a PN code generator 20,
Buffer unit 30, parallel matched filter 50, phase component removing unit 70
And a position detection unit 80.

When the power is turned on, the receiver 10
5 to receive the spread spectrum signal transmitted through a predetermined channel. This spread spectrum signal is composed of spectrum data of a plurality of frames. Receiver 10
Converts the received spread spectrum signals (down-converting) and provides the converted I and Q data to the parallel matched filter 50 via their corresponding predetermined channels.

On the other hand, the PN code generator 20 generates a PN code sequence having the same sequence but a different phase for the spread spectrum signal. The PN code sequence has a PN_I code sequence and a PN_Q code sequence. That is, the PN code generator 20 is a CDMA system.
PN_I code and PN of the PN_I code sequence according to the chip clock Tc (not shown) generated from (not shown)
The PN_Q code of the _Q code sequence is sequentially generated to the PN buffer unit 30. PN buffer unit 30 is a PN code generator
By connecting between the parallel matching filter 50 and the
PN_I code sequence and PN_Q from code generator 20
Store the code sequences in their corresponding areas.

FIG. 2 is a detailed schematic diagram of the PN buffer unit 30. Each of the PN buffer units 30 has N (for example, 256)
And a pair of buffer rows 32 and 34 each having one buffer.
One of the buffer rows (for example, 32) has a PN_I code
Store the sequence and the other buffer column (i.e., 34)
Stores the _Q code sequence. These buffer columns 3
When 2 and 34 are clogged with the PN_I and PN_Q code sequences generated from PN code generator 20, respectively, the PN_I and PN_Q code sequences in buffer rows 32 and 34 will have a predetermined rising edge of the Tc clock. The parallel matched filter shown in FIG.
Transmitted in parallel to 50.

Referring again to FIG. 1, the parallel matched filter
50 is the I and Q data of the spread spectrum signal and the PN buffer
Perform parallel matching process with PN code sequence from 30. For this process, as shown in FIG. 3, the parallel matched filter 50 is provided with two correlators 55 and 65, a multiplexer (MUX) 58, and a recursive adder 60. These two correlators 55 and 65 are identical to each other, except that the first correlator 55 processes the I data and the second correlator 65 processes the Q data. As shown in FIG. 3, the first correlator 55 has a shift register 52, a latch circuit 54, and a multiplication circuit 56,
The second correlator 65 has a shift register 62, a latch circuit 64, and a multiplication circuit 66. With such a configuration, the processing time required for establishing synchronization between the received spread spectrum signal and the PN_I code sequence generated from the PN code generator 20 can be reduced.

More specifically, the shift register 52 is used for the receiver 1
Stores each chip data of I data supplied from 0,
This is shifted to the right according to the Tc clock. Each chip data is composed of, for example, 4 bits. This series of storage / shifting processes involves powering the shift registers.
As long as the signal is supplied to the terminal 52, for example, the operation is repeated at every rising edge of the Tc clock. In such an iterative process, when the shift register 52 is clogged with I data chip data, these chip data are sent to the corresponding multiplier in the multiplication circuit 56 at a predetermined rising edge of the Tc clock. It is taken out at the same time. After that, shift register 52
Shifts a series of chip data input for the next fetch process to the right in chip data units.

On the other hand, the latch circuit 54 temporarily stores the PN_I code sequence on the buffer sequence 32 generated from the PN buffer unit 30 in FIG. 1, and after a predetermined time interval, stores the stored PN_I code sequence. Is output to the corresponding multiplier of the multiplication circuit 56. At the predetermined rising edge of the Tc clock, each multiplier of the multiplication circuit 56
Multiply by the corresponding PN_I code of the PN_I code sequence. Subsequently, all the I data multiplied by each multiplier are output to the MUX 58 at the same time.

Similarly, the shift register 62 of the second correlator 65
Operates in the same manner as the correlator 55 described above. That is, the shift register 62 stores the chip data of the Q data output from the receiver 10 in FIG. 1 and shifts the data to the right. When the shift register 62 is filled with chip data of Q data in such a series of storing / shifting operations, these chip data are simultaneously output to the corresponding multipliers in the multiplication circuit 66. The latch circuit 64
The PN_Q code sequence on the buffer train 34 generated from the PN buffer unit 30 is temporarily stored, and is output to a corresponding multiplier of the multiplication circuit 66 after a predetermined time interval. continue,
Each multiplier of the multiplier circuit 66 multiplies the chip data of the Q data by the corresponding PN_Q code of the PN_Q code sequence at a predetermined rising edge of the Tc clock. Thus, all the Q data multiplied by each multiplier are output to the MUX 58 at the same time.

The MUX 58 alternately receives the multiplied I data from the multiplication circuit 56 and the multiplied Q data from the multiplication circuit 66 and outputs them to the recursive addition section 60. For example, the MUX 58 outputs the multiplied I data at a predetermined rising edge of the Tc clock, and outputs the multiplied Q data at a predetermined falling edge of the Tc clock. Then, the recursive addition unit
Numeral 60 recursively adds the data received from the MUX 58, that is, all multiplied I data and all multiplied Q data, in synchronization with the Tc clock. The recursive addition unit 60 can be embodied by using, for example, an addition module having 4'256 adders. Thereafter, the added I data and Q data are supplied to the phase component removing unit 70 in FIG.

Referring again to FIG. 1, the phase component removing unit 70
Is the absolute value of each of the added I data and Q data
After taking the power, the square I data and the square Q data are added. In such a series of absolute / squaring processes,
The phase component removing unit 70 can obtain correlation data by removing a phase component from the added I data and Q data.
FIG. 4 is a detailed block diagram of the phase component removing unit 70,
The phase component removing unit 70 includes an absoluteizing circuit 72, a squaring circuit 74,
It has an adder 76 and a MUX 78.

The absoluteizing circuit 72 calculates the added I data and Q
This is used to prevent the number of bits of I data and Q data from increasing when the data is squared by the squaring circuit 74. That is, the absoluteization circuit 72
Absolute for each of the data and Q data. Such a process is performed for each of the added I data and Q data if a negative sign bit is detected in each data.
This is done by taking the complement of Thereafter, the absolute I data and the absolute Q data by the absoluteizing circuit 72 are transmitted to the squaring circuit 74, respectively, and are squared.

Thereafter, the squared I data and Q data are transmitted to the adder 76, respectively. The adder 76 adds the output from the MUX 78 to the input square I data and square Q data, and outputs addition data. The output from the MUX78 adds the zero value to the squared I data at a predetermined falling edge of the Tc clock, or adds the squared Q data to the squared I data at a predetermined falling edge. Can be sought. The addition data thus obtained is supplied to the position detection unit 80 in FIG. 1 as phase removal data.

Referring back to FIG. 1, the position detecting section 80 detects the largest data among many input phase-removed data and has the largest received spread spectrum data.
It performs the function of detecting the start position of I data and Q data. The detected starting position represents the position where the received spread spectrum data is synchronized with the PN code sequence generated from PN code generator 20. As shown in FIG. 5, the position detection unit 80 includes a maximum data storage circuit 83 and a position information storage circuit 84.
, And a comparator 86.

More specifically, the phase-removed data obtained by the adder 76 in FIG. 4 is first input to the maximum data storage circuit 83 and the comparator 86. The maximum data storage circuit 83 compares the received phase elimination data (current phase elimination data) with the previously stored phase elimination data (previous phase elimination data), and displays the previous phase elimination data according to the comparison result. Either update with the phase elimination data or bypass the current phase elimination data as it is.

Initially, the maximum data storage circuit 83 includes a comparator 86
Irrespective of the update control signal from the adder 76, stores the phase-removed data from the adder 76 (i.e., the current phase-removed data), and sets the stored data as the maximum data, for the subsequent processor (not shown). ) And to the comparator 86 as pre-phase elimination data. Thereafter, the maximum data storage circuit 83 receives the next phase elimination data following the current phase elimination data (new current phase elimination data), and in response to the update control signal, stores the internally stored current phase elimination data (that is, The previous phase removal data is updated with the new current phase removal data, or the new current phase removal data is bypassed as it is. That is, when the update control signal from the comparator 86 indicates that the new current phase elimination data is larger than the previous phase elimination data stored in the maximum data storage circuit 83, the maximum data storage circuit 83 Is updated with the new current phase elimination data. Otherwise, the new current phase elimination data is bypassed. The phase elimination data updated by the maximum data storage circuit 83 is supplied to the comparator 86 as the previous phase elimination data, and is also supplied to the subsequent processor as new maximum data. Such a series of comparison / update processes is repeatedly performed until all the phase removal data is processed.

The comparator 86 outputs the phase removal data from the adder 76.
(Current phase elimination data) and the previous phase elimination data from the maximum data storage circuit 83, and determines whether the current phase elimination data is larger than the previous phase elimination data. Based on the determination result, the comparator 86 supplies an update control signal to the maximum data storage circuit 83 and the position information storage circuit 84.

On the other hand, the position information storage circuit 84 stores the position information indicating the start position of the I and Q data corresponding to the data stored in the maximum data storage circuit 83 as the spread spectrum data. Of course, the position data stored in the position information storage circuit 84 is updated with the position data corresponding to the data in the maximum data storage circuit 83 in response to the update control signal from the comparator 86. This position information can be obtained by monitoring the sequence of the spread spectrum data to be processed and counting the number of chips of the Tc clock supplied to the position information storage circuit 84.

Although the preferred embodiments of the present invention have been described above, those skilled in the art will be able to make various modifications without departing from the scope of the present invention.

[0029]

Thus, according to the present invention, the use of a novel parallel matched filter which performs correlation processing of a received PN signal and a PN signal supplied from a receiver in parallel is achieved by using a conventional correlation technique using a serial correlation technique. As compared with the synchronization establishing apparatus, the synchronization establishing algorithm can be performed at a higher speed, and the start-up of a mobile station, a channel switching process during a call, and the like in a wireless communication system can be efficiently realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronization establishing apparatus according to the present invention.

FIG. 2 is a detailed schematic diagram of a PN buffer unit in FIG.

FIG. 3 is a detailed circuit diagram of the parallel matched filter in FIG. 1;

FIG. 4 is a detailed block diagram of a phase component removing unit in FIG. 1;

FIG. 5 is a detailed block diagram of a position detection unit in FIG.

[Explanation of symbols]

 5 ... Antenna 10 ... Receiver 20 ... PN code generator 30 ... PN buffer part 32,34 ... Buffer row 50 ... Parallel matched filter 52,62 ... Shift register 52,64 ... Latch circuit 55,65 ... Correlator 56, 66 Multiplying circuit 58, 78 Multiplexer (MUX) 60 Recursive adding unit 70 Phase removing unit 72 Absolute circuit 74 Squaring circuit 76 Adder 80 Position detecting unit 82 Storage circuit 83 Maximum data storage circuit 84 ... Position information storage circuit 86 ... Comparator

Claims (9)

[Claims] An apparatus for synchronizing a spread-spectrum signal transmitted through a predetermined channel with a pseudo-noise (PN) code sequence generated at a receiver for use in a wideband code division multiple access (CDMA) system. In-phase (I) data and quadrature (Q) from the spread spectrum signal
Data fetching means for fetching data, data receiving means for serially receiving the PN code sequence and storing it in a storage element, and outputting the stored data in parallel when the storage element is clogged with the PN code sequence. Correlating means for correlating the I data and the Q data in parallel with the PN_I code sequence and the PN_Q code sequence included in the PN code sequence, respectively, to generate correlated I data and correlated Q data; Processing means for processing the I data and the correlation Q data and outputting the processing result data as the current phase elimination data; determining whether the current phase elimination data is larger than the previous phase elimination data; Determining means for selectively updating the previous phase elimination data with the current phase elimination data. 2. Correlation means: storing means for storing the I data and Q data of the spread spectrum signal, each having a series of chip data; and storing each chip data of the I data in the PN_I Multiplying means by multiplying the corresponding code of the code sequence by each chip data of the Q data by the corresponding code of the PN_Q code sequence; adding all the multiplied I chip data; Adding all the multiplied Q chip data,
2. The synchronization establishing apparatus according to claim 1, further comprising an adding unit that outputs the I chip data and the added Q chip data as correlation I data and correlation Q data, respectively. 3. An absoluteizing means for performing absolute processing on each of the correlation I data and the correlation Q data, an absolute I data and an absolute Q obtained by the absoluteizing means.
Squaring means for squaring each of the data, square I data and square Q obtained by the squaring means
Means for summing the data and outputting the sum as the phase-removed data.
Synchronization establishing device according to claim 1. 4. The synchronization establishing apparatus according to claim 2, wherein said storage means is embodied using a shift register. 5. The method according to claim 1, wherein the storing means stores the I data and the Q data.
Each of the data is stored, and each chip data is
Means for shifting to the right in chip data units each time the data is input to the register, and simultaneously outputting all chip data of the I data and the Q data stored in the shift register to the multiplication means; 5. The synchronization establishing device according to claim 1, comprising: 6. The method of claim 3, further comprising the step of selectively outputting all of the multiplied I-chip data or all of the multiplied Q-chip data. apparatus. 7. The determining means receives the current phase elimination data and determines whether the current phase elimination data is greater than the previous phase elimination data, and the current phase elimination data is the previous phase elimination data. If it is determined to be larger than the data, the previous phase elimination data is updated with the current phase elimination data, and the updated phase elimination data is used as new front phase elimination data in a subsequent determination process by the determining means. And a means for repeating the operation of the determining means and the first updating means with respect to the next phase removing data until all the phase removing data are processed. 2. The synchronization establishing device according to 1. 8. The method according to claim 8, wherein the determining means updates the position data of the previous phase removal data with the position data of the current phase removal data when the current phase removal data is determined to be larger than the previous phase removal data. The system of claim 7, further comprising two updating means, wherein the position data is obtained by monitoring a series of spread spectrum data to be processed and using a chip clock generated in the CDMA system. Synchronization establishing device as described. 9. PN_I in the PN code sequence
The code sequence and the PN_Q code sequence are
2. The synchronization establishing device according to claim 1, wherein the synchronization establishing device outputs a PN_I code sequence and a plurality of buffers corresponding to the number of code data of each of the PN_Q code sequences and is simultaneously output from a latch module.