JP3770753B2 - Received signal demodulation method and wireless communication apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a code spread (spread spectrum) communication system, and more particularly to a method for demodulating a code spread QPSK modulated received signal and a radio communication apparatus using the method.
[0002]
[Prior art]
In recent years, cellular mobile communication systems (IS-95) using a spread spectrum system have been put into practical use in the United States, Hong Kong, South Korea, and the like. In this field, for example, it is promising to apply a digital matched filter (hereinafter referred to as “matched filter: MF”) to a spread spectrum receiver because of advantages such as high speed of initial synchronization acquisition and flexibility such as RAKE reception path search. It has become. However, in order to widely spread spread spectrum receivers using matched filters, it is necessary to reduce power consumption, circuit scale, and LSI cost in the synchronization acquisition circuit unit.
[0003]
In spread spectrum communication, when a transmission signal is modulated by QPSK (Quadrature Phase Shift Keying), each receiver needs to have a despreader having a demodulation function of the QPSK signal. The I component (I: In phase) of the QPSK modulated received signal is Di, the Q component (Q: Quadrature phase) is Dq, the I component spreading code (chip sequence) used in the despreader is Ci, and the Q component is spread. When the code is Cq, in order to demodulate the original signal,
Si + jSq = (Di + jDq) (Ci−jCq)
Paying attention to the real part Si and the imaginary part Sq, the operation represented by the following equation may be performed between the despread signals.
Real part: Si = DiCi + DqCq. . . . (Equation 1)
Imaginary part: Sq = DqCi-DiCq. . . . (Equation 2)
That is, the spread spectrum QPSK signal can be demodulated by a despreader that adds and subtracts the multiplication results of the received signals Di and Dq and the spreading codes Ci and Cq to satisfy the above equations (Equation 1) and (Equation 2). .
[0004]
8 to 10 show an example of a circuit configuration of a conventional despreader that demodulates a spread spectrum QPSK signal using a matched filter.
The despreader includes a matched filter unit 61, a QPSK demodulation unit 62, and an accumulation unit 63. The matched filter unit 61 has four received signal shift types in which the received signal Di (t) or Dq (t) and the spreading code Ci (t) or Cq (t) are input in time series in different combinations. It consists of a matched filter 610 (610a to 610d). The QPSK demodulator 62 includes an adder 621 that performs the calculation of (Expression 1) and an adder 622 for subtraction that performs the calculation of (Expression 2). It consists of two accumulation registers 630a and 630b that accumulate the outputs of 621 and 622 over a predetermined symbol period.
[0005]
The correlation value DiCi output from the matched filter 610a and the correlation value DqCq output from the matched filter 610d are added by the adder 621, and the addition output is accumulated over several symbol periods by the accumulation register 630a. The I component demodulated output Si (t) (= DiCi + DqCq) shown in 1) is obtained. Further, the correlation value DiCq output from the matched filter 610c is subtracted by the adder 622 (added after sign inversion) from the correlation value DqCi output from the matched filter 610b, and is accumulated over several symbol periods by the accumulation register 630b. Thus, a Q component demodulated output Sq (t) (= DqCi−DiCq) is obtained.
[0006]
In FIG. 9, a signed 4-bit width received signal Rx (t) oversampled at a rate four times the chip rate of the spread code is supplied to one input terminal, and the reverse of the 1-bit width is supplied to the other input terminal. The structure of the received signal shift type matched filter 610 to which the spread code PN (t) is supplied at the chip rate is shown.
The matched filter 610 sequentially shifts the received signal Rx (t) and outputs the received signal in parallel from the 16 taps Tap0 to Tap15 corresponding to the chip position at the sampling rate. A coefficient register unit 613 that holds PN (t) and outputs the coefficients of each chip in parallel from 16 taps, and 16 registers for multiplying the outputs of the input register 611 and the coefficient register 613 for each tap. And a summing unit 614 that fully adds the outputs of the multipliers and outputs the result as a correlation value Corr (t).
[0007]
The coefficient register 613 includes a 16-stage shift register that sequentially shifts the spread code PN (t), and chip registers C0 to C15 that latch chip coefficients at the timing of the load signal Wc from each stage of the shift register. . The block indicated by symbol T in the coefficient register 613 means that the spread code PN (t) is shifted at the chip rate, and the block indicated by symbol 4D in the input register unit 611 is the received signal Rx (t). Is shifted at a sampling rate, that is, four times the chip rate.
The despread code PN (t) is multiplied by the received signal output at the sampling rate from each tap of the input register 611 for each chip coefficient of the spread code held in the chip registers C0 to C15 of the coefficient register unit 613. Is done. At this time, if the received signal Rx (t) is 4 bits wide, the output Corr (t) of the adder 614 that performs addition for 16 taps is 8 bits wide. When the spreading ratio Gp of the received signal Rx (t) is equal to 16 taps, the input signal of several symbol periods is repeatedly despread with the same chip sequence held in the chip registers C0 to C15. When the spreading ratio Gp exceeds the number of taps 16, the load signal Wc is generated every 16 chip periods, and the coefficient values held in the chip registers C0 to C15 are periodically updated.
[0008]
FIG. 10 shows a configuration of the accumulation unit 630a. The other accumulation register unit 630b has the same configuration.
The accumulation register unit 630a includes a 16-stage shift register 6302a and an adder 6301a for accumulating the output signal and the input signal of the shift register 6302a. Each stage of the shift register 6302a is composed of four stages of shift registers, as indicated by symbol 4D, and shifts the input signal at a speed four times the chip rate. Each stage of the shift register is reset to the initial value 0 at the start of the accumulation operation.
The accumulation register unit 630a accumulates the output signal of the QPSK demodulation unit 62 over a predetermined symbol period, and outputs the result to the output terminal OUT. That is, the output signal of the adder 6301a is sequentially accumulated by a shift register 6302a having the same number of shift stages as the number of taps of the matched filter 610 (in this example, the number of stages is four times the number of taps). By repeating the addition with the output of the last stage of the shift register, the demodulation result of the QPSK signal can be accumulated for each chip interval (in this example, for each oversample interval).
[0009]
In the above-described matched filter 610, the correlation value Corr () at the timing when the chip pattern output from the taps Tap0 to Tap15 of the input register 611 matches the chip pattern of the spread code (C0 to C15) output from the coefficient register 613. t) is the maximum, and at other timings, the correlation value Corr (t) is 0 or a small value. The change in the correlation value is repeated at the symbol period, and the output signal of the QPSK demodulator 62 repeats the same change as the correlation value. Therefore, each stage of the accumulation register 630a has a correlation value Corr for each chip section. (t) is accumulated over multiple symbol periods.
[0010]
Accordingly, the accumulation register 630a obtains an output signal OUT having a periodicity indicating a peak value in a chip section in which the phase of the received signal coincides with the chip pattern of the spread code. Therefore, at the timing when the peak value is detected. Synchronization acquisition can be achieved by initiating dephasing code phase shifting. If the input signal IN of the accumulation register 630a is 9 bits wide and the correlation value is accumulated over a period of 4 symbols, the output OUT of the accumulation register is 11 bits wide.
However, the despreader using the received signal shift type matched filter 610 described above needs to include accumulation registers 630a and 630b having the same number of shift stages as the matched filter taps (Tap0 to Tap15) outside the matched filter. is there.
[0011]
FIG. 11 shows a despreader using a cyclic accumulation type matched filter filed in Japanese Patent Application No. 9-205774 by the same applicant as the present application.
This despreader includes a matched filter unit 91 and a QPSK demodulator 92, and it is not necessary to connect an accumulator after the QPSK demodulator 92. The matched filter unit 91 includes four cyclic accumulation type matched filters 910 (910a to 910d) each having an accumulator therein, and correlation values DiCi, DqCq, DqCi output from these matched filters and DiCq is added and subtracted by the adders 921 and 922 of the QPSK demodulator 92 to obtain an I component demodulated signal Si (t) (= DiCi + DqCq) represented by (Equation 1) and a Q component represented by (Equation 2). The demodulated signal Sq (t) (= DqCi−DiCq) is obtained.
[0012]
FIG. 12 shows a basic configuration of the cyclic accumulation type matched filter 910.
The cyclic accumulation type matched filter 910 includes a multiplication unit 101, a spread code coefficient register unit 102, and a cyclic accumulation unit 103. In the following description of the operation, a despreader is applied to spread spectrum communication with a spreading ratio Gp = 64, and the multiplier 101 receives a sampling rate at which the received signal Rx (t) is k (k = 4) times the chip rate. Is input.
The reception signal Rx (t) is individually multiplied by the m-chip spreading code PN (t) held in the coefficient register unit 102 in the multiplication unit 101. These multiplication results are output in parallel from the m taps of the multiplication unit 101 and are cyclically accumulated by the cyclic accumulation unit 103. When the result of multiplication by the cyclic accumulation unit 103 is Gp / m = 4 cycles, a correlation value Corr (t) for one symbol is obtained.
[0013]
The coefficient register unit 102 includes m stages (m = 16) of coefficient registers C0 to C15 controlled by a latch signal Lcj (j = 0 to 15). In these coefficient registers, the chip signals of the spread code PN (t) are sequentially set for each chip by sequentially supplying the latch signals Lc0 to Lc15. That is, the j-th coefficient register Cj (j = 0 to 15) takes in the chip coefficient of the spread code PN (t) at the input timing of the latch signal Lcj, and keeps the value of the chip coefficient until the next latch signal Lcj is received. Hold. The coefficient register Cj receives the next latch signal Lcj every m × k = 64 operation clocks (oversampling clock).
[0014]
The multiplication unit 101 multiplies the value of the spread code PN (t) set in each coefficient register C0 to C15, that is, m (m) for multiplying the coefficient value of each chip by the received signal Rx (t). = 16) multipliers MPY0 to MPY15, and the operation results of each multiplier are supplied to the cyclic accumulation unit 103 as m (m = 16) tap outputs Tap0 (t) to Tap15 (t). .
The cyclic accumulation unit 103 includes m (m = 16) sub accumulation registers 1300 to 1315 and adders ADD0 to ADD15 corresponding to the tap outputs Tap0 (t) to Tap15 (t). The accumulator registers and adders are connected in a ring to cyclically accumulate the tap output. In addition, a switch circuit 133 is connected to the sub-accumulation register 1315 at the final stage in order to output the correlation value Corr (t) indicating the despread demodulation result to the outside at a predetermined timing.
[0015]
In the cyclic accumulation unit 103, each adder ADDj (j = 0 to 15) is supplied with a tap output Tapj (j = 0 to 15) supplied from the multiplication unit 101 at a frequency four times the chip rate. The accumulation result Accj ′ (t) output from the sub accumulation register 13j-1 (j = 00 to 15) located in the preceding stage is added, and the addition result Accj (t) is added to the sub accumulation register 10j associated therewith. Is entered. Therefore, Acc0 (t) = Tap0 (t) + Acc15 ′ (t) is output from the first-stage adder ADD0, and Acc1 (t) = Tap1 (t) + Acc0 ′ (t) from the second adder ADD1. ) Is output. Similarly, the adders ADD2 to ADD15 output the addition results Acc2 (t) to Acc15 (t) and input them to the sub accumulation registers associated therewith.
[0016]
Each sub-accumulation register 13j (j = 00 to 15) includes a cascade connection shift register 132 having a number of stages equal to the sampling coefficient k. In this example, since the received signal is oversampled at a rate four times the chip rate, the accumulation result Accj (t) is delayed by 4 operation clock times in each sub accumulation register 13j, and Accj ′ (t ) (J = 0-15). Therefore, a signal which has a relationship of Accj ′ (t) = Accj (t−4) and has started despread demodulation processing with PN (0) with respect to the signal Rx (0) received at t = 0 is m The sub-accumulation registers 1300 to 1315 (m = 16) are cyclically passed through Gp / m = 4 times, and the accumulation process is repeated during this period. In this case, if the received signal Rx (t) is 4 bits wide, the correlation value Corr (t) becomes 10 bits wide by adding 16 taps and repeating 4 times.
[0017]
[Problems to be solved by the invention]
According to the above conventional example, in the case of the despreader using the received signal shift type matched filter shown in FIG. 8, the accumulation is performed after the complete sum of the tap outputs is output from each matched filter 610. Therefore, the necessary number of accumulators 630 can be reduced to two by performing QPSK synthesis before the accumulating unit 63. However, each matched filter 610 requires a shift register 611 for shifting the received signal Rx (t), and there is a problem that the circuit scale of the matched filter unit increases.
On the other hand, in the case of the despreader using the cyclic accumulation type matched filter 910 shown in FIG. 11, since the accumulation unit is formed inside each cyclic accumulation type matched filter, a despreader for QPSK modulation is provided. As a result, four accumulators are required for the configuration, and there is a problem that the circuit scale increases as a whole.
[0018]
An object of the present invention is to provide a method for demodulating a code spread QPSK modulation signal that can reduce the circuit scale of a despreader.
Another object of the present invention is to provide a code spread QPSK modulation type wireless communication apparatus capable of reducing the circuit scale and reducing the power consumption.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, QPSK demodulation (combination) operation is performed for each chip of the spread code, and the QPSK demodulation results generated in parallel by a plurality of chips are cyclically performed along the chip sequence. A correlation signal between the received signal and the spread code is obtained by accumulating.
[0020]
That is, in the method for demodulating a QPSK modulated signal and the wireless communication apparatus of the present invention, the I component received signal Di (t) and the Q component received signal Dq (t) of the code spread QPSK modulated signal input in time series are converted into I components. By despreading for each chip with the spreading code Ci and the Q component spreading code Cq, a plurality of sequences of despreading results corresponding to different combinations of received signals and spreading codes are generated for each chip, and the plurality of sequences By calculating the despreading result of the above in a predetermined combination, the I component and Q component demodulated values of the QPSK modulation signal are generated for each chip, and the I component and Q component demodulated values for each chip are generated. It is characterized by cyclically accumulating according to the chip sequence of the spreading code.
[0021]
More specifically, the demodulation method of the QPSK modulation signal of the present invention is as follows.
(A) holding at least part of the chip sequence of the I component spreading code Ci of the QPSK modulation signal and at least part of the chip sequence of the Q component spreading code Cq, The I component received signal Di (t) and the Q component received signal Dq (t) of the code spread QPSK modulation signal input in time series are calculated, and the multiplication result DqCi (t), DiCi is calculated for each chip of the spread code. (t), generating DqCq (t), DiCq (t);
(B) For each chip of the spreading code, by adding the DiCi (t) and DqCq (t), a partial value of the I component of the QPSK modulation signal is generated, and the DiCq (t) is generated from the DqCi (t). Generating a partial value of the Q component of the QPSK modulated signal by subtracting
(C) The method includes a step of cyclically accumulating the partial value of the I component and the partial value of the Q component in the sequence order of each spreading code chip sequence.
[0022]
Further, the wireless communication apparatus of the present invention includes a spreading code generator, a receiving circuit for demodulating a transmission signal by despreading a received signal of code spreading QPSK modulation with a spreading code generated from the spreading code generator, A synchronization acquisition circuit for synchronizing the generation of the spread code from the spread code generator with the received signal, and the synchronization acquisition circuit is connected in a cascade manner so as to return the output of the final stage to the first stage. It consists of multiple stages of matched filters.
A spread code Ci at a specific chip position in the I component and Q component spread codes is added to the I component received signal Di (t) and the Q component received signal Dq (t) of the code spread QPSK modulated signal input in time series. Means for multiplying Cq and generating operation results DqCi (t), DiCi (t), DqCq (t) and DiCq (t) in parallel;
A partial demodulated value corresponding to the I component of the QPSK modulated signal is generated from the calculation results DiCi (t) and DqCq (t), and the Q component of the QPSK modulated signal is calculated from the DqCi (t) and DiCq (t). Means for generating a partial demodulated value,
The partial demodulated values of the I component and the Q component are respectively added to the accumulated demodulated values of the I component and the Q component supplied from the preceding stage or the final stage matched filter, and the addition result is supplied to the next stage or the first stage matched filter. And means for supplying the accumulated demodulated value of the Q component.
[0023]
Another feature of the wireless communication apparatus according to the present invention is that the synchronization acquisition circuit includes a first register circuit that holds at least a part of a chip sequence of a spreading code Ci supplied from the spreading code generator, and the spreading code. The second register circuit that holds at least a part of the chip sequence of the spread code Cq supplied from the generator, and the chip sequences of the held spread codes Ci and Cq are respectively input in time series. The I component received signal Di (t) and the Q component received signal Dq (t) of the code spread QPSK modulated signal are multiplied, and the multiplication results DqCi (t), DiCi (t), DqCq ( t) and DiCq (t), a plurality of multiplier groups, and partial demodulation of the I component of the QPSK modulated signal by adding DiCi (t) and DqCq (t) for each chip of the spreading code Generate a value for each QPSK by subtracting DiCq (t) from DqCi (t) for each chip of the spreading code, and a first cyclic accumulation circuit that cyclically accumulates partial demodulated values in the sequence of the spreading code chip sequence. A partial demodulated value of the Q component of the modulated signal is generated, and a second cyclic accumulating circuit that cyclically accumulates each partial demodulated value in the sequence of the spreading code chip sequence is provided.
[0024]
More specifically, the first and second register circuits include a plurality of register areas arranged in the order of chip sequence and the spread codes Ci or Cq supplied from the spread code generator in the register areas. Each of the multiplier groups is composed of a plurality of multipliers corresponding to the number of register areas of the first and second register circuits, respectively. A time-series output of a multiplication result of the spread code held in the register area and the I component received signal Di (t) or the Q component received signal Dq (t).
The first and second cyclic accumulation circuits temporarily store a plurality of adders or subtracters corresponding to the plurality of multipliers in each multiplier group and the operation results of the adders or subtractors. Is stored in the register and then supplied to the next stage adder or subtracter. The final stage register selectively transfers the output of the register to an external circuit or first stage adder or subtracter. A change-over switch is provided.
[0025]
According to a preferred embodiment of the present invention, each register constituting the first and second cyclic accumulation circuits cyclically selects a plurality of storage areas and a storage area to which data is written and read. The operation result of the adder or subtracter written in each storage area is read out after a predetermined time and output to the adder or subtracter in the next stage.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a despreader according to the present invention having a QPSK demodulation function.
The despreader according to the present embodiment includes a plurality of cascaded matched filters MF0 to MF15, and performs despreading of a received signal and partial addition and accumulation for QPSK demodulation for each matched filter. The result is circulated to the next-stage matched filter.
[0027]
The matched filters MF0 to MF15 correspond to chips at specific positions in each chip row of the I-phase spreading code Ci (t) and the Q-phase spreading code Cq (t), respectively, and the first-stage matched filter MF0 is a spreading code. Ci0 and Cq0, the next-stage matched filter MF1 uses spreading codes Ci1 and Cq1, and so on. Similarly, the final-stage matched filter MF15 uses spreading codes Ci15 and Cq15, respectively, to receive signals Di (t) and Dq (t ) And despread. Since each matched filter MFj (j = 0 to 15) has the same configuration and repeats the same operation, the configuration and operation of the first-stage matched filter MF0 will be described.
[0028]
The matched filter MF0 includes a multiplier composed of four multipliers MII, MQI, MIQ, MQQ, a QPSK demodulator composed of adders 12a and 12b, an accumulator composed of adders 13a and 13b and accumulation registers 14a and 14b. It consists of an arithmetic part.
Multipliers MII, MQI, MIQ, MQQ respectively multiply the received signal Di and the spreading code Ci0, Dq and Ci0, Di and Cq0, Dq and Cq0, and multiply the results DiCi0 (t), DqCi0 (t), DiCq0 (t ), DqCq0 (t) is sent to the QPSK demodulator.
[0029]
The output DiCi0 (t) of the multiplier MII and the output DqCq0 (t) of the multiplier MQQ are added to each other by the adder 12a, and then the previous matched filter (in this case, the final stage) is added by the adder 13a of the accumulation unit. And the output of the matched filter MF15). As a result, as a partial demodulation output of the I component,
Si0 (t) = (DiCi0 (t) + DqCq0 (t)) + Si15 (t)
Is obtained and input to the accumulation register 14a.
[0030]
The output DqCi0 (t) of the multiplier MQI and the output DiCq0 (t) of the multiplier MIQ are added to each other by the adder 12b, and then the previous matched filter (in this case, the final stage) is added by the adder 13b of the accumulation unit. Of the matched filter MF15) is subtracted (added after sign inversion). Thus, as a partial demodulated output of the Q component,
Sq0 (t) = (DqCi0 (t) −DiCq0 (t)) + Sq15 (t)
Is obtained and input to the accumulation register 14b.
[0031]
The subsequent matched filters MF1 to MF15 also operate in the same manner as the above MF0, and as a partial demodulation output of the I component,
Si1 (t) = (DiCi1 (t) + DqCq1 (t)) + Si0 (t)
Si2 (t) = (DiCi2 (t) + DqCq2 (t)) + Si1 (t)
......
Si15 (t) = (DiCi15 (t) + DqCq15 (t)) + Si14 (t)
As a partial demodulated output of the Q component,
Sq1 (t) = (DqCi1 (t) −DiCq1 (t)) + Sq0 (t)
Sq2 (t) = (DqCi2 (t) −DiCq2 (t)) + Sq1 (t)
......
Sq15 (t) = (DqCi15 (t) −DiCq15 (t)) + Sq14 (t)
Is generated.
[0032]
As is apparent from the above description of the operation, the despreader of this embodiment performs partial addition and accumulation for QPSK demodulation for each tap in the conventional m-tap matched filter, and the result is used as the next tap. It is patrol. For example, when the cyclic accumulation over one symbol (or several symbols) period is completed, the correlation value Si (t) indicating the demodulation result is switched by switching the switches 15a and 15b connected to the output circuit of the final-stage matched filter MF15. ) S and q (t) are taken out.
[0033]
According to the above configuration, since the cyclic accumulation registers need only be two series 14a and 14b, the circuit scale can be reduced as compared with the conventional despreader shown in FIGS. Further, since it is only necessary to supply the matched signals MF0 to MF15 with the received signals Di (t) and Dq (t) in parallel, the circuit scale is larger than that of the conventional received signal shift type matched filter. Can be downsized. In the above embodiment, the 16-tap despreading circuit is shown. However, the despreading circuit of the present invention has a configuration in which matched filters having the same configuration are connected cyclically, so that it corresponds to the required number of taps. By connecting a number of matched filters, a despreader with an arbitrary number of taps can be easily formed.
[0034]
FIG. 2 shows another embodiment of a despreader according to the present invention.
In order to facilitate comparison with the conventional cyclic matched filter described with reference to FIG. 12, the despreader is again applied to a spread spectrum communication system having a spreading ratio Gp = 64, and the received signals Dq (t), Di It is assumed that (t) is over-sampled at 4 times the chip rate (k = 4) and supplied to the despreader.
The despreader of this embodiment forms a matched filter with m (m = 16) taps, and is connected to two spread code coefficient registers 102a and 102b for I phase and Q phase, and a coefficient register 102a. First and second multipliers 101a and 101b, third and fourth multipliers 101c and 101d connected to the coefficient register 102b, and two cyclic accumulation units for I-phase and Q-phase 103a and 103b.
[0035]
Similar to the embodiment shown in FIG. 1, the despreader of this embodiment also uses the coefficient register in common for the two multipliers by performing QPSK demodulation in the cyclic accumulator, and is necessary for despreading the QPSK signal. The number of simple cyclic coefficient registers is reduced to two.
[0036]
The coefficient register units 102a and 102b are each composed of m (m = 16) coefficient registers C0 to C15 that are latch-controlled by a latch signal Lcj (j = 0 to 15). Each coefficient register Cj (j = 0 to 15) of the coefficient register unit 102a latches the spread code coefficient Ci (t) for I phase at the generation timing of each latch signal Lcj until the next latch signal is given. Hold this. Similarly, each of the registers Cj (j = 0 to 15) of the coefficient register unit 102b also obtains the spreading code coefficient Cq (t) for the Q phase at the generation timing of the respective latch signal Lcj (j = 0 to 15). Latch. Each register Cj is supplied with a latch signal Lci every m × k (= 64) operation clocks. Therefore, a new spreading code coefficient is set in the register Cj when the received signals Dq (t) and Di (t) in the m-chip period are despread with one spreading code coefficient latched in the register Cj. .
[0037]
The first multiplication unit 101a includes m (m = 16) multipliers MQI0 to MQI15 corresponding to the coefficient registers C0 to C15 of the coefficient register unit 102a, and each multiplier MQIj (j = 0 to 15) The Q-phase received signal Dq (t) is multiplied by the spread signal Cij (j = 0-15) held in each coefficient register Cj (j = 0-15), and the multiplication result DqCij (t) is each tap. Output from.
The second multiplication unit 101b includes m (m = 16) multipliers MII0 to MII15 corresponding to the coefficient registers C0 to C15 of the coefficient register unit 102a, and each multiplier MIIj (j = 0 to 15) The I-phase received signal Di (t) is multiplied by the spread signal Cij (j = 0-15) held in each coefficient register Cj (j = 0-15), and DiCij (t) is output from each tap. To do.
[0038]
The third multiplication unit 101c includes m (m = 16) multipliers MQQ0 to MQQ15 corresponding to the coefficient registers C0 to C15 of the coefficient register unit 102b, and each multiplier MQQj (j = 0 to 15) The Q-phase received signal Dq (t) is multiplied by the spread signal Cqj (j = 0-15) held in each coefficient register Cj (j = 0-15), and DqCqj (t) is output from each tap. To do.
The fourth multiplication unit 101d includes m (m = 16) multipliers MIQ0 to MQ15 corresponding to the coefficient registers C0 to C15 of the coefficient register unit 102b, and each multiplier MQj (j = 0 to 15) The I-phase received signal Di (t) is multiplied by the spread signal Cqj (j = 0-15) held in each coefficient register Cj (j = 0-15), and DiCqj (t) is output from each tap. To do.
[0039]
The I-phase cyclic accumulation unit 103a performs QPSK demodulation for each tap based on the tap outputs DiCij (t) and DqCqj (t) supplied from the second and third multiplication units 101b and 101c. Then, the demodulation result is accumulated cyclically Gp / m = 4 times, and an I-phase correlation value Si (t) is output. Similarly, the Q-phase cyclic accumulating unit 103b is provided for each tap based on the tap outputs DqCij (t) and DiCqj (t) supplied from the first and fourth multipliers 101a and 101d. QPSK is demodulated, and the demodulation result is accumulated cyclically Gp / m = 4 times to output a Q-phase correlation value Sq (t).
[0040]
As shown in FIG. 3, the I-phase cyclic accumulation unit 103a includes an adder ADDj (j = 0 to 15) and a sub accumulation register 14j (j = 00 to 15) corresponding to each tap. Each adder ADDj outputs the multiplication results DiCij (t) and DqCqj (t) supplied from the second and third multipliers 101b and 101c and the output of the sub-accumulation register 14 (j-1) in the previous stage. Acc (j−1) a ′ (t) is added, and the addition result Accja (t) is input to the sub-accumulation register 14j. That is, the j-th tap adder output Accja (t) in the cyclic accumulation unit 102a is expressed by the following equation.
Accja (t) = DiCij (t) + DqCqj (t) + Acc (j−1) a ′ (t) In the cyclic accumulation unit 103a, the output of the final stage sub-accumulation register 1415 is supplied to the first stage adder ADD0. Acc15a ′ (t) is input. Accordingly, the result of QPSK demodulation performed for each tap is cyclically accumulated by passing through the adder and sub-accumulation register for each tap connected in a circular manner. In FIG. 3, the adder ADDj (j = 0 to 15) is represented as a three-input adder. However, a two-input adder for adding DiCij (t) and DqCqj (t) May be divided into a two-input adder for adding the output of the previous sub-accumulation register.
[0041]
The sub-accumulation register 1415 in the final stage is provided with a switch 15a for stopping the circulation of the demodulation result to the first-stage adder ADD0 at a predetermined timing and outputting the result as a correlation value of the despread demodulation result to the outside. Each sub-accumulation register 14j is composed of four-stage registers operating at an oversampling rate as shown in the final stage 1415, and the demodulation result Accja (t) of each tap is four operation clock periods. (= 1 chip period) Delayed to reach the adder ADD (j + 1) of the next tap.
[0042]
As shown in FIG. 4, the Q-phase cyclic accumulation unit 103b also includes an adder ADDj (J = 0 to 15) and a sub accumulation register 14j (j = 00 to 15) corresponding to each tap. . Each adder ADDj subtracts the multiplication result DiCqj (t) supplied from the fourth multiplication unit 101d from the multiplication result DqCij (t) supplied from the first multiplication unit 101a, and subtracts this from the previous sub-accumulation. The output Acc (j−1) b ′ (t) of the arithmetic register 14 (j−1) is added, and the addition result Accjb (t) is input to the sub-accumulation register 14j. That is, the Q-phase cyclic accumulation unit 102b obtains an output of the following expression by the j-th tap adder Accj.
Accjb (t) = DqCij (t) −DiCqj (t) + Acc (j−1) b ′ (t) The Q-phase cyclic accumulation unit 103b subtracts the other from one of the multiplication results by the adders Acc0 to Acc10. Except for this point, it is structurally identical to the I-phase cyclic accumulation unit 103a.
[0043]
With the above configuration, when cyclic accumulation sections 103a and 103b start despreading demodulation processing starting from input signals Di (t) and Dq (t) at t = 0, the demodulation result for each tap is one symbol period. The cyclic accumulation circuit composed of m (m = 16) sub accumulation registers is cyclically repeated Gp / m = 4 times while accumulating the demodulation results of subsequent taps. When the demodulation result makes at least one cycle of the cyclic accumulation circuit, the outputs of the cyclic accumulation units 103a and 103b satisfy the equations 1 and 2, respectively. Therefore, by switching the switches 15a and 15b at an appropriate timing, for example, when one symbol period has elapsed, the cyclic accumulation unit 103a receives the I-phase demodulated correlation value Si (t), and the cyclic accumulation unit 103b Each Q-phase demodulated correlation value Sq (t) can be extracted to the outside.
[0044]
When the number of taps of the despreader (m = 16) is smaller than the spreading ratio (Gp = 64) as in the present embodiment, matching (multiplication) is performed with each coefficient of the spreading code set in the coefficient register units 102a and 102b. ) The possible range is only a part of the chip sequence for one symbol of the received signals Di and Dq. Therefore, at the start of despreading, the phase shift between the heads of the spreading codes Ci (t) and Cq (t) and the head positions of the symbols of the received signals Di and Dq has exceeded the collation range (16 chips). In this case, no peaks exceeding the predetermined threshold appear in the demodulation correlation values Si (t) and Sq (t). In this case, spreading codes Ci (t) and Cq (t) are generated in a state where the phase shift with respect to the received signal is shifted by the above collation range from the previous time, and the above demodulation operation is repeated, so that Gp / m at the maximum. Synchronization can be captured with 1 retry.
[0045]
FIG. 5 shows an example of a register structure applied as the sub-accumulation register 14j of the cyclic accumulation unit 103 (103a, 103b).
The accumulation register block 14 includes four registers 141 (r0 to r3) as many as the oversampling number k (k = 4), and a selector 142 for selecting outputs of these selectors. Of the registers 141, the register to which data is written / read is sequentially switched by the latch timings Lr0 to Lr3 generated by the quaternary counter 143, and the output of the register specified at the latch timing is selected by the selector 142. Then, the next tap is output. The quaternary counter 143 is shared by a plurality of accumulation registers 1400 to 1415 in each cyclic accumulation unit 103.
[0046]
When the above accumulation register block 14 is applied to the first accumulation register 1400 of the cyclic accumulation unit 103b, the accumulation result ACC0b (t) of the adder Acc0 is one of the registers specified by the latch timings Lr0 to Lr3. It is written in r0 to r3. At this time, the accumulated result of the previous four clocks held so far is output from the specific register, and is output to the next tap as output ACC0b ′ (t) via the selector.
By sequentially switching the registers r0 to r3 at the latch timings Lr0 to Lr3 and reading the previous data in synchronization with the writing of new data in each register, the input data is output from the accumulation register block 14 after 4 timings. Can function as a four-stage shift register. According to the above configuration, each register 142 (r0 to r3) has only to perform a write / read operation at a rate of once every four timings. Therefore, a general shift register in which the cascade-connected registers are always operated. Compared to the configuration, power consumption can be greatly reduced.
[0047]
FIG. 6 shows an example of a wireless terminal device (mobile terminal) to which the despreader of the present invention is applied.
The mobile terminal includes a processing device 21 connected to the internal bus 30, a memory 22 for storing various programs and data executed by the processing device 21, and a display device for displaying character information as a user interface. 23, an input device 24 including a numeric keypad and other function keys, a microphone 26 and a speaker 27 connected to the speech encoding / decoding circuit 25, and an interface circuit 28 for connecting to an external storage device or computer device. Prepare. In addition, the transmission circuit 31, the reception circuits 32 A and 32 B, and the power supply control circuit 33 are connected to the internal bus 30, and the transmission circuit 31 and the reception circuits 32 A and 32 B are connected to the antenna via the radio unit 33. 34.
[0048]
In a code division multiple access (CDMA) wireless communication system, a unique spreading code is assigned to each of a downlink radio section from a radio base station to each mobile terminal and an uplink radio section from each mobile terminal to each radio terminal. Are assigned to a plurality of channels. The transmission circuit 31 transmits an uplink common control channel for notifying the base station of the transmission from each mobile terminal, an individual control channel used for transmission / reception of connection control information after the incoming call notification, and user information Therefore, switching of these channels is performed in accordance with a channel (spreading code) designation signal given from the processing device 21 to the signal line 41. It is done by switching. When the transmission circuit 31 is used as a common or individual control channel, a control signal output from the processing device 21 is supplied to the transmission circuit via the bus 30 and the selector 35, and these control signals are supplied to each control circuit. Code spreading is performed with a specific spreading code assigned to the channel. On the other hand, when the transmission circuit 31 is used for a traffic channel, the audio signal from the microphone 26 encoded by the audio encoding / decoding circuit 25 is supplied to the transmission circuit 31 via the selector 35, and A PQSK modulated signal code-spread with a specific spreading code of the traffic channel is transmitted from the antenna 34 via the radio unit 33.
[0049]
The reception circuit 32A is used to transmit system information essential for control of the wireless communication system, such as cell information, synchronization information, or spreading codes to be used in other control channels, to all mobile terminals in common. This circuit is dedicated to the first common control channel in the downstream direction. Also, the receiving circuit 32B includes a second common control channel in the downlink direction used for incoming notification to each terminal and allocation control of the individual control channel, and an individual control channel used for connection control between the base stations. And a traffic channel used for transmitting user information from the base station to the terminal. As with the transmission circuit 31, the channel specification in the reception circuit 32A and the channel switching in the reception circuit 32B are performed in accordance with the channel (spreading code) designation signal given from the processing device 21 to the signal line 43. This is done by switching the sign.
[0050]
FIG. 7 shows a basic configuration of the receiving circuit 32B. The receiving circuit 32A has the same configuration.
The receiving circuit 32B includes spreading code generators 50i and 50q for generating spreading codes for I-phase and Q-phase used for despreading, and a synchronization acquisition circuit 51 comprising the above-described despreader of the present invention, A despreading circuit 53 for despreading the received signals Di (t) and Dq (t) input from the signal radio unit 33 using the spreading codes Ci and Cq output from the spreading code generator. .
[0051]
The spread code generators 50 i and 50 q generate spread codes in accordance with the control signal 43 a supplied from the processing device 21. The synchronization acquisition circuit 51 despreads the received signals Di (t) and Dq (t) input from the signal radio unit 33 using the spreading codes Ci and Cq output from the spreading code generator, and QPSK. Demodulation correlation values Si (t) and Sq (t) are output. The start of the synchronization acquisition (despreading) operation and the sending of correlation values Si (t) and Sq (t) by switching the switch 15 are controlled by a control signal 43c supplied from the processing device 21. The output of the synchronization acquisition circuit 51 is input to the peak detection circuit 52, and when a peak exceeding a predetermined threshold is detected, the synchronization acquisition signal 43b output from the peak detection circuit 52 generates a spread code generator 50i, 50q starts the phase shift operation of the spread code.
[0052]
When synchronization is acquired, the mode shifts to the synchronization tracking mode, and the despreading circuit 53 uses the spread codes Ci and Cq output from the spread code generators 50i and 50q to receive signals Di (t) and Dq (t). Is despread and a QPSK demodulated signal is output. The QPSK demodulated signal is subjected to predetermined demodulation processing by the detection circuit 54 and then error-corrected by the error correction decoder 55. The output of the error correction decoder 55 is supplied to the interface circuit 57 via the reception buffer 56. Is done. When the transmission circuit 32B is operating for the control channel, the received signal is output to the internal bus 30, and when it is operating for the traffic channel, it is output to the speech code decoding circuit 25.
[0053]
【The invention's effect】
As is apparent from the above description, according to the present invention, the code spread QPSK signal can be demodulated with a small number of accumulators and a simple matched filter, so that the circuit scale of the despreader can be reduced and the power consumption can be reduced. This is possible and particularly effective in battery-powered portable wireless terminals.
[Brief description of the drawings]
FIG. 1 shows a first embodiment of a despreader and a synchronization acquisition circuit according to the present invention.
FIG. 2 is a diagram showing a second embodiment of the despreader and the synchronization acquisition circuit according to the present invention.
FIG. 3 is a diagram showing an example of a specific circuit configuration of a cyclic accumulation unit 103a shown in FIG.
4 is a diagram illustrating an example of a specific circuit configuration of a cyclic accumulation unit 103b illustrated in FIG. 2;
FIG. 5 is a diagram illustrating an embodiment of an accumulation register applied to the cyclic accumulation unit illustrated in FIGS. 3 and 4;
FIG. 6 is a diagram showing an embodiment of a wireless communication apparatus showing an application example of a despreader and a synchronization acquisition circuit according to the present invention.
7 is a diagram showing a detailed configuration of a receiving circuit 32B shown in FIG. 6. FIG.
FIG. 8 is a diagram showing a configuration of a conventional despreader using a received signal shift type matched filter.
9 is a diagram showing a configuration of a received signal shift type matched filter 810 applied to the despreader of FIG. 8. FIG.
10 is a diagram showing a configuration of an accumulation register 630a applied to the despreader of FIG.
FIG. 11 is a diagram illustrating an example of a configuration of a conventional despreader using a cyclic accumulation type matched filter.
12 is a diagram showing a configuration of a cyclic accumulation type matched filter 910 applied to the despreader of FIG. 11. FIG.
[Explanation of symbols]
MF0 to MF15: matched filter,
101: Multiplier, MQI, MII, MQQ, MQ: Multiplier,
102: coefficient register unit, C0 to C15: coefficient register, 103: cyclic accumulation unit,
12, 13, ADD0 to ADD15: adder,
14, 1400 to 1415: Accumulation register, 15a, 15b: Output changeover switch, 50: Spreading code generator, 51: Synchronization acquisition circuit, 52: Peak detection circuit,
53: Despreading circuit.

Claims (13)

Despreading for each chip in a time-series manner of the reception signal input I Ingredient D i (t) and Q Ingredient D q (t) of the spreading code I Ingredient C i and Q Ingredient C q by despreading results of a plurality of streams corresponding to different combinations of the respective received signal and the spreading code generated at the each chip, by calculating the despreading result of the plurality of series in a predetermined combination of the received signal A code characterized in that demodulated values of the I component and Q component are generated for each chip, and the demodulated values of the I component and Q component for each chip are cyclically accumulated according to the chip sequence of each spreading code. A method for demodulating the spread received signal. The coefficient values of each chip of the spread code I component Ci and Q component Cq applied to the despreading of the I component Di (t) and Q component Dq (t) of the received signal are sequentially updated in a predetermined cycle, 2. The received signal demodulation method according to claim 1, wherein the demodulated values of the I component and the Q component for each chip are cyclically accumulated over at least one symbol period. The I component Di (t) and the Q component Dq (t) of the received signal are oversampled and supplied, and the demodulated values of the I component and the Q component are generated a plurality of times in each chip period. Item 4. A received signal demodulation method according to Item 1. The received signal modulation method, wherein the received signal is a signal modulated and transmitted by a QPSK modulation method. And at least a portion of the chip sequence I Ingredient C i of the spread code, may be held and at least a portion of the chip sequence Q Ingredient C q, and the chip sequence is the holding, in each time series It calculates the I Ingredient D i of the received signal input (t) and Q Ingredient D q (t), for each chip of the spreading code multiplication result DqCi (t), DiCi (t ), DqCq (t ), Generating DiCq (t);
For each chip of the spreading code, by adding the DiCi (t) and DqCq (t), a partial value of the I component of the received signal is generated, and the DiCq (t) is subtracted from the DqCi (t). To generate a partial value of the Q component of the received signal,
A method of demodulating a code-spread received signal, comprising the step of cyclically accumulating the partial value of the I component and the partial value of the Q component in the sequence order of each spreading code chip sequence. Despreading for each chip in a time-series manner of the reception signal input I Ingredient D i (t) and Q Ingredient D q (t) of the spreading code I Ingredient C i and Q Ingredient C q Means for generating a despreading result of a plurality of sequences corresponding to different combinations of received signals and spreading codes for each chip,
Means for generating an I component demodulated value and a Q component demodulated value of the received signal for each chip by calculating the despread results of the plurality of sequences in a predetermined combination;
Further comprising a despreader for code spreading modulation comprising a means for accumulating cyclically in accordance with the respective spreading code chip sequence generated above I component demodulated value and Q component demodulated value for each chip A wireless communication device. 7. The wireless communication apparatus according to claim 6, wherein the received signal is a signal that is modulated and transmitted by a QPSK modulation method. A spreading code generator, a receiving circuit for demodulating the transmission signal received signals modulated by despreading with a spreading code generated from the spreading code generator, the generation of the spread code from the spread code generator In a wireless communication apparatus having a synchronization acquisition circuit for synchronizing the received signal with the received signal,
The synchronization acquisition circuit is composed of a plurality of stages of matched filters that are connected in a cascade manner so as to return the output of the last stage to the first stage.
When the series received signals input I Ingredient D i (t) and Q Ingredient D q (t), the spreading code Ci of the particular chip position in the spreading code for an I component and Q component, the Cq Means for multiplying and generating operation results DqCi (t), DiCi (t), DqCq (t) and DiCq (t) in parallel;
A partial demodulated value corresponding to the I component of the received signal is generated from the calculation results DiCi (t) and DqCq (t), and a portion corresponding to the Q component of the received signal from the DqCi (t) and DiCq (t) Means for generating a demodulated value;
The partial demodulated values of the I component and the Q component are respectively added to the accumulated demodulated values of the I component and the Q component supplied from the preceding stage or the final stage matched filter, and the addition result is supplied to the next stage or the first stage matched filter. And a means for supplying an accumulated demodulated value of the Q component. 9. The wireless communication apparatus according to claim 8, wherein the received signal is a signal transmitted after being modulated by a QPSK modulation method. A spread code generator for generating an I Ingredient C i and Q Ingredient C q of the spreading code of the transmission signal, the spreading code of the received signal generated from the spread code generator I component Ci, Q component Cq A radio circuit having a receiver circuit that despreads the signal and demodulates the transmission signal and a synchronization acquisition circuit for synchronizing the generation of the Q component Cq of the I component Ci and Q of the spread code from the spread code generator with the received signal In the communication device, the synchronization acquisition circuit includes:
A first register circuit for holding at least a part of a chip sequence of the I component Ci of the spread code supplied from the spread code generator; and at least one of the Q component Cq of the spread code supplied from the spread code generator. A second register circuit that holds a chip row of a portion;
I component Ci of the retained spreading codes, each chip sequence Q component Cq of reception signals respectively time-series manner input I Ingredient D i (t) and Q Ingredient D q (t) and A plurality of multiplier groups that generate multiplication results DqCi (t), DiCi (t), DqCq (t), and DiCq (t) for each chip of the spreading code,
For each chip of the spread code, by adding the DiCi (t) and DqCq (t), a partial demodulated value of the I component of the received signal is generated, and each partial demodulated value is cycled in the sequence of the spread code chip sequence. A first cyclic accumulation circuit that accumulates automatically,
For each chip of the spread code, a partial demodulated value of the Q component of the received signal is generated by subtracting DiCq (t) from the DqCi (t), and each partial demodulated value is cyclically arranged in the sequence of the spread code chip sequence. radio communications device characterized by comprising a second cyclic accumulation circuit for accumulating the. Each of the first and second register circuits sequentially stores a plurality of register areas arranged in the order of a chip sequence and a spreading code Ci or Cq supplied from the spreading code generator in each register area in units of chips. And a latch signal supply circuit that
Each of the multiplier groups is composed of a plurality of multipliers corresponding to the number of register areas of the first and second register circuits, respectively, and each of the multipliers includes a spread code held in the register area and the I The radio communication apparatus according to claim 10 , wherein a multiplication result of the component reception signal Di (t) or the Q component reception signal Dq (t) is output in time series. The first and second cyclic accumulation circuits temporarily hold a plurality of adders or subtracters corresponding to a plurality of multipliers of each multiplier group, and operation results of the adders or subtractors. After that, it consists of a plurality of registers to be supplied to the adder or subtracter of the next stage, and the register at the final stage selectively transfers the output of the register to an external circuit, or to the adder or subtracter of the first stage. The wireless communication device according to claim 11 , further comprising a changeover switch. Each of the registers constituting the first and second cyclic accumulation circuits comprises a plurality of storage areas and means for cyclically selecting a storage area to which data is to be written and read. 13. The wireless communication apparatus according to claim 12 , wherein the operation result of the adder or subtracter written in is read out after a predetermined time and output to the adder or subtracter in the next stage.

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