JP2000307472A - Method for demodulating code spread qpsk modulated signal and radio communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulating method for spread spectrum QPSK (quadrature phase shift keying) modulated signal and a radio communication device which can make a circuit smaller in scale and lower in power consumption. SOLUTION: The I component Di(t) and Q component Dq(t) of a code spread QPSK modulated signal are inversely spread by chips with an I component spread code Ci and a Q component spread code Cq to generate a plurality of series of inverse spread results by the chips, the series of inverse spread results are processed in specific combinations to generate demodulated values of the I component and Q component of the QPSK modulated signal by the chips, and the demodulated values of the I component and Q component by the chips are cyclically accumulated according to respective chip sequences of the spread code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code spread (spread spectrum) communication system,
The present invention relates to a method of demodulating a code-spread QPSK-modulated received signal and a wireless communication device using the same.

[0002]

2. Description of the Related Art In recent years, in the United States, Hong Kong, Korea, etc., cellular mobile communication systems (I
S-95) has been put to practical use. In this field, it is promising to apply a digital matched filter (hereinafter referred to as a matched filter: MF) to a spread spectrum receiver because of advantages such as high speed of initial synchronization acquisition and flexibility such as a path search for RAKE reception. It has become. However, in order to spread a spread spectrum receiver using a matched filter, it is necessary to reduce the power consumption, the circuit size, and the LSI price in the synchronization acquisition circuit.

In the spread spectrum communication, when a transmission signal is QPSK (Quadrature Phase Shift Keying) modulated, each receiver needs to be provided with a despreader having a function of demodulating the QPSK signal. The I component (I: In phase) of the QPSK modulated received signal is Di, and the Q component (Q: Quadrature p)
hase) is Dq, the spreading code (chip sequence) of the I component used in the despreader is Ci, and the spreading code of the Q component is Cq, in order to demodulate the original signal, the operation formula Si + jSq = ( Focusing on the real part Si and the imaginary part Sq in (Di + jDq) (Ci-jCq), an operation represented by the following equation may be performed between the despread signals. Real part: Si = DiCi + DqCq. . . . (Equation 1) Imaginary part: Sq = DqCi-DiCq. . . . (Equation 2) That is, the spread spectrum QPSK signal is the received signal D
Demodulation can be performed by a despreader that performs addition and subtraction that satisfies the above equations (Equation 1) and (Equation 2) on the multiplication result of i, Dq and the spreading codes Ci, Cq.

FIGS. 8 to 10 show an example of a circuit configuration of a conventional despreader for demodulating a spread spectrum QPSK signal using a matched filter. The despreader includes a matched filter unit 61, a QPSK demodulation unit 62, and an accumulation unit 63. The matched filter unit 61 includes four reception signal shift type receiving units in which the reception signal Di (t) or Dq (t) and the spreading code Ci (t) or Cq (t) are input in different combinations in time series. Matched filter 61
0 (610a to 610d). Further, the QPSK demodulation unit 62 includes an adder 621 that performs the operation of the above (Equation 1),
And an adder 622 for subtraction for performing the operation of (Equation 2).
The accumulator 63 includes two accumulation registers 630a and 630b for accumulating the outputs of the adders 621 and 622 over a predetermined symbol period.

The correlation value DiCi output from the matched filter 610a and the correlation value DqCq output from the matched filter 610d are added by an adder 621, and the added output is accumulated by an accumulation register 630a over several symbol periods. , (Equation 1), the demodulated output Si (t) (= DiCi + DqCq) of the I component is obtained. Further, the correlation value D output from the matched filter 610b
By subtracting (adding after sign inversion) the correlation value DiCq output from the matched filter 610c from qCi by the adder 622 and accumulating it over several symbol periods by the accumulation register 630b, the demodulation output Sq (t )
(= DqCi-DiCq) is obtained.

FIG. 9 shows that a received signal Rx (t) having a signed 4-bit width oversampled at a rate four times the chip rate of a spread code is supplied to one input terminal, and one bit is supplied to the other input terminal. The configuration of a received signal shift type matched filter 610 to which a despread code PN (t) having a width is supplied at a chip rate is shown. The matched filter 610
Is an input register section 611 that sequentially shifts the received signal Rx (t) and outputs the received signal from the 16 taps Tap0 to Tap15 corresponding to the chip position at a sampling rate in parallel, and a spreading code PN (t). And a coefficient register unit 613 that outputs the coefficient of each chip from the 16 taps in parallel, and 16 multipliers for multiplying the output of the input register 611 and the coefficient register 613 for each tap. Multiplication unit 612, and an addition unit 6 that adds all outputs of the multipliers and outputs the result as a correlation value Corr (t).
14.

The coefficient register 613 stores the spreading code PN
(t) is sequentially shifted, and 16 stages of shift registers, and chip registers C0 to C15 which latch chip coefficients from each stage of the shift register at the timing of the load signal Wc.
Consists of The block indicated by the symbol T in the coefficient register 613 means that the spreading code PN (t) is shifted at the chip rate, and the symbol 4 in the input register unit 611.
The block indicated by D means that the received signal Rx (t) is shifted at a sampling rate, that is, four times the chip rate. The despreading code PN (t) is stored in the chip registers C0 to C15 of the coefficient register unit 613.
Is multiplied by the received signal output from each tap of the input register 611 at the sampling rate for each chip coefficient of the spread code held in the. At this time, if the received signal Rx (t) has a 4-bit width, the output Corr (t) of the adder 614 that performs addition for 16 taps has an 8-bit width. If the spreading ratio Gp of the received signal Rx (t) is equal to 16 taps, the same chip row held in the chip registers C0 to C15 repeatedly despreads the input signal for several symbol periods. When the diffusion ratio Gp exceeds 16 taps, a load signal Wc is generated every 16 chip periods, and the coefficient values held in the chip registers C0 to C15 are periodically updated.

FIG. 10 shows the configuration of the accumulator 630a.
The other accumulation register section 630b has the same configuration. The accumulation register section 630a includes a 16-stage shift register 6302a and an adder 6301a for accumulating the output signal and the input signal of the shift register 6302a.
It is composed of Each stage of the shift register 6302a includes four stages of shift registers, as indicated by a symbol 4D, and shifts an input signal at a speed four times the chip rate. Each stage of the shift register is reset to an initial value 0 at the start of the accumulation operation. The accumulation register section 630a accumulates the output signal of the QPSK demodulation section 62 over a predetermined symbol period and outputs the result to an output terminal OUT. That is, the output signal of the adder 6301a is sequentially accumulated by the shift register 6302a having the same number of shift stages as the number of taps of the matched filter 610 (in this example, four times the number of taps), and the input signal IN and the above By repeating the addition with the output of the last stage of the shift register, the demodulation result of the QPSK signal can be accumulated for each chip section (in this example, for each oversampling section).

In the above-described matched filter 610, the correlation between the chip pattern output from the taps Tap 0 to Tap 15 of the input register 611 and the chip pattern of the spread code (C 0 to C 15) output from the coefficient register 613 coincides with each other. The value Corr (t) becomes maximum, and at other times, the correlation value Corr (t) becomes 0.
Or a small value. This change in the correlation value is repeated in the symbol cycle, and the output signal of the QPSK demodulation unit 62 also changes in the same manner as the above-described correlation value. Therefore, each stage of the accumulation register 630a stores the correlation value Corr for each chip section.
(t) is accumulated over multiple symbol periods.

Therefore, the output signal OUT having a periodic value showing a peak value in a chip section where the phase of the received signal matches the chip pattern of the spread code is obtained from the accumulation register 630a. Synchronization acquisition can be achieved by starting the phase shift of the despreading code at the specified timing. Assuming that the input signal IN of the accumulation register 630a has a 9-bit width and the correlation value is accumulated over four symbol periods, the output OUT of the accumulation register has an 11-bit width. However, the despreader using the received signal shift type matched filter 610 described above needs to include accumulation registers 630a and 630b having the same number of shift stages as the number of taps (Tap0 to Tap15) of the matched filter outside the matched filter. is there.

FIG. 11 shows that the same applicant as the present application is disclosed in Japanese Patent Application No.
1 shows a despreader using a cyclic accumulation type matched filter filed in US Pat. This despreader comprises a matched filter section 91 and a QPSK demodulation section 92,
There is no need to connect an accumulation unit after the SK demodulation unit 92. The matched filter unit 91 includes four cyclic accumulation type matched filters 910 (910a
910d), and the correlation values DiCi, DqCq, DqCi output from these matched filters.
And DiCq are subjected to addition and subtraction processing by adders 921 and 922 of the QPSK demodulation unit 92 to obtain an I-component demodulated signal Si (t) (= DiCi + DqCq) represented by (Expression 1).
And a Q component demodulated signal Sq (t) (= D
qCi-DiCq).

FIG. 12 shows a basic configuration of the above cyclic accumulation type matched filter 910. The cyclic accumulation type matched filter 910 includes a multiplication unit 101, a spreading code coefficient register unit 102, and a cyclic accumulation unit 103.
In the following description of the operation, the despreader is applied to spread spectrum communication with a spreading ratio of Gp = 64.
It is assumed that the received signal Rx (t) is input at a sampling rate k (k = 4) times the chip rate. The received signal Rx (t) is individually multiplied by the m-chip spreading code PN (t) held by the coefficient register unit 102 in the multiplication unit 101. These multiplication results are output in parallel from the m taps of the multiplication unit 101 and the cyclic accumulation unit 103
Is accumulated cyclically. At the time when the multiplication result is Gp / m = 4 in the cyclic accumulation unit 103, the correlation value Corr (t) for one symbol is obtained.

The coefficient register section 102 has m (m = m) stages controlled by a latch signal Lcj (j = 0 to 15).
16) Coefficient registers C0 to C15. By sequentially applying latch signals Lc0 to Lc15 to these coefficient registers, the chip coefficients of the spreading code PN (t) are sequentially set one chip at a time. That is, the j-th coefficient register Cj (j = 0 to 15) stores the latch signal Lcj
, The chip coefficient of the spreading code PN (t) is fetched at the input timing, and the value of the chip coefficient is held until the next latch signal Lcj is received. The coefficient register Cj has m × k =
64 operation clocks (oversampling clock)
Each time, it receives the next latch signal Lcj.

The multiplication unit 101 multiplies the value of the spreading code PN (t) set in each of the coefficient registers C0 to C15, that is, m, for multiplying the coefficient value of each chip by the received signal Rx (t). (M = 16) multipliers MPY0 to MPY1
5, and the operation result of each multiplier is supplied to the cyclic accumulation unit 103 as m (m = 16) tap outputs Tap0 (t) to Tap15 (t). The cyclic accumulation unit 103 includes m (m = 16) sub accumulation registers 1300 to 13 corresponding to the tap outputs Tap0 (t) to Tap15 (t).
15 and adders ADD0 to ADD15, and these accumulation registers and adders are connected in a ring shape to cyclically accumulate the tap output. Further, in order to output the correlation value Corr (t) indicating the result of the despread demodulation to the outside at a predetermined timing, the sub-accumulation register 131 at the final stage is used.
5 is connected to a switch circuit 133.

In the cyclic accumulator 103, each adder ADDj (j = 0 to 15) outputs a tap output Tapj supplied from the multiplier 101 at a frequency four times the chip rate.
(J = 0 to 15) and the accumulation result Accj '(t) output from the sub accumulation register 13j-1 (j = 0 to 15) located at the preceding stage, and the addition result Acc
j (t) is input to the sub-accumulation register 10j associated therewith. Therefore, the first-stage adder ADD0 outputs Ac
c0 (t) = Tap0 (t) + Acc15 '(t) is output, and from the second adder ADD1, Acc1 (t) = T
ap1 (t) + Acc0 '(t) is output. Hereinafter, similarly, the adders ADD2 to ADD15 output the addition result Ac.
c2 (t) to Acc15 (t) are output and input to the associated sub accumulation registers.

Each sub accumulation register 13j (j = 00 to 1)
5) is composed of the cascade connection shift registers 132 of the number of stages equal to the sampling coefficient k. In this example, since the received signal is oversampled at a rate four times the chip rate, the accumulation result Accj (t) is delayed by four operation clock times in each sub accumulation register 13j, and Ac
It is output as cj '(t) (j = 0 to 15). Therefore, there is a relationship of Accj '(t) = Accj (t-4),
The signal obtained by starting the despreading demodulation process at PN (0) with respect to the signal Rx (0) received at t = 0 is expressed by G (m = 16) sub-accumulation registers 1300 to 1315 at Gp / m = Four times,
It passes cyclically, during which the accumulation process is repeated. In this case, if the received signal Rx (t) is 4 bits wide, 1
The correlation value Corr (t) has a 10-bit width due to the addition of 6 taps and the four repetitive accumulations.

[0017]

According to the above prior art,
In the case of the despreader using the received signal shift type matched filter shown in FIG. 8, the accumulation is performed after the complete sum of the tap outputs is output from each matched filter 610. By performing the QPSK synthesis in the foreground, the required number of accumulators 630 can be reduced to two. However, each matched filter 610
Requires a shift register 611 for shifting the reception signal Rx (t), and there is a problem that the circuit size of the matched filter unit becomes large. On the other hand, in the case of a despreader using the cyclic accumulation type matched filter 910 shown in FIG. 11, since an accumulation unit is formed inside each cyclic accumulation type matched filter, a despreader for QPSK modulation is used. In order to configure, as a result, four accumulators are required, and there is a problem that the circuit scale increases as a whole.

An object of the present invention is to provide a method of demodulating a code-spread QPSK modulated signal that can reduce the circuit size of a despreader. Another object of the present invention is to provide a wireless communication apparatus of a code spreading QPSK modulation system capable of reducing the circuit size and reducing power consumption.

[0019]

In order to achieve the above object, according to the present invention, a QPSK demodulation (synthesis) operation is performed for each chip of a spread code, and a QPSK demodulation result generated in parallel by a plurality of chips is provided. Are accumulated cyclically along the chip sequence to obtain a correlation signal between the received signal and the spread code.

That is, in the method for demodulating a QPSK modulated signal and the radio communication apparatus according to the present invention, the I-component received signal Di (t) and the Q-component received signal Dq (t) of the code spread QPSK modulated signal input in time series. Is despread for each chip with an I component spreading code Ci and a Q component spreading code Cq, thereby generating a plurality of sequences of despread results corresponding to different combinations of the received signal and the spreading code for each of the chips,
By calculating the despread results of the plurality of sequences in a predetermined combination, demodulated values of the I and Q components of the QPSK modulated signal are generated for each of the chips, and the I component and Q
It is characterized in that the demodulated value of each component chip is cyclically accumulated according to the chip sequence of each spreading code.

More specifically, the method of demodulating a QPSK modulated signal according to the present invention comprises the steps of: (a) at least a part of a chip sequence of an I component spread code Ci of a QPSK modulated signal and at least a part of a Q component spread code Cq; Keep the tip row and
Each of the held chip columns and the I-component reception signal Di of the code spread QPSK modulation signal input in time series.
(t) and the Q component received signal Dq (t) are calculated, and a multiplication result DqCi (t), DiCi
(t), generating DqCq (t), DiCq (t); and (b) for each chip of the spreading code, the DiCi
By adding (t) and DqCq (t), QPSK
A partial value of the I component of the modulated signal is generated, and the DqCi (t)
Generating a partial value of the Q component of the QPSK modulated signal by subtracting DiCq (t) from
And a step of cyclically accumulating the partial value of the I component and the partial value of the Q component in the sequence of the respective spreading code chip sequences.

Further, the radio communication apparatus of the present invention comprises: a spread code generator; and a reception code for demodulating a transmission signal by despreading a reception signal of code spread QPSK modulation with a spread code generated from the spread code generator. And a synchronization acquisition circuit for synchronizing the generation of the spreading code from the spreading code generator with the received signal, wherein the synchronization acquisition circuit is cascaded cyclically so as to return the output of the final stage to the initial stage. It is composed of a plurality of connected matched filters, and each of the matched filters described above is used for the I-component reception signal Di (t) and the Q-component reception signal Dq (t) of the code-spread QPSK modulation signal input in time series.
Multiplying the spreading codes Ci and Cq at specific chip positions in the spreading codes for the I component and the Q component,
means for generating (t), DiCi (t), DqCq (t) and DiCq (t) in parallel, and the operation result DiCi
(t) and DqCq (t), a partial demodulated value corresponding to the I component of the QPSK modulated signal is generated, and DqCi (t) and Di
Means for generating a partial demodulated value corresponding to the Q component of the QPSK modulated signal from Cq (t);
The partial demodulated value of the component is added to the accumulated demodulated value of the I component and the Q component supplied from the matched filter of the previous stage or the last stage, respectively, and the addition result is accumulated in the matched filter of the next stage or the first stage. Means for supplying as an arithmetic and demodulation value.

Another feature of the wireless communication apparatus according to the present invention is that the synchronization acquisition circuit holds at least a part of a chip string of the spread code Ci supplied from the spread code generator.
And a second register circuit for holding at least a part of the chip sequence of the spreading code Cq supplied from the spreading code generator, and the held spreading code Ci,
Each chip sequence of Cq is multiplied by the I-component reception signal Di (t) and the Q-component reception signal Dq (t) of the code spread QPSK modulation signal input in time series, and , Multiplication result DqCi (t), DiCi (t), D
By adding the plurality of multiplier groups for generating qCq (t) and DiCq (t) and the above-mentioned DiCi (t) and DqCq (t) for each chip of the spreading code, the I component of the QPSK modulated signal is obtained. A first cyclic accumulation circuit for generating a partial demodulation value and cyclically accumulating each partial demodulation value in the sequence of the spreading code chip sequence;
QP by subtracting DiCq (t) from Ci (t)
A second cyclic accumulation circuit generates a partial demodulated value of the Q component of the SK modulation signal and cyclically accumulates each partial demodulated value in the sequence of the spreading code chip sequence.

More specifically, the first and second register circuits store a plurality of register areas arranged in a chip sequence order and a spreading code Ci or Cq supplied from the spreading code generator. A latch signal supply circuit for sequentially storing data in a register area on a chip-by-chip basis. Each of the multiplier groups includes a plurality of multipliers corresponding to the number of register areas of the first and second register circuits, respectively. Each of the multipliers outputs a result of multiplication of the spread code held in the register area and the I-component received signal Di (t) or the Q-component received signal Dq (t) in a time-series manner. Further, the first and second cyclic accumulation circuits temporarily store a plurality of adders or subtractors corresponding to the plurality of multipliers of each of the multiplier groups and the operation results of the respective adders or subtractors. , And a plurality of registers to be supplied to the next-stage adder or subtractor. The final-stage register selectively transfers the output of the register to an external circuit or the first-stage adder or subtractor. And a changeover switch for performing the operation.

According to a preferred embodiment of the present invention, each of the registers constituting the first and second cyclic accumulation circuits cyclically stores a plurality of storage areas and storage areas where data is to be written and read. The operation result of the adder or subtractor written in each of the storage areas is read out after a predetermined time and output to the next-stage adder or subtractor. I do.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a despreader according to the present invention having a QPSK demodulation function. The despreader of this embodiment is composed of a plurality of cascaded matched filters MF0 to MF15, and performs despreading of a received signal and partial addition and accumulation for QPSK demodulation for each matched filter. The result is circulated to the next-stage matched filter.

The matched filters MF0 to MF15 respectively include an I-phase spreading code Ci (t) and a Q-phase spreading code Cq.
(t) corresponds to a chip at a specific position in each chip row, and the first-stage matched filter MF0 is a spread code Ci0
And Cq0, and the next-stage matched filter MF1 has a spreading code C
i1 and Cq1, and thereafter, similarly, the matched filter MF15 at the last stage despreads the received signals Di (t) and Dq (t) using the spreading codes Ci15 and Cq15, respectively. Since each matched filter MFj (j = 0 to 15) has the same configuration and repeats the same operation, the configuration and operation of the first-stage matched filter MF0 will be described.

The matched filter MF0 includes a multiplier composed of four multipliers MII, MQI, MIQ and MQQ, a QPSK demodulator composed of adders 12a and 12b, adders 13a and 13b and accumulation registers 14a and 14b. And an accumulation unit consisting of Multipliers MII, MQI, MI
Q and MQQ are the received signal Di and the spreading code Ci, respectively.
0, Dq and Ci0, Di and Cq0, Dq and Cq0, and multiplication results DiCi0 (t), DqCi0 (t), DiC
q0 (t) and DqCq0 (t) are sent to the QPSK demodulation unit.

The output DiCi0 (t) of the multiplier MII and the output DqCq0 (t) of the multiplier MQQ are added to each other by the adder 12a, and then the matched filter of the preceding stage (in this case, , Final stage matched filter M
F15). As a result, as a partial demodulated output of the I component, Si0 (t) = (DiCi0 (t) + DqCq0 (t)) + S
i15 (t) is obtained and input to the accumulation register 14a.

The output DqCi0 (t) of the multiplier MQI and the output DiCq0 (t) of the multiplier MIQ are added to each other by the adder 12b, and then the matched filter of the preceding stage (in this case, , Final stage matched filter M
F15) is subtracted from the output (added after sign inversion). As a result, as a partial demodulation output of the Q component, Sq0 (t) = (DqCi0 (t) -DiCq0 (t)) + S
q15 (t) is obtained and input to the accumulation register 14b.

Each of the matched filters MF1 to MF at the next and subsequent stages
F15 operates in the same manner as the above MF0, and as partial demodulated output of the I component, Si1 (t) = (DiCi1 (t) + DqCq1 (t)) + Si0 (t) Si2 (t) = (DiCi2 (t) + DqCq2 (t)) + Si1 (t)... Si15 (t) = (DiCi15 (t) + DqCq15 (t)) + Si14 (t), and Sq1 (t) = (DqCi1) as a partial demodulated output of the Q component (t) -DiCq1 (t)) + Sq0 (t) Sq2 (t) = (DqCi2 (t) -DiCq2 (t)) + Sq1 (t) Sq15 (t) = (DqCi15 (t) -DiCq15 (t) ) + Sq14 (t).

As is apparent from the above description of operation, the despreader of this embodiment performs partial addition and accumulation for QPSK demodulation for each tap in a conventional m-tap matched filter, and calculates the result. It is traveling to the next tap. For example, when the cyclic accumulation over one symbol (or several symbols) period is completed, the last-stage matched filter M
Switches 15a and 15b connected to the output circuit of F15
Is switched, the correlation value Si indicating the demodulation result is obtained.
(t) S and q (t) are taken out.

According to the above configuration, since the cyclic accumulation registers need only have two systems of 14a and 14b, the circuit scale can be reduced as compared with the conventional despreader shown in FIGS. Each of the matched filters MF0 to MF15 has
Since the reception signals Di (t) and Dq (t) need only be supplied in parallel, the circuit scale can be reduced as compared with a conventional reception signal shift type matched filter. In the above embodiment, the 16-tap despreading circuit is shown. However, since the despreading circuit of the present invention has a configuration in which matched filters having the same configuration are connected cyclically, the despreading circuit according to the required number of taps is provided. By connecting the number of matched filters, a despreader having an arbitrary number of taps can be easily formed.

FIG. 2 shows another embodiment of the despreader according to the present invention. To facilitate comparison with the conventional recursive matched filter described in FIG. 12, a despreader is applied to a spread spectrum communication system with a spreading ratio Gp = 64, and the received signals Dq (t) and Di are also used here. (t) is assumed to be over-sampled at four times the chip rate (k = 4) and supplied to the despreader. The despreader of the present embodiment has m
A (m = 16) tap matched filter is formed, and two spreading code coefficient registers 10 for I-phase and Q-phase are used.
2a and 102b, first and second multipliers 101a and 101b connected to the coefficient register 102a, and third and fourth multipliers 101c connected to the coefficient register 102b.
101d and two cyclic accumulators 103 for I-phase and Q-phase
a and 103b.

As in the embodiment shown in FIG. 1, the despreader of this embodiment also performs QPSK demodulation in the cyclic accumulator, so that the coefficient register is commonly used in the two multipliers and the QPSK demodulator is used.
The number of cyclic coefficient registers required for despreading of the K signal is 2
We have reduced to pieces.

Each of the coefficient register sections 102a and 102b is composed of m (m = 16) coefficient registers C0 to C15 latched by a latch signal Lcj (j = 0 to 15). Each coefficient register Cj of the coefficient register section 102a
(J = 0 to 15) latches the I-phase spreading code coefficient Ci (t) at the generation timing of each latch signal Lcj and holds it until the next latch signal is given. Similarly, each of the registers Cj (j = 0 to 15) of the coefficient register unit 102b also has its own latch signal Lc
At the occurrence timing of j (j = 0 to 15), the spreading code coefficient Cq (t) for the Q phase is latched. Each of the registers Cj has a latch signal Lc every m × k (= 64) operation clocks.
i is given. Therefore, with one spreading code coefficient latched in the register Cj, the reception signal Dq for m chip periods
(t) and Di (t) are despread, and the register Cj
Is set with a new spreading code coefficient.

The first multiplier 101a includes m (m = 16) multipliers MQI0 to MQI15 corresponding to the coefficient registers C0 to C15 of the coefficient register 102a.
Each of the multipliers MQIj (j = 0 to 15) includes a Q-phase received signal Dq (t) and a spread signal Cij (j = 0 to 15) held in each of the coefficient registers Cj (j = 0 to 15). And outputs a multiplication result DqCij (t) from each tap.
The second multiplication unit 101b includes m (m = 16) multipliers MII0 to MII15 corresponding to the coefficient registers C0 to C15 of the coefficient register unit 102a.
j (j = 0 to 15) is obtained by multiplying the I-phase received signal Di (t) by the spread signal Cij (j = 0 to 15) held in each of the coefficient registers Cj (j = 0 to 15). , DiCij
(t) is output from each tap.

The third multiplier 101c comprises m (m = 16) multipliers MQQ0 to MQQ15 corresponding to the coefficient registers C0 to C15 of the coefficient register 102b.
Each of the multipliers MQQj (j = 0 to 15) includes a Q-phase received signal Dq (t) and a spread signal Cqj (j = 0 to 15) held in each of the coefficient registers Cj (j = 0 to 15). , And outputs DqCqj (t) from each tap. The fourth multiplier 101d includes m (m = 16) multipliers M corresponding to the coefficient registers C0 to C15 of the coefficient register 102b.
Each of the multipliers MIQj (j =
0 to 15) are the I-phase received signal Di (t) and the spread signal Cq held in each of the coefficient registers Cj (j = 0 to 15).
j (j = 0 to 15) and output DiCqj (t) from each tap.

The I-phase cyclic accumulator 103a performs QPSK for each tap based on the tap outputs DiCij (t) and DqCqj (t) supplied from the second and third multipliers 101b and 101c. And demodulate the result to Gp / m
== 4 times cyclically accumulated to output the I-phase correlation value Si (t). Similarly, the cyclic accumulator 103b for the Q phase outputs a tap for each tap based on the tap outputs DqCij (t) and DiCqj (t) supplied from the first and fourth multipliers 101a and 101d. And demodulate the QPSK, and
p / m = 4 times cyclically accumulate and output Q phase correlation value Sq (t).

As shown in FIG. 3, the cyclic accumulator 103a for the I-phase includes an adder ADDj (j = j) corresponding to each tap.
0 to 15) and the sub-accumulation register 14j (j = 0 to 1)
5), and each adder ADDj outputs the multiplication result DiCij supplied from the second and third multiplication units 101b and 101c.
(t), DqCqj (t) and the sub-accumulation register 14
(J-1) output Acc (j-1) a '(t), and
The addition result Accja (t) is input to the sub accumulation register 14j. That is, the adder output Accja (t) of the j-th tap in the cyclic accumulation unit 102a is represented by the following equation. Accja (t) = DiCij (t) + DqCqj (t) + A
cc (j-1) a '(t) In the cyclic accumulation unit 103a, the first-stage adder ADD
0 is the output Ac of the sub-accumulation register 1415 at the last stage.
c15a '(t) has been input. Accordingly, the result of QPSK demodulation performed for each tap is cyclically accumulated by passing through the adder and sub-accumulation register for each tap connected in a ring. In FIG. 3, the adder AD
Although Dj (j = 0 to 15) is described as a three-input adder, a two-input adder for adding DiCij (t) and DqCqj (t), and an output of the preceding sub-accumulation register May be divided into a two-input adder for adding.

In the sub-accumulation register 1415 at the last stage,
At a predetermined timing, there is provided a switch 15a for stopping the circulation of the demodulation result to the first-stage adder ADD0 and outputting the correlation value to the outside as a correlation value of the despread demodulation result. Each of the sub-accumulation registers 14j is a four-stage register operating at an oversampling rate as shown in the final stage 1415, and the demodulation result Accj of each tap is obtained.
a (t) is delayed by four operation clock periods (= 1 chip period) and reaches the adder ADD (j + 1) of the next tap.

As shown in FIG. 4, the cyclic accumulator 103b for the Q phase also has an adder ADDj (J = J) corresponding to each tap.
0 to 15) and the sub-accumulation register 14j (j = 0 to 1)
5). Each adder ADDj includes a first multiplication unit 10
From the multiplication result DqCij (t) supplied from 1a, the fourth
Multiplication result DiCqj supplied from the multiplication unit 101d of
(t) is subtracted, and this is added to the sub-accumulation register 14 (j
-1) is added to the output Acc (j-1) b '(t), and the addition result Accjb (t) is input to the sub-accumulation register 14j. That is, the cyclic accumulation unit 102b for the Q-phase
The output of the following equation is obtained by the tap adder Accj. Ac
cjb (t) = DqCij (t) -DiCqj (t) + Acc
(j-1) b '(t) The cyclic accumulator 103b for the Q phase is structurally a cyclic accumulator for the I phase except that the adders Acc0 to Acc10 subtract one of the multiplication results from the other. Accumulator 10
Same as 3a.

With the above configuration, the cyclic accumulator 103a,
103b, the input signals Di (t) and Dq at t = 0
When the despreading demodulation process is started with (t) as a starting point, demodulation results for each tap are m (m = 1) within one symbol period.
The cyclic accumulation circuit composed of the sub accumulation registers in 6) is provided by Gp /
The circuit circulates while repeating accumulation with the demodulation result of the subsequent tap m = 4 times. When the demodulation result has made at least one round of the cyclic accumulation circuit, the outputs of the cyclic accumulation units 103a and 103b satisfy the arithmetic expressions of Equations 1 and 2, respectively. Therefore, by switching the switches 15a and 15b at appropriate timing, for example, at the timing when one symbol period has elapsed, the cyclic accumulation unit 103a outputs the I-phase demodulation correlation value Si (t) and the cyclic accumulation unit 103b outputs The Q-phase demodulation correlation value Sq (t) can be extracted to the outside.

When the number of taps (m = 16) of the despreader is smaller than the spreading ratio (Gp = 64) as in this embodiment, each coefficient of the spreading code set in the coefficient register units 102a and 102b is used. The range that can be checked (multiplied) is only a part of the chip sequence for one symbol of the received signals Di and Dq. Therefore, at the start of despreading, the spreading code C
The phase shift between the top of i (t) and Cq (t) and the top of the symbol of received signal Di and Dq is the above-mentioned collation range (for 16 chips).
, The demodulated correlation values Si (t), Sq
No peak at or above the predetermined threshold appears at (t). in this case,
Spreading codes Ci (t) and Cq (t) are generated with the phase shift with respect to the received signal shifted by the matching range from the previous time,
By repeating the demodulation operation described above, Gp /
Synchronization can be captured with m retries.

FIG. 5 shows the cyclic accumulator 103 (103a, 1a).
03b) shows an example of a register structure applied as the sub-accumulation register 14j of FIG. Accumulation register block 14
Consists of four registers 141 (r0 to r3) of the same number as the oversampling number k (k = 4), and a selector 142 for selecting an output of these selectors. Of the registers 141, registers to which data is written / read are sequentially switched by latch timings Lr0 to Lr3 generated by the quaternary counter 143, and the output of the register specified by the latch timing is selected by the selector 142. Then, the next tap is output. The quaternary counter 143 is provided for each cyclic accumulator 1.
03 are shared by a plurality of accumulation registers 1400 to 1415.

When the accumulation register block 14 is applied to the first accumulation register 1400 of the cyclic accumulator 103b, the accumulation result ACC0b (t) of the adder Acc0 is determined by the latch timing Lr0 to Lr3. The data is written to the registers r0 to r3. At this time, the accumulated result of four clocks previously held is output from the specific register, and the output ACC0 is output via the selector.
Output to the next tap as b '(t). The registers r0 to r3 are sequentially switched at the latch timings Lr0 to Lr3, and the previous data is read out in each register in synchronization with the writing of new data, so that the input data is output from the accumulation register block 14 after four timings. Can function as a four-stage shift register. According to the above configuration, each of the registers 142 (r0 to r
In the case of 3), the write / read operation only needs to be performed once every four timings. Therefore, compared to a general shift register configuration in which the registers of the cascade-connected stages always operate.
Power consumption can be greatly reduced.

FIG. 6 shows an example of a radio terminal (mobile terminal) to which the above-described despreader of the present invention is applied. The mobile terminal
A processing device 21 connected to the internal bus 30; a memory 22 for storing various programs and data executed by the processing device 21; a display device 23 for displaying character information as a user interface; An input device 24 including other function keys;
The microphone includes a microphone 26 and a speaker 27 connected to the audio encoding / decoding circuit 25, and an interface circuit 28 for connecting to an external storage device or computer device. Also connected to the internal bus 30 are a transmitting circuit 31, receiving circuits 32A and 32B, and a power control circuit 33.
And the transmission circuit 31 and the reception circuits 32A and 32B
Are connected to an antenna 34 via a radio unit 33.

CDMA (Code Division Multiple Acces)
s) In the wireless communication system, a plurality of unique spreading codes are assigned to a downlink wireless section from the wireless base station to each mobile terminal and an uplink wireless section from each mobile terminal to the wireless base station. Channels are formed. The transmission circuit 31 transmits an uplink common control channel for notifying the base station of a transmission from each mobile terminal, an individual control channel used for transmitting and receiving connection control information after the reception notification, and user information. Therefore, these channels are shared with the uplink traffic channels allocated to each mobile terminal, and switching of these channels is performed according to a channel (spreading code) designation signal given from the processing device 21 to the signal line 41.
This is performed by switching spread codes used for spread spectrum. When the transmission circuit 31 is used as a common or individual control channel, a control signal output from the processing device 21 is supplied to the transmission circuit via the bus 30 and the selector 35, and these control signals are transmitted to each control circuit. Code spreading is performed with a specific spreading code assigned to the channel. On the other hand, when the transmission circuit 31 is used for a traffic channel, the audio signal from the microphone 26 encoded by the audio encoding / decoding circuit 25 is supplied to the transmission circuit 31 via the selector 35, and P code-spread with a specific spreading code of the traffic channel
The QSK modulated signal is transmitted from antenna 34 via radio section 33.

The receiving circuit 32A is used to transmit system information essential to control of the radio communication system, such as cell information, synchronization information, or a spreading code to be used in another control channel, to all mobile terminals in common. Is a circuit dedicated to the first common control channel in the downlink direction used in the first embodiment. Further, the reception circuit 32B includes a downlink second common control channel used for notification of incoming call to each terminal and allocation control of an individual control channel, and an individual control channel used for connection control with a base station. And a traffic channel used for transmitting user information from the base station to the terminal. The channel specification in the reception circuit 32A and the switching of the channel in the reception circuit 32B are performed in the same manner as the transmission circuit 31 in accordance with the channel (spreading code) designation signal given from the processing device 21 to the signal line 43 by the spread spectrum used for spectrum spreading. This is done by switching the sign.

FIG. 7 shows a basic configuration of the receiving circuit 32B. The receiving circuit 32A has a similar configuration. The receiving circuit 32B is used for the I phase and Q
Spreading code generator 50i for generating a spreading code for a phase
And 50q, the synchronization acquisition circuit 51 including the above-described despreader of the present invention, and the received signals Di (t) and Dq (t) input from the signal radio section 33, and the spread signals output from the spread code generator. And a despreading circuit 53 for despreading using the codes Ci and Cq.

The spread code generators 50i and 50q generate spread codes according to the control signal 43a supplied from the processing device 21. The synchronization acquisition circuit 51 despreads the received signals Di (t) and Dq (t) input from the signal radio unit 33 using the spreading codes Ci and Cq output from the spreading code generator, and performs QPSK. Demodulated correlation values Si (t), S
Output q (t). Start of synchronous acquisition (despreading) operation,
Correlation values Si (t), Sq by switching of switch 15
(t) is transmitted by the control signal 4 supplied from the processing device 21.
3c. The output of the synchronization acquisition circuit 51 is input to a peak detection circuit 52, and when a peak exceeding a predetermined threshold is detected, a spread code generator 50i is output by a synchronization acquisition signal 43b output from the peak detection circuit 52. 50q starts the spreading code phase shift operation.

When the synchronization is captured, the mode shifts to the synchronization tracking mode, and the despreading circuit 53 operates the spread code generators 50i,
The received signals Di (t) and Dq (t) are despread using the spreading codes Ci and Cq output from 0q, and a QPSK demodulated signal is output. The QPSK demodulated signal undergoes a predetermined demodulation process in a detection circuit 54, and is then corrected in an error correction decoder 55. The output of the error correction decoder 55 is supplied to an interface circuit 57 via a reception buffer 56. Is done.
The receiving signal is output to the internal bus 30 while the transmitting circuit 32B is operating for the control channel, and is output to the voice code decoding circuit 25 while operating for the traffic channel.

[0053]

As is apparent from the above description, according to the present invention, a code spread QPSK signal can be demodulated by a small number of accumulators and a simple matched filter, so that the circuit size of the despreader can be reduced. Power consumption can be reduced, and this is particularly effective for a battery-powered portable wireless terminal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a despreader and a synchronization acquisition circuit according to the present invention.

FIG. 2 is a diagram showing a second embodiment of the despreader and the synchronization acquisition circuit according to the present invention.

FIG. 3 is a diagram illustrating an example of a specific circuit configuration of a cyclic accumulation unit 103a illustrated in FIG. 2;

FIG. 4 is a diagram illustrating an example of a specific circuit configuration of a cyclic accumulation unit 103b illustrated in FIG. 2;

FIG. 5 is a diagram showing an embodiment of an accumulation register applied to the cyclic accumulation unit shown in FIGS. 3 and 4;

FIG. 6 is a diagram showing one embodiment of a wireless communication apparatus showing an application example of a despreader and a synchronization acquisition circuit according to the present invention.

FIG. 7 is a diagram showing a detailed configuration of a receiving circuit 32B shown in FIG.

FIG. 8 is a diagram showing the configuration of a conventional despreader using a received signal shift type matched filter.

FIG. 9 is a diagram showing a configuration of a received signal shift type matched filter 810 applied to the despreader of FIG.

10 is an accumulation register 6 applied to the despreader of FIG.
It is a figure showing composition of 30a.

FIG. 11 is a diagram showing an example of a configuration of a conventional despreader using a cyclic accumulation type matched filter.

12 is a diagram showing a configuration of a cyclic accumulation type matched filter 910 applied to the despreader of FIG.

[Explanation of symbols]

MF0 to MF15: matched filter, 101: multiplier, MQI, MII, MQQ, MIQ: multiplier, 10
2: coefficient register section, C0 to C15: coefficient register, 1
03: cyclic accumulation unit, 12, 13, ADD0 to ADD1
5: adder, 14, 1400 to 1415: accumulation register, 15a, 15b: output changeover switch, 50: spreading code generator, 51: synchronization acquisition circuit, 52: peak detection circuit, 53: despreading circuit.

Continued on the front page (72) Inventor Mei Suzuki 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 5K004 AA05 FA05 FG02 FH08 5K022 EE02 EE33

Claims (10)

[Claims] An I component reception signal Di (t) and a Q component reception signal Dq of a code spread QPSK modulation signal input in time series.
By despreading (t) for each chip with the I-component spreading code Ci and the Q-component spreading code Cq, a plurality of sequences of despread results corresponding to different combinations of the received signal and the spreading code are obtained for each of the chips. By generating and calculating the despread result of the plurality of sequences in a predetermined combination, Q
Generating demodulated values of an I component and a Q component of a PSK modulated signal for each of the chips, and cyclically accumulating the demodulated values of the I component and the Q component for each chip in accordance with a chip sequence of each spreading code. Characterized code-spread QP
A method of demodulating an SK modulation signal. 2. A method for sequentially updating coefficient values of respective chips of spreading codes Ci and Cq applied to despreading of the received signals Di (t) and Dq (t) at predetermined intervals, and The Q value according to claim 1, wherein the demodulated value for each chip is cyclically accumulated over at least one symbol period.
A demodulation method of a PSK modulation signal. 3. The method according to claim 1, wherein the received signals Di (t) and Dq (t) are oversampled and supplied, respectively, and the demodulated values of the I component and the Q component are generated a plurality of times during each chip period. Item 2. A method for demodulating a QPSK modulated signal according to item 1. 4. A chip sequence of at least a part of an I-component spread code Ci of a QPSK modulated signal and at least a part of a chip sequence of a Q-component spread code Cq are held. Calculates the I-component received signal Di (t) and the Q-component received signal Dq (t) of the code-spread QPSK modulated signal input in time series, and calculates a multiplication result DqCi (t) for each chip of the spread code. , DiCi (t), DqC
q (t) and DiCq (t); and for each chip of the spreading code, the DiCi (t) and DqC
By adding q (t) to the QPSK modulated signal,
Generate a partial value of the component and calculate DiCq from DqCi (t).
generating a partial value of the Q component of the QPSK modulated signal by subtracting (t); and cyclically accumulating the partial value of the I component and the partial value of the Q component in the sequence of the respective spreading code chip sequences. Code-spreading QPSK, comprising:
Demodulation method of modulated signal. 5. An I-component reception signal Di (t) and a Q-component reception signal Dq of a code spread QPSK modulation signal input in time series.
By despreading (t) for each chip with the I-component spreading code Ci and the Q-component spreading code Cq, a plurality of sequences of despread results corresponding to different combinations of the received signal and the spreading code are obtained for each of the chips. Means for generating an I-component demodulated value and a Q-component demodulated value of a QPSK modulated signal for each chip by calculating the despread results of the plurality of sequences in a predetermined combination. And a means for cyclically accumulating the I-component demodulated value and Q-component demodulated value generated for each chip in accordance with the respective spreading code chip sequences. A wireless communication device characterized by the above-mentioned. 6. A spread code generator, a receiving circuit for demodulating a transmission signal by despreading a received signal of code spread QPSK modulation with a spread code generated from the spread code generator, and the spread code generator. A synchronization acquisition circuit for synchronizing the generation of a spread code from the received signal with the reception signal, wherein the synchronization acquisition circuit is cascaded in a circular manner so as to return the output of the final stage to the initial stage. Each of the above-mentioned matched filters converts the I-component received signal Di (t) and the Q-component received signal Dq (t) of the code-spread QPSK modulated signal inputted in time series into I-component and Q-component received signals. The multiplication result is multiplied by the spreading codes Ci and Cq at the specific chip position in the component spreading code, and the operation result DqCi
(t), DiCi (t), DqCq (t) and DiCq (t)
, And a QPS based on the operation results DiCi (t) and DqCq (t).
Means for generating a partial demodulated value corresponding to the I component of the K modulated signal, and generating a partial demodulated value corresponding to the Q component of the QPSK modulated signal from the DqCi (t) and DiCq (t); The component and Q component partial demodulation values are respectively added to the I and Q component accumulated demodulation values supplied from the preceding or final stage matched filter, and the addition result is added to the next or first stage matched filter. Means for supplying a component as an accumulated demodulated value. 7. A spread code generator for generating an I component spread code Ci and a Q component spread code Cq of a QPSK modulated signal, and a spread code Ci generated from the spread code generator for receiving a code spread QPSK modulated received signal. , Cq, a receiving circuit for demodulating the transmission signal by despreading, and a synchronization acquisition circuit for synchronizing the generation of the spreading codes Ci, Cq from the spreading code generator with the reception signal,
A first register circuit for holding at least a part of a chip sequence of the spreading code Ci supplied from the spreading code generator; and at least one of a spreading code Cq supplied from the spreading code generator. A second register circuit for holding the chip sequence of the unit, the chip sequences for the held spread codes Ci and Cq, and the I-component reception signal Di (D) of the code spread QPSK modulation signal input in time series. t) and Q component received signal Dq
(t), and multiply results DqCi (t), DiCi (t), DqCq (t) and Di for each chip of the spreading code.
A plurality of multiplier groups for generating Cq (t), and the DiCi (t) and DqC for each chip of the spreading code.
and q (t) to obtain the IPS of the QPSK modulated signal.
A first cyclic accumulation circuit for generating partial demodulated values of components and cyclically accumulating each partial demodulated value in the sequence of the sequence of spreading code chips, and for each chip of the spreading code, from the DqCi (t) Di
By subtracting Cq (t), the QPSK modulated signal Q
The wireless communication system according to claim 7, further comprising a second cyclic accumulation circuit that generates partial demodulated values of the components and cyclically accumulates each partial demodulated value in the sequence of the spreading code chip sequence. apparatus. 8. The first and second register circuits each store a plurality of register areas arranged in the order of a chip sequence and a spreading code Ci or Cq supplied from the spreading code generator in each of the register areas. A latch signal supply circuit for sequentially storing data in units of units, wherein each of the multiplier groups includes a plurality of multipliers corresponding to the number of register areas of the first and second register circuits, respectively. Outputting a multiplication result of the spread code held in the register area and the I-component received signal Di (t) or the Q-component received signal Dq (t) in a time-series manner. The wireless communication device according to claim 1. 9. A plurality of adders or subtractors corresponding to a plurality of multipliers in each of the multiplier groups, and an operation result of each of the adders or subtractors, wherein the first and second cyclic accumulation circuits are provided. , And a plurality of registers to be supplied to the next-stage adder or subtractor, and the last-stage register selects the output of the register to an external circuit or the first-stage adder or subtractor. The wireless communication device according to claim 8, further comprising a changeover switch for performing a transfer. 10. Each of the registers constituting the first and second cyclic accumulation circuits comprises a plurality of storage areas and means for cyclically selecting a storage area in which data is to be written and read. 10. The radio according to claim 9, wherein the operation result of the adder or the subtractor written in each of the storage areas is read out after a predetermined time and output to the next-stage adder or subtractor. Communication device.