CN109951173B - FIR filtering method and filter for multi-channel parallel input and parallel processing - Google Patents
FIR filtering method and filter for multi-channel parallel input and parallel processing Download PDFInfo
- Publication number
- CN109951173B CN109951173B CN201910167215.5A CN201910167215A CN109951173B CN 109951173 B CN109951173 B CN 109951173B CN 201910167215 A CN201910167215 A CN 201910167215A CN 109951173 B CN109951173 B CN 109951173B
- Authority
- CN
- China
- Prior art keywords
- processed
- signal
- signals
- input
- signal set
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Complex Calculations (AREA)
- Image Processing (AREA)
Abstract
The invention discloses a multi-path parallel input parallel processing FIR filtering method and a filter, wherein N paths of parallel input data are delayed according to a grouping delay method and then are sent into N groups of cache shift registers, the cache shift registers are shifted according to a parallel shift method, then the data in the N groups of shift registers are simultaneously sent into N paths of parallel filtering modules, the obtained N points are respectively used as one point in N paths of filtering data, and the steps are repeated until all the filtering data are obtained. The method provided by the invention improves the frequency range of the FPGA for processing the high-speed signal, and can solve the problem of filtering the current and future high-speed and ultra-high-speed signals in the FPGA.
Description
Technical Field
The invention relates to an FIR filtering method, in particular to an FIR filtering method and a filter for multi-path parallel input and parallel processing.
Background
The FIR filter is the most basic element in a digital signal processing system, has a linear phase-frequency characteristic, and has a Finite unit sampling Response, so that the FIR filter can realize a stable system. The traditional FIR filter can only adapt to multiple paths of antenna data for processing by configuring multiple sets of FIR filters, and can meet the requirement of data real-time processing, but along with the continuous increase of the antenna scale, the scheme of using multiple sets of FIR filters can obviously increase the corresponding hardware overhead, and can not meet the filtering requirement of low consumption and high speed.
The parallel algorithm means that a data stream is subjected to serial-parallel conversion before entering an FIR filter, then the interior of the FIR filter performs parallel processing on multi-channel data, and the multi-channel data to be output is output after being subjected to parallel-serial conversion after being subjected to multi-channel operation.
The prior method provides a parallel FIR filtering method and a filter, designs a serial input parallel processing FIR filter, and reduces the hardware overhead by pre-accumulation, but the prior method can not be used in high-speed signal processing because of the requirement of serial input.
Disclosure of Invention
The invention aims to provide a multi-path parallel input and parallel processing FIR filtering method and filter, which are used for solving the problems of low filtering speed, low efficiency and the like caused by the fact that the parallel FIR filtering method and filter in the prior art cannot realize parallel input.
In order to realize the task, the invention adopts the following technical scheme:
a multi-path parallel input and parallel processing FIR filtering method is used for filtering N series of input signal sequences, wherein one series of input signal sequences comprises a plurality of input signals, N is an integer greater than 1, and the method is implemented according to the following steps:
step 1, after steps 1.1-1.6 are executed for a plurality of times, obtaining a plurality of output signals:
step 1.1, simultaneously inputting one input signal in each series of input signal sequences to obtain the 1 st input signal set S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N Wherein the 1 st set of input signals comprises N input signals, x 1i For the ith input signal in the 1 st input signal set, i belongs to N;
copying N-1 times of the input signal set to obtain N input signal sets:
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
wherein S is i For the ith input signal set, x ii Is the ith input signal in the ith input signal set;
step 1.2, when i =1, 2, \ 8230, N-1, for the ith input signal set S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN Grouping to obtain the ith first signal set C to be processed i ＝{x i1 ,x i2 ,…,x ii And the ith set of delayed signals D i ＝{x ii+1 ,x ii+2 ,…,x iN }；
When i = N, for the Nth input signal set S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN Dividing into groups to obtain the Nth first signal set C to be processed N ＝S N And Nth delayed signal set
Repeating the step 1.2 until N first to-be-processed signal sets processed this time and N delayed signal sets processed this time are obtained;
step 1.3, combining the ith first to-be-processed signal set processed this time with the ith delay signal set processed last time to obtain an ith second to-be-processed signal set, wherein when the processing of this time is the 1 st processing, each delay signal set processed last time is an empty set;
repeating the step 1.3 until N second signal sets to be processed are obtained;
step 1.4, simultaneously performing parallel shift processing on all second signals to be processed in each second signal set to be processed to obtain N third signal sets to be processed;
step 1.5, simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering mode;
step 1.6, outputting N output signals;
and 2, collecting the plurality of output signals according to the sequence executed in the step 1 to obtain N series of filtered signal sequences.
Further, in step 1.4, when all the second signals to be processed in each second signal set to be processed are shifted in parallel, the unit of shifting is N bits, and N third signal sets to be processed are obtained.
Further, the step 1.5 of simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering manner specifically includes:
point-multiplying each third processing signal with a filter coefficient respectively to obtain a plurality of point-multiplied third processing signals;
and summing all the dot-multiplied third processed signals to obtain an output signal.
A multi-path parallel input and parallel processing FIR filter comprises an input module and an output module, and also comprises a grouping processing module, a signal merging module, a buffer shift register and a filtering module;
the input module is used for simultaneously inputting one input signal in each series of input signal sequences to obtain a 1 st input signal set S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N Wherein the 1 st set of input signals comprises N input signals, x 1i For the ith input signal in the 1 st input signal set, i belongs to N;
and is further configured to copy N-1 back to the set of input signals to obtain a total of N sets of input signals:
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
wherein S is i For the ith input signal set, x ii Is the ith input signal in the ith input signal set;
the grouping processing module is used for judging that when i =1, 2, \8230andN-1, the ith input signal set S is subjected to i ＝{x i1 ,x i2 ,…,x ii ,…,x iN Grouping to obtain the ith first signal set C to be processed i ＝{x i1 ,x i2 ,…,x ii And the ith set of delayed signals D i ＝{x ii+1 ,x ii+2 ,…,x iN }；
When i = N, for the Nth input signal set S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN Dividing into groups to obtain the Nth first signal set C to be processed N ＝S N And Nth delayed signal set
Obtaining N first to-be-processed signal sets processed this time and N delayed signal sets processed this time;
the signal merging module is used for merging the ith first to-be-processed signal set processed this time with the ith delay signal set processed last time to obtain an ith second to-be-processed signal set, and when the processing of this time is the 1 st processing, each delay signal set processed last time is an empty set;
obtaining N second signal sets to be processed;
the buffer shift register is used for simultaneously carrying out parallel shift processing on all second signals to be processed in each second signal set to be processed to obtain N third signal sets to be processed;
the filtering module is used for simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering mode;
the output module is used for outputting the N output signals;
and is further configured to aggregate the output signals to obtain N series of filtered signal sequences.
Furthermore, the buffer shift register comprises a plurality of data bits, and each data bit is used for registering a second signal to be processed.
Further, the filtering module comprises a dot product module and a summation module;
the dot multiplication module comprises a plurality of filter coefficients, and is used for dot-multiplying each third processing signal with the filter coefficients to obtain a plurality of dot-multiplied third processing signals;
and the summation module is used for summing the third processing signals obtained by multiplying all the points to obtain an output signal.
Furthermore, the number of the data bits of the cache shift register is the same as the number of the filter coefficients in the filter module.
Compared with the prior art, the invention has the following technical characteristics:
1. the FIR filtering method and the filter for multi-channel parallel input and parallel processing realize the function of parallel input of signals by grouping and delaying the signals, realize the full parallel processing of high-speed signals from input to output and improve the processing speed of the signals;
2. the traditional serial filtering algorithm can only process one data in one period, the FIR filtering method and the filter for multi-path parallel input and parallel processing provided by the invention output through N paths of parallel input and processing, the operation clock is 1/N of the output rate, and the signal processing of N times of the rate can be realized under the drive of a low-speed clock.
Drawings
FIG. 1 is a schematic diagram of an FIR filter architecture provided in one embodiment of the present invention;
fig. 2 is a schematic diagram of parallel shift of a buffer shift register according to an embodiment of the present invention.
Detailed Description
FIR filter: the finite-length single-bit impulse response filter, also called non-recursive filter, is the most basic element in a digital signal processing system, and can ensure any amplitude-frequency characteristic and simultaneously have strict linear phase-frequency characteristic, and the unit sampling response of the finite-length single-bit impulse response filter is finite.
Parallel shift processing: data is input in parallel, and each time pulse data is output after being shifted to the left or right by a plurality of data bits, generally one data bit.
A buffer shift register: the data is input into the device in a parallel or serial mode, then each time pulse is sequentially shifted to the left or the right by one bit and stored, and the data is output at an output end, can be used for registering codes, and can also be used for realizing serial-parallel conversion of the data, numerical value operation and data processing.
And (3) filter coefficient: the index is used for expressing the steep degree of both sides of the channel filtering frequency amplitude characteristic, generally, the value of the ratio of the 6dB bandwidth and the 60dB bandwidth of a channel is closer to 1, and the steeper the filtering characteristic is, the more ideal the selectivity is.
The FIR filter in the prior art is generally implemented based on a convolution structure, and the FIR filter implemented based on the convolution structure is simple in structure and easy to implement, but has a problem that the calculation delay is too large, for example, an input signal sequence with a length of M, each period sequentially inputs a value into the FIR filter, and M periods are required to obtain an output with a length of M points in total, but as the data throughput of a digital peer-to-peer system is larger and larger, the processing speed of the FIR filter gradually becomes a bottleneck.
Example one
In this embodiment, a FIR filtering method for multi-channel parallel input and parallel processing is disclosed, which is used for filtering N series of input signal sequences, where a series of input signal sequences includes a plurality of input signals, N is an integer greater than 1, and is characterized in that steps 1.1-1.6 are performed multiple times to obtain N series of output signal sequences.
In order to increase the signal processing speed, the N series of input signals are processed simultaneously, but only N signals can be processed in one period, so that the N series of input signals are sequentially filtered in the sequence of the signals in the sequence.
The invention is implemented according to the following steps:
step 1, after steps 1.1-1.6 are executed for a plurality of times, obtaining a plurality of output signals:
step 1.1, simultaneously inputting an input signal in each series of input signal sequences to obtain a 1 st input signal set S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N Wherein the 1 st set of input signals comprises N input signals, x 1i For the ith input signal in the 1 st input signal set, i belongs to N;
copying N-1 times the input signal set to obtain N input signal sets:
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
wherein S is i For the ith input signal set, x ii Is the ith input signal in the ith input signal set;
in the embodiment, N series of input signal sequences are processed, each series of input signal sequences includes a plurality of input signals; in this step, one input signal in each series of input signals is input simultaneously to obtain a set of input signals, e.g. in the first cycle, the set of input signals obtained is S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N -a total of N input signals;
in this step, it is also necessary to copy the input signal set S times 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N When the input signal is input, the input sequence number set S is copied for N-1 times to obtain N input signal sets, and the input signals in each input signal set are completely the same.
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
I.e. x 11 ＝x 21 ＝x i1 ＝x N1 ，x 12 ＝x 22 ＝x i2 ＝x N2 ，x 1i ＝x 2i ＝x ii ＝x Ni ，x 1N ＝x 2N ＝x iN ＝x NN 。
Step 1.2, when i =1, 2, \ 8230, N-1, for the ith input signal set S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN Grouping to obtain the ith first signal set C to be processed i ＝{x i1 ,x i2 ,…,x ii And the ith set of delayed signals D i ＝{x ii+1 ,x ii+2 ,…,x iN }；
When i = N, for the Nth input signal set S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN Dividing into groups to obtain the Nth first signal set C to be processed N ＝S N And Nth delayed signal set
Repeating the step 1.2 until N first to-be-processed signal sets processed this time and N delayed signal sets processed this time are obtained;
in this step, in order to increase the speed of signal processing, all the signals in the input signal set are subjected to grouping processing, that is, N input signals in the N input signal sets are all subjected to grouping processing.
For example, when step 1.1 to step 1.6 are performed at the 1 st time, all signals in the N input signal sets shown below are grouped, which specifically includes:
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
for the 1 st input signal set S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N Taking the first 1 input signals as the first signals to be processed of this time, and the rest other signals as the delayed signals of this time, so that the first input signal set is divided into the first signal set to be processed C 1 ＝{x 11 And a first set of delayed signals D 1 ＝{x 12 ,…,x 1i ,…,x 1N }；
For the 2 nd input signal set S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N The first 2 input signals are used as the first signal to be processed of this time, and the rest other signals are used as the delay signals of this time, so that the second input signal set is divided into the second first signal set to be processed C 2 ＝{x 21 ,x 22 And a second set of delayed signals D 2 ＝{x 23 ,…,x 2N }；
In the above order, for the Nth input signal set S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN The first N input signals are used as the first signals to be processed of the current time, and the rest other signals are used as the delay signals of the current time, so that the Nth input signal set is divided into an Nth first signal set to be processed C N ＝S N And Nth delayed signal set
In the 2 nd execution of steps 1.1 to 1.6, the N input signal sets are:
S 1 ＝{y 11 ,y 12 ,…,y 1i ,…,y 1N }
S 2 ＝{y 21 ,y 22 ,…,y 2i ,…,y 2N }
…
S i ＝{y i1 ,y i2 ,…,y ii ,…,y iN }
…
S N ＝{y N1 ,y N2 ,…,y Ni ,…,y NN }
the above multiple sets of the 2 nd processed first to-be-processed signal and the 2 nd processed delayed signal can be obtained as follows:
first set of signals to be processed of the 2 nd processing
And a first set of delayed signals
2 nd first set of signals to be processed of 2 nd processing
And 2 nd set of delayed signals
Nth of 2 nd treatmentFirst set of signals to be processed
And Nth delayed signal set
Step 1.3, combining the ith first to-be-processed signal set processed this time with the ith delay signal set processed last time to obtain an ith second to-be-processed signal set, wherein when the processing of this time is the 1 st processing, each delay signal set processed last time is an empty set;
repeating the step 1.3 until N second signal sets to be processed are obtained;
in this embodiment, when step 1.1-step 1.6 are performed for the 1 st time, through step 1.2, N first to-be-processed signal sets and N delayed signal sets are obtained, and then when N second to-be-processed signal sets are obtained, the N first to-be-processed signal sets are directly taken as the N second to-be-processed signal sets.
When step 1.1 to step 1.6 are performed for the 2 nd time, through step 1.2, N first sets of signals to be processed and N sets of delayed signals are obtained, where the N first sets of signals to be processed are all obtained during the 2 nd time processing, and the N first sets of signals to be processed obtained during the 2 nd time processing and the N sets of delayed signals obtained during the 1 st time processing are combined, for example:
1 st first signal to be processed obtained in the 2 nd processing is set
With the 1 st set D of delayed signals obtained at the 1 st processing 1 ＝{x 21 ,x 31 ,…,x N1 Combining to obtain the 1 st second signal set to be processed { y } 12 ,x 21 ,x 31 ,…,x N1 }；
The 2 nd first signal to be processed obtained in the 2 nd processing is collected
And 1 st pointSet D of 2 nd delayed signals obtained in time 2 ＝{x 31 ,…,x N1 Combining to obtain a 2 nd second signal set to be processed { y } 12 ,y 22 ,x 31 ,…,x N1 }。
Step 4, simultaneously carrying out parallel shift processing on all second signals to be processed in each second signal set to be processed to obtain N third signal sets to be processed;
in this step, when performing parallel shift processing on signals, a common method in the prior art is to shift each signal simultaneously by 1 bit to the right or left.
In the present invention, in order to improve the processing efficiency, as a preferred processing method, when performing parallel shift processing on all second signals to be processed in each second signal set to be processed at the same time in step 1.4, the unit of movement is N bits, so as to obtain N third signal sets to be processed;
in this embodiment, when the parallel shift processing of N bits is performed, each signal in the initial state in the third set of signals to be processed is a random signal.
The following explains the parallel shift process, where the initial state of the third set of signals to be processed is shown in table 1, the number of signals in the third set of signals to be processed is 12 bits, and the number of input signals is 3.
TABLE 1 initial state table of third signal set to be processed
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| A | B | C | D | E | F | G | H | I | J | K | L |
For the second to-be-processed signal set which needs to be subjected to parallel shift processing, namely, there is one second to-be-processed signal, when performing shift, the signal a on the D0 bit is shifted to the D3 bit, the signal D on the D3 bit is shifted to the D6 bit, the signal G on the D6 bit is shifted to the D9 bit, and the signal J on the D9 bit overflows; now, signal 1 in the second set of signals to be processed is placed at bit D0, and a third set of signals to be processed is obtained, as shown in table 2.
TABLE 2 third pending signal set status table
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| 1 | B | C | A | E | F | D | H | I | G | K | L |
For the second to-be-processed signal set that needs to be subjected to parallel shift processing, which is {1,2}, that is, there are two second to-be-processed signals, then in shifting, in table 1, signals a and B on D0 bit and D1 bit are shifted to D3 bit and D4 bit, signals D and F on D3 bit and D4 bit are shifted to D6 bit and D7 bit, signals G and H on D6 bit and D7 bit are shifted to D9 bit and D10 bit, and signals J and K on D9 bit and D10 bit are overflowed; at this time, signal 1 and signal 2 in the second set of signals to be processed are placed in the D0 bit and D1 bit, and at this time, a third set of signals to be processed is obtained, which is shown in table 3.
Table 3 third pending signal set state table
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| 1 | 2 | C | A | B | F | D | E | I | G | H | L |
Similarly, for the second set of signals to be processed that need to be subjected to parallel shift processing, which is {1,2, 3}, i.e., there are three second signals to be processed, the third signals to be processed are obtained as shown in table 4.
Table 4 initial state table of third signal set to be processed
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| 1 | 2 | 3 | A | B | C | D | E | F | G | H | I |
Therefore, the parallel shift processing method stores N paths of input data into the first N data bits, and stores data in data bits with sequence number 1+ k × N to N + k × N into data bits with sequence number 1+ (1 + k) × N to N + (k + 1) × N in the next cycle, where k =0,1, \\ 8230, and Y/N, where Y is the total number of data bits or the total number of signals in the third signal set to be processed.
Step 1.5, simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering mode;
in this step, all the third signals to be processed in the third signal set to be processed are combined into one output signal, and the combining method specifically includes:
point-multiplying each third processing signal with a filter coefficient respectively to obtain a plurality of point-multiplied third processing signals;
and summing all the dot-multiplied third processed signals to obtain an output signal.
In this embodiment, if the third set of signals to be processed is { t } 1 ,t 2 ,t 3 ,…,t N H, the set of filter coefficients is k 1 ,k 2 ,k 3 ,…,k N Then the output signal is
And step 1.6, outputting N output signals.
And 2, collecting the output signals according to the sequence executed in the step 1 to obtain N series of filtered signal sequences.
And combining the obtained plurality of output signals according to the sequence of executing the steps 1.1-1.6 for a plurality of times to obtain an output signal sequence.
The method provided by the invention can be realized in an FPGA and a system based on a singlechip, particularly in the FPGA, because the highest running speed C of the FPGA is mainly limited by the manufacturing process, the parallel processing method can realize the filtering processing with the output speed of N x C, the traditional method can only realize the filtering processing with the output speed of C, and the frequency range of the FPGA for processing high-speed signals is improved.
Example two
In this embodiment, a 3-way parallel input 3-way parallel processing model is taken as an example, and the method of the present invention is further described.
Filtering 3 series of input signal sequences, wherein a series of input signal sequences comprises a plurality of input signals.
In this embodiment, the 3 series input signal sequences are respectively:
Y 1 ＝{x 11 ,x 12 ,x 13 }
Y 2 ＝{x 21 ,x 22 ,x 23 }
Y 3 ＝{x 31 ,x 32 ,x 33 }
each series of input signal sequences comprises 3 input signals, so 3 times of executing steps 1.1-1.6 obtain 3 series of output signal sequences:
step 1.1, simultaneously inputting an input signal in each series of input signal sequences to obtain an input signal set, wherein the input signal set comprises 3 input signals;
copying 2 times the input signal set to obtain 3 input signal sets;
in this embodiment, the 1 st time step 1.1 is performed, the input signal set is S 1 ＝{x 11 ,x 21 ,x 31 In the 2 nd execution of step 1.1, the input signal set is S 2 ＝{x 12 ,x 22 ,x 32 In the 3 rd execution of step 1.1, the input signal set is S 3 ＝{x 13 ,x 23 ,x 33 }。
In the 1 st execution of step 1.1, the input signal sets are copied for 2 times to obtain 3 input signal sets
In the 2 nd execution of step 1.1, the input signal sets are copied for 2 times to obtain 3 input signal sets
Likewise, step 1.1 is performed 3 rd time to obtain
Step 2, simultaneously dividing all input signals in each input signal set into a first signal set to be processed and a delay signal set to obtain N first signal sets to be processed and N delay signal sets to be processed;
in this embodiment, step 1.2 is performed the 1 st time, 3 input signal sets are collected
Wherein for the 1 st input signal set, the input signals are divided into a first set of signals to be processed
And a first set of delayed signals
For the 2 nd input signal set, dividing into the 2 nd first signal set to be processed
And 2 nd set of delayed signals
For the 3 rd input signal set, dividing into the 3 rd first signal set to be processed
And 3 rd set of delayed signals
Step 1.2, step 2, set of 3 input signals
Wherein for the 1 st input signal set, the input signals are divided into a first set of signals to be processed
And a first set of delayed signals
For the 2 nd input signal setIs divided into the 2 nd first signal set to be processed
And 2 nd set of delayed signals
For the 3 rd input signal set, dividing into the 3 rd first signal set to be processed
And 3 rd set of delayed signals
For the 3 rd time step 1.2 is performed, 3 input signal sets are collected
Wherein for the 1 st input signal set, the input signals are divided into a first set of signals to be processed
And a first set of delayed signals
For the 2 nd input signal set, dividing into the 2 nd first signal set to be processed
And 2 nd set of delayed signals
For the 3 rd input signal set, dividing into the 3 rd first signal set to be processed
And 3 rd set of delayed signals
Step 1.3, simultaneously combining each first signal set to be processed of the current processing with each delay signal set processed at the last time to obtain 3 second signal sets to be processed;
in this embodiment, for the 1 st time of performing step 1.3, the first and second sets of signals to be processed { x } 11 H, a 2 nd second set of signals to be processed { x 11 ，x 21 And a 3 rd second set of signals to be processed { x } 11 ，x 21 ,x 31 }。
For the 2 nd time of step 1.3, the first signal set to be processed of this time processing
And the first set of delayed signals of order 1
Combining to obtain the 1 st 2 nd signal set to be processed { x 12 ,x 21 ,x 31 }; for the 2 nd first signal set to be processed of the current processing
And the 2 nd delayed signal set of 1 st time
Combining to obtain the 2 nd signal set to be processed { x 12 ，x 22 ,x 31 }; for the 3 rd first signal set to be processed of the current processing
And the 3 rd delayed signal set of the 1 st time
Combining to obtain the 3 nd 2 nd signal set to be processed { x 12 ，x 22 ,x 32 }。
For the 3 rd time of executing step 1.3, the first signal set to be processed of the current processing
And the 2 nd first set of delayed signals
Combining to obtain the 1 st second signal set to be processed { x 13 ,x 22 ,x 32 }; for the 2 nd first signal set to be processed of the current processing
And 2 nd delayed signal set of 2 nd time
Combining to obtain the 2 nd second signal set to be processed { x } 32 ，x 13 ，x 23 }; for the 3 rd first signal set to be processed of the current processing
And the 3 rd delayed signal set of 1 st time
Combining to obtain the 3 rd second signal set to be processed { x 13 ，x 23 ,x 33 }。
Step 1.4, simultaneously carrying out parallel shift processing on all second signals to be processed in each second signal set to be processed to obtain N third signal sets to be processed;
in this embodiment, for the 1 st time of performing step 1.4, the first and second sets of signals to be processed { x } are processed 11 H, a 2 nd second set of signals to be processed { x 11 ，x 21 And a 3 rd second set of signals to be processed { x } 11 ，x 21 ,x 31 Carry on the parallel shift processing, the result obtained is shown in table 5.
TABLE 5 third pending signal set State Table
In this embodiment, for the 2 nd time when step 1.4 is performed, the first and second sets of signals to be processed { x } are processed 12 ,x 21 ,x 31 H, a 2 nd second set of signals to be processed { x 12 ，x 22 ,x 31 And a 3 rd second set of signals to be processed { x } 12 ，x 22 ,x 32 Carry on the parallel shift processing, the result obtained is shown in table 6.
TABLE 6 third pending signal set status table
In this embodiment, for the 3 rd execution of step 1.4, the 1 st second set of signals to be processed { x } 13 ,x 22 ,x 32 H, a 2 nd second set of signals to be processed { x 32 ，x 13 ，x 23 And a 3 rd second set of signals to be processed { x } 13 ，x 23 ,x 33 Carry on the parallel shift processing, the result obtained is shown in table 7.
TABLE 7 third pending signal set State Table
Step 1.5, simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering mode;
in this embodiment, 3 third to-be-processed signal sets obtained at the 1 st time are combined to obtain 3 output signals;
combining 3 third to-be-processed signal sets obtained in the 2 nd time to obtain 3 output signals;
combining 3 third to-be-processed signal sets obtained in the 3 rd time to obtain 3 output signals;
step 1.6, outputting N output signals;
when step 1.6 is executed for the 1 st time, 3 output signals { X1, Y1, Z1} are obtained;
when step 1.6 is executed for the 2 nd time, 3 output signals { X2, Y2, Z2} are obtained;
when step 1.6 is executed for the 3 rd time, 3 output signals { X3, Y3, Z3} are obtained;
and 2, collecting the plurality of output signals to obtain N series of filtered signal sequences.
In this embodiment, the output signals obtained 3 times are combined, X1, X2, and X3 are combined to obtain a first series of output signal sequences, Y1, Y2, and Y3 are combined to obtain a second series of output signal sequences, Z1, Z2, and Z3 are combined to obtain a third series of output signal sequences, and 3 series of output signal sequences are obtained in total.
EXAMPLE III
In this embodiment, as shown in fig. 1, a multi-channel parallel input and parallel processing FIR filter is disclosed, which includes an input module and an output module, and the FIR filter further includes a grouping processing module, a signal combining module, a buffer shift register and a filtering module;
the input module is used for simultaneously inputting one input signal in each series of input signal sequences to obtain a 1 st input signal set S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N Wherein the 1 st set of input signals comprises N input signals, x 1i For the ith input signal in the 1 st input signal set, i belongs to N;
and for replicating N-1 back to said set of input signals to obtain a total of N sets of input signals:
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
wherein S is i For the ith input signal set, x ii Is the ith input signal in the ith input signal set;
the grouping processing module is used for judging that when i =1, 2, \8230andN-1, the ith input signal set S is subjected to i ＝{x i1 ,x i2 ,…,x ii ,…,x iN Grouping to obtain the ith first signal set C to be processed i ＝{x i1 ,x i2 ,…,x ii And the ith set of delayed signals D i ＝{x ii+1 ,x ii+2 ,…,x iN }；
When i = N, for the Nth input signal set S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN Dividing into groups to obtain the Nth first signal set C to be processed N ＝S N And Nth delayed signal set
Obtaining N first to-be-processed signal sets processed this time and N delayed signal sets processed this time;
in this embodiment, the packet processing module delays N inputs of different shift register groups according to the serial number of each buffer shift register group, and for the ith buffer shift register group, delays input data with serial number greater than i in N inputs of the buffer shift register by one beat and then simultaneously uses the delayed input data and the previous i inputs as N input data of the buffer shift register.
The signal merging module is used for merging the ith first to-be-processed signal set processed this time with the ith delay signal set processed last time to obtain an ith second to-be-processed signal set, and when the processing of this time is the 1 st processing, each delay signal set processed last time is an empty set;
obtaining N second signal sets to be processed;
the buffer shift register is used for simultaneously carrying out parallel shift processing on all second signals to be processed in each second signal set to be processed to obtain N third signal sets to be processed;
in this embodiment, the buffer shift register has N input ports, and the buffer shift register has Y registers, the number of which is the same as that of the filter coefficients, and Y output ports.
In this embodiment, as shown in fig. 2, the parallel shift operation of the buffer shift register is to store N channels of input data into the first N registers, and store signals in the registers with sequence numbers of 1+ (1 + k) × N-N + (k + 1) × N in the next cycle, where k =0,1, \\8230;, Y/N.
For example, the 1 st, 2 nd and 3 rd inputs of the buffer shift register are respectively stored in a register D0, a register D1 and a register D2, and the operations of storing the data in the register D0 into a register D3, storing the data in the register D3 into a register D6, storing the data in the register D6 into a register D9, storing the data in the register D1 into a register D4, storing the data in the register D4 into a register D7, storing the data in the register D7 into a register D10, storing the data in the register D2 into a register D5, storing the data in the register D5 into a register D8 and storing the data in the register D8 into a register D11 are simultaneously executed in each cycle according to the parallel shift method.
The filtering module is used for simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering mode;
the output module is used for outputting the N output signals;
and is further configured to aggregate the output signals to obtain N series of filtered signal sequences.
Optionally, the buffer shift register includes a plurality of data bits, and each data bit is used for registering a second signal to be processed.
Optionally, the filtering module includes a dot product module and a summation module;
the dot multiplication module comprises a plurality of filter coefficients, and is used for dot-multiplying each third processing signal with the filter coefficients to obtain a plurality of dot-multiplied third processing signals;
and the summation module is used for summing the third processing signals obtained by multiplying all the points to obtain an output signal.
In this embodiment, the Y buffered data in the buffer shift register in the filtering module is dot-multiplied and summed with the Y coefficients of the filter.
Optionally, the number of data bits of the buffer shift register is the same as the number of filter coefficients in the filter module.
In this embodiment, 12 register data in the buffer shift register are all output to the filtering module every cycle, 12 filter tap coefficients are stored in the filtering module, and the 12 filter tap coefficients are multiplied by the 12 register data one by one, summed, and output as a result of parallel filtering. In fig. 1, 3 buffer shift registers are identical, and 3 filter modules are also identical.
Claims (7)
1. A multi-path parallel input and parallel processing FIR filtering method for filtering N series of input signal sequences, wherein a series of input signal sequences comprises a plurality of input signals, N is an integer greater than 1, characterized by the following steps:
step 1, after steps 1.1-1.6 are executed for a plurality of times, obtaining a plurality of output signals:
step 1.1, simultaneously inputting one input signal in each series of input signal sequences to obtain the 1 st input signal set S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N Wherein the 1 st set of input signals comprises N input signals, x 1i For the ith input signal in the 1 st input signal set, i belongs to N;
copying N-1 times the input signal set to obtain N input signal sets:
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
wherein S is i For the ith input signal set, x ii Is the ith input signal in the ith input signal set;
step 1.2, when i =1, 2, \ 8230, N-1, for the ith input signal set S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN Grouping to obtain the ith first signal set C to be processed i ＝{x i1 ,x i2 ,…,x ii And the ith set of delayed signals D i ＝{x ii+1 ,x ii+2 ,…,x iN }；
When i = N, for the Nth input signal set S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN Dividing into groups to obtain the Nth first signal set C to be processed N ＝S N And Nth delayed signal set
Repeating the step 1.2 until N first to-be-processed signal sets processed this time and N delayed signal sets processed this time are obtained;
step 1.3, combining the ith first to-be-processed signal set processed this time with the ith delay signal set processed last time to obtain an ith second to-be-processed signal set, wherein when the processing of this time is the 1 st processing, each delay signal set processed last time is an empty set;
repeating the step 1.3 until N second signal sets to be processed are obtained;
step 1.4, simultaneously carrying out parallel shift processing on all second signals to be processed in each second signal set to be processed to obtain N third signal sets to be processed;
step 1.5, simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering mode;
step 1.6, outputting N output signals;
and 2, collecting the plurality of output signals according to the sequence executed in the step 1 to obtain N series of filtered signal sequences.
2. The FIR filtering method with multi-channel parallel input and parallel processing as claimed in claim 1, wherein said step 1.4, when all the second signals to be processed in each second signal set to be processed are shifted in parallel, the unit of shift is N bits, so as to obtain N third signal sets to be processed.
3. The FIR filtering method with multi-channel parallel input and parallel processing according to claim 2, wherein the step 1.5 of combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering manner at the same time specifically comprises:
point-multiplying each third processing signal with a filter coefficient respectively to obtain a plurality of point-multiplied third processing signals;
and summing the third processed signals multiplied by all the points to obtain an output signal.
4. A multi-path parallel input and parallel processing FIR filter comprises an input module and an output module, and is characterized in that the FIR filter also comprises a grouping processing module, a signal merging module, a buffer shift register and a filtering module;
the input module is used for simultaneously inputting one input signal in each series of input signal sequences to obtain a 1 st input signal set S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N Wherein the 1 st set of input signals comprises N input signals, x 1i For the ith input signal in the 1 st input signal set,i∈N；
and for replicating N-1 back to said set of input signals to obtain a total of N sets of input signals:
S 1 ＝{x 11 ,x 12 ,…,x 1i ,…,x 1N }
S 2 ＝{x 21 ,x 22 ,…,x 2i ,…,x 2N }
…
S i ＝{x i1 ,x i2 ,…,x ii ,…,x iN }
…
S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN }
wherein S is i For the ith input signal set, x ii Is the ith input signal in the ith input signal set;
the grouping processing module is used for judging that when i =1, 2, \8230andN-1, the ith input signal set S is subjected to i ＝{x i1 ,x i2 ,…,x ii ,…,x iN Grouping to obtain the ith first signal set C to be processed i ＝{x i1 ,x i2 ,…,x ii And the ith set of delayed signals D i ＝{x ii+1 ,x ii+2 ,…,x iN }；
When i = N, for the Nth input signal set S N ＝{x N1 ,x N2 ,…,x Ni ,…,x NN Dividing into groups to obtain the Nth first signal set C to be processed N ＝S N And Nth delayed signal set
Obtaining N first to-be-processed signal sets processed this time and N delayed signal sets processed this time;
the signal merging module is used for merging the ith first to-be-processed signal set processed this time with the ith delay signal set processed last time to obtain an ith second to-be-processed signal set, and when the processing of this time is the 1 st processing, each delay signal set processed last time is an empty set;
obtaining N second signal sets to be processed;
the buffer shift register is used for simultaneously carrying out parallel shift processing on all second signals to be processed in each second signal set to be processed to obtain N third signal sets to be processed;
the filtering module is used for simultaneously combining all the third signals to be processed in each third signal set to be processed into one output signal in a filtering mode;
the output module is used for outputting N output signals;
and is further configured to aggregate the output signals to obtain N series of filtered signal sequences.
5. The FIR filter with multiple parallel inputs and parallel processing according to claim 4, wherein said buffer shift register comprises a plurality of data bits, each data bit for registering a second signal to be processed.
6. The FIR filter with multiple parallel inputs and parallel processing as claimed in claim 5, wherein said filtering module comprises a dot multiplication module and a summation module;
the dot multiplication module comprises a plurality of filter coefficients, and is used for dot-multiplying each third processing signal with the filter coefficients to obtain a plurality of dot-multiplied third processing signals;
and the summation module is used for summing the third processing signals obtained by multiplying all the points to obtain an output signal.
7. The FIR filter with multiple parallel inputs and parallel processing according to claim 6, wherein the number of data bits of said buffer shift register is the same as the number of filter coefficients in said filter module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910167215.5A CN109951173B (en) | 2019-03-06 | 2019-03-06 | FIR filtering method and filter for multi-channel parallel input and parallel processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910167215.5A CN109951173B (en) | 2019-03-06 | 2019-03-06 | FIR filtering method and filter for multi-channel parallel input and parallel processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109951173A CN109951173A (en) | 2019-06-28 |
| CN109951173B true CN109951173B (en) | 2023-03-21 |
Family
ID=67009116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910167215.5A Active CN109951173B (en) | 2019-03-06 | 2019-03-06 | FIR filtering method and filter for multi-channel parallel input and parallel processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109951173B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114063926B (en) * | 2021-11-22 | 2024-03-15 | 上海创远仪器技术股份有限公司 | Method and device for realizing interpolation processing between data based on FPGA hardware, processor and computer readable storage medium thereof |
| CN114584109B (en) * | 2022-03-15 | 2023-03-10 | 苏州赛迈测控技术有限公司 | Method for real-time filtering parallel signals transmitted by high-speed serial interface |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5392230A (en) * | 1992-07-29 | 1995-02-21 | Thomson Consumer Electronics | Fir filter apparatus for multiplexed processing of time division multiplexed signals |
| JPH09116388A (en) * | 1995-10-16 | 1997-05-02 | Sony Corp | Finite length impulse response filter, digital signal processor and digital signal processing method |
| JP2008054175A (en) * | 2006-08-28 | 2008-03-06 | Mitsubishi Electric Corp | Parallelization lookup table system |
| US8725785B1 (en) * | 2004-08-09 | 2014-05-13 | L-3 Communications Corp. | Parallel infinite impulse response filter |
| GB201611064D0 (en) * | 2015-07-21 | 2016-08-10 | Cirrus Logic Int Semiconductor Ltd | Hybrid finite impulse response filter |
| CN106817106A (en) * | 2016-12-21 | 2017-06-09 | 上海华为技术有限公司 | A kind of parallel FIR filtering methods and FIR filter |
| CN107769755A (en) * | 2017-10-24 | 2018-03-06 | 中国科学院电子学研究所 | A kind of design method of parallel FIR decimation filters and parallel FIR decimation filters |
| CN108832908A (en) * | 2018-05-23 | 2018-11-16 | 成都玖锦科技有限公司 | Multipath high-speed filter implementation method based on FPGA |
-
2019
- 2019-03-06 CN CN201910167215.5A patent/CN109951173B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5392230A (en) * | 1992-07-29 | 1995-02-21 | Thomson Consumer Electronics | Fir filter apparatus for multiplexed processing of time division multiplexed signals |
| JPH09116388A (en) * | 1995-10-16 | 1997-05-02 | Sony Corp | Finite length impulse response filter, digital signal processor and digital signal processing method |
| US8725785B1 (en) * | 2004-08-09 | 2014-05-13 | L-3 Communications Corp. | Parallel infinite impulse response filter |
| JP2008054175A (en) * | 2006-08-28 | 2008-03-06 | Mitsubishi Electric Corp | Parallelization lookup table system |
| GB201611064D0 (en) * | 2015-07-21 | 2016-08-10 | Cirrus Logic Int Semiconductor Ltd | Hybrid finite impulse response filter |
| CN106817106A (en) * | 2016-12-21 | 2017-06-09 | 上海华为技术有限公司 | A kind of parallel FIR filtering methods and FIR filter |
| CN107769755A (en) * | 2017-10-24 | 2018-03-06 | 中国科学院电子学研究所 | A kind of design method of parallel FIR decimation filters and parallel FIR decimation filters |
| CN108832908A (en) * | 2018-05-23 | 2018-11-16 | 成都玖锦科技有限公司 | Multipath high-speed filter implementation method based on FPGA |
Non-Patent Citations (2)
| Title |
|---|
| V.S. Rosa ; E. Costa ; S. Bampi.A High Performance Parallel FIR Filters Generation Tool.《Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP"06)》.2006, * |
| 高速并行FIR滤波器的FPGA实现;张维良等;《系统工程与电子技术》;20090815;第1819-1822页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109951173A (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106803750B (en) | Multichannel running water FIR filter | |
| CN109951173B (en) | FIR filtering method and filter for multi-channel parallel input and parallel processing | |
| JP2003179467A (en) | Digital filter having high precision and high efficiency | |
| CN105991137A (en) | Systems and methods of variable fractional rate digital resampling | |
| CN101282322A (en) | Built-in digital filter apparatus for physical layer of wireless intermediate-range sensing network | |
| JP6256348B2 (en) | Fast Fourier transform circuit, fast Fourier transform processing method, and fast Fourier transform processing program | |
| WO2006109240A2 (en) | Fast fourier transform architecture | |
| CN101425794B (en) | Digital filter with fixed coefficient | |
| CN103117730A (en) | Multichannel comb filter and implement method thereof | |
| CN110620566B (en) | FIR filtering system based on combination of random calculation and remainder system | |
| CN1862960B (en) | Fraction double interpolation multi-phase filter and filtering method | |
| CN110677138B (en) | FIR filter based on error-free probability calculation | |
| Ye et al. | A low cost and high speed CSD-based symmetric transpose block FIR implementation | |
| CN109921764A (en) | 4 times of interpolation Integrator-Comb cic filter parallel high-speed algorithms | |
| CN103078606A (en) | Multichannel CIC (Cascaded Integrator Comb) interpolation-filter system and implementation method thereof | |
| CN101072018B (en) | Digital signal frequency-division filter method and system | |
| US20200136865A1 (en) | Data stream processing device with reconfigurable data stream processing resources and data stream processing method | |
| US8977885B1 (en) | Programmable logic device data rate booster for digital signal processing | |
| JP5557339B2 (en) | Decimation filter and decimation processing method | |
| US9954698B1 (en) | Efficient resource sharing in a data stream processing device | |
| JPH0834406B2 (en) | Input weighted transversal filter | |
| JP2003046374A (en) | Digital filter circuit | |
| TWI768504B (en) | Filter circuits and associated signal processing methods | |
| US6101517A (en) | Circuit and method for the multiple use of a digital transversal filter | |
| CN114978210B (en) | Digital channelized receiving device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |