CN109951173A - A kind of the FIR filtering method and filter of multidiameter delay input parallel processing - Google Patents
A kind of the FIR filtering method and filter of multidiameter delay input parallel processing Download PDFInfo
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Abstract
The invention discloses a kind of multidiameter delay input parallel processing FIR filtering method and filters, it is sent into after the road N parallel input data is postponed by packetization delay method in N group caching shift register, after caching shift register is shifted according to parallel shift method, data are sent into the road N parallel filtering module simultaneously in N group shift register again, obtained N number of point is respectively as a point in the filtering data of the road N, it repeats the above steps, until obtaining whole filtering datas.Method provided by the invention improves the frequency range of FPGA processing high speed signal, is able to solve the filtering problem of the present and following high speed and ultra high speed signal in FPGA.
Description
Technical field
The present invention relates to FIR filtering methods, and in particular to a kind of FIR filtering method of multidiameter delay input parallel processing and
Filter.
Background technique
Finite impulse response filter (full name in English: Finite Impulse Response, English abbreviation: FIR) is several
Most basic element in word signal processing system, have linear phase-frequency characteristic, and its unit sample respo be it is time-limited, because
Stable system may be implemented in this FIR filter.Conventional FIR filter can only be more to be adapted to by configuring more set FIR filters
Road antenna data is handled, and be can be only achieved the demand of generating date, but with the continuous increase of antenna scale, is used
The scheme of more set FIR filters can make corresponding hardware spending obviously increase, and cannot meet the filtering demands of low-consumption high-speed again.
Parallel algorithm refers to that data flow is first gone here and there and converted before entering FIR filter, then inside FIR filter
To multichannel data carry out parallel processing, to carried out again after the multiplex arithmetric that will be exported and go here and there conversion after export, in high-speed figure
In field of signal processing, as front-end A/D C acquisition rate is higher and higher, the sample rate from 1Gsps to 40Gsps, such signal
It can not directly be handled in FPGA with series form, it is therefore necessary to consider that the method for parallel input parallel processing realizes high speed
The processing of serial signal.
Existing method proposes a kind of parallel FIR filtering method and filter, devises serial input-parallel processing
FIR filter, and by pre- cumulative reduction hardware spending, but since it requires serial input, it can not be used at high speed signal
In reason.
Summary of the invention
The purpose of the present invention is to provide the FIR filtering methods and filter of a kind of input parallel processing of multidiameter delay, use
Parallel input, which be cannot achieve, to solve parallel FIR filtering method and filter in the prior art causes filtering speed unhappy, imitates
The problems such as rate is not high.
In order to realize above-mentioned task, the invention adopts the following technical scheme:
A kind of FIR filtering method of multidiameter delay input parallel processing, for being filtered to N string input signal sequence,
Wherein a string of input signal sequences include multiple input signals, and N is the integer greater than 1, are executed according to the following steps:
Step 1 after step 1.1-1.6 is performed a plurality of times, obtains multiple output signals:
Step 1.1, simultaneously input it is every string input signal sequence in an input signal, obtain the 1st input signal collection
S1={ x11,x12,…,x1i,…,x1N, wherein the 1st input signal collection includes N number of input signal, x1iFor the 1st input signal
I-th of the input signal concentrated, i ∈ N；
It replicates N-1 and returns the input signal collection, obtain N number of input signal collection altogether:
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
Wherein, SiFor i-th of input signal collection, xiiI-th input signal concentrated for i-th of input signal；
Step 1.2, when i=1,2 ..., N-1 when, to i-th of input signal collection Si={ xi1,xi2,…,xii,…,xiN}
Grouping obtains i-th of first signal collection C to be processedi={ xi1,xi2,…,xiiAnd i-th of postpones signal collection Di={ xii+1,
xii+2,…,xiN}；
As i=N, to n-th input signal collection SN={ xN1,xN2,…,xNi,…,xNNGrouping, obtain n-th first
Signal collection C to be processedN=SNAnd n-th postpones signal collection
Step 1.2 is repeated until obtaining the N number of first signal collection to be processed of this processing and N number of delay of this processing
Signal collection；
Step 1.3, i-th of postpones signal collection for handling i-th of first signal collection to be processed of this processing and last time
Merge, obtains i-th of second signal collection to be processed, when this processing is the 1st processing, each postpones signal of last time processing
Collection is empty set；
Step 1.3 is repeated, until obtaining N number of second signal collection to be processed；
Step 1.4 concentrates all second signals to be processed to carry out parallel each of described second signal to be processed simultaneously
Shifting processing obtains N number of third signal collection to be processed；
Step 1.5, simultaneously by each third signal to be processed concentrate all thirds signal to be processed using filter by the way of
Merge into an output signal；
Step 1.6, the N number of output signal of output；
Step 2 gathers multiple output signals according to the sequence that step 1 executes, and it is filtered to obtain N string
Signal sequence.
Further, the step 1.4, each of described second signal to be processed is concentrated all second wait locate simultaneously
When managing signal progress parallel shift processing, mobile unit is N, obtains N number of third signal collection to be processed.
Further, the step 1.5, each third signal to be processed concentrated into all third signals to be processed simultaneously
An output signal is merged by the way of filtering, is specifically included:
By each third processing signal respectively and after filter factor dot product, the third after obtaining multiple dot products handles signal；
Third processing signal after all dot products is summed, an output signal is obtained.
A kind of FIR filter of multidiameter delay input parallel processing, including input module and output module, it is described
FIR filter further includes PHM packet handling module, signal merging module, caching shift register and filter module；
The input module is used for while inputting an input signal in every string input signal sequence, obtains the 1st
Input signal collection S1={ x11,x12,…,x1i,…,x1N, wherein the 1st input signal collection includes N number of input signal, x1iIt is the 1st
I-th of input signal that a input signal is concentrated, i ∈ N；
It is also used to replicate N-1 and returns the input signal collection, obtain N number of input signal collection altogether:
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
Wherein, SiFor i-th of input signal collection, xiiI-th input signal concentrated for i-th of input signal；
The PHM packet handling module for judge when i=1,2 ..., N-1 when, to i-th of input signal collection Si={ xi1,
xi2,…,xii,…,xiNGrouping, obtain i-th of first signal collection C to be processedi={ xi1,xi2,…,xiiAnd i-th of delay
Signal collection Di={ xii+1,xii+2,…,xiN}；
As i=N, to n-th input signal collection SN={ xN1,xN2,…,xNi,…,xNNGrouping, obtain n-th first
Signal collection C to be processedN=SNAnd n-th postpones signal collection
Obtain the N number of first signal collection to be processed of this processing and N number of postpones signal collection of this processing；
The signal merging module is used for the of i-th first signal collection to be processed of this processing and last time processing
I postpones signal collection merges, and obtains i-th of second signal collection to be processed, when this processing is the 1st processing, last time processing
Each postpones signal collection be empty set；
Obtain the N number of second signal collection to be processed；
The caching shift register for simultaneously to each of described second signal to be processed concentrate all second to
It handles signal and carries out parallel shift processing, obtain N number of third signal collection to be processed；
The filter module is for simultaneously adopting all thirds signal to be processed that each third signal to be processed is concentrated
An output signal is merged into the mode of filtering；
The output module is used to export N number of output signal；
It is also used to gather the output signal, obtains the filtered signal sequence of N string.
It further, include multiple data bit in the caching shift register, each data bit is for depositing one
Second signal to be processed.
Further, the filter module includes dot product module and summation module；
It include multiple filter factors in the dot product module, the dot product module is used to each third handling signal
Respectively and after filter factor dot product, the third after obtaining multiple dot products handles signal；
The summation module is used to sum the third processing signal after all dot products, obtains an output letter
Number.
Further, the number of the data bit of the caching shift register and filter factor in the filter module
Number is identical.
The present invention has following technical characterstic compared with prior art:
1, the FIR filtering method and filter of a kind of multidiameter delay input parallel processing provided by the invention pass through to signal
It is grouped delay, realizes the function of signal parallel input, and realizes high speed signal from the full parellel for being input to output
Reason, improves the processing speed of signal；
2, traditional serial filtering algorithm a cycle can only handle a data, a kind of multidiameter delay provided by the invention
For the FIR filtering method and filter for inputting parallel processing by the parallel input processing output in the road N, operation clock is output speed
1/N can realize the signal processing of N times of rate under the driving of the clock of low speed.
Detailed description of the invention
Fig. 1 is the FIR filter structure schematic diagram provided in one embodiment of the present of invention；
Fig. 2 is the caching shift register parallel shift schematic diagram provided in one embodiment of the present of invention.
Specific embodiment
FIR filter: there are limit for length's unit impulse response filter, also known as non-recursive type filter, be at digital signal
Most basic element in reason system, it can be while guaranteeing any amplitude-frequency characteristic with stringent linear phase-frequency characteristic, together
When its unit sample respo be time-limited.
Parallel shift processing: data input in a parallel fashion, and each time pulse data integrally to the left or move right more
It is exported after a data bit, generally a data bit.
Cache shift register: data are input in the device in a manner of concurrently or sequentially, then each time pulse
It successively to the left or moves right after a bit and saves, exported in output end, can be used to deposit code, can also be used to
Realize serial-Parallel transformation, the operation of numerical value and the processing of data of data.
Filter factor: being the index for expressing channel filtering frequent subsequences both sides steep, 6dB band of generally winning the confidence
For the ratio between wide and 60dB bandwidth numerical value closer to 1, the characteristic of filtering is more precipitous, and selectivity is more ideal.
FIR filter in the prior art is generally basede on convolutional coding structure realization, the FIR filter realized based on convolutional coding structure
Structure is simple, easy to accomplish, but problem is that computing relay is too big, for example, length be M input signal sequence, each period according to
One value of secondary input needs altogether M period to obtain the output that length is M point into FIR filter, but as number is gone together
The data throughout of system is increasing, and the processing speed of FIR filter is increasingly becoming bottleneck.
Embodiment one
A kind of FIR filtering method of multidiameter delay input parallel processing is disclosed in the present embodiment, is inputted for going here and there to N
Signal sequence is filtered, wherein a string of input signal sequences include multiple input signals, N is the integer greater than 1, and feature exists
In, be performed a plurality of times step 1.1-1.6 obtain N string output signal sequence.
The present invention is handled N string input signal to improve the processing speed of signal simultaneously, but in a cycle
It is interior to handle N number of signal, therefore N string input signal sequence is successively filtered by the sequence of signal in sequence.
The present invention executes according to the following steps:
Step 1 after step 1.1-1.6 is performed a plurality of times, obtains multiple output signals:
Step 1.1, simultaneously input it is every string input signal sequence in an input signal, obtain the 1st input signal collection
S1={ x11,x12,…,x1i,…,x1N, wherein the 1st input signal collection includes N number of input signal, x1iFor the 1st input signal
I-th of the input signal concentrated, i ∈ N；
It replicates N-1 and returns the input signal collection, obtain N number of input signal collection altogether:
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
Wherein, SiFor i-th of input signal collection, xiiI-th input signal concentrated for i-th of input signal；
In the present embodiment, N string input signal sequence is handled, includes multiple defeated in every string input signal sequence
Enter signal；In this step, while an input signal in every string input signal sequence is inputted, obtains input signal collection, example
Such as in a cycle, the input signal of acquisition integrates as S1={ x11,x12,…,x1i,…,x1N, it altogether include that N number of input is believed
Number；
In this step, it is also necessary to n times be replicated to input signal collection, input signal is integrated as S1={ x11,x12,…,
x1i,…,x1NWhen, input serial number collection S is replicated N-1 times, N input signal collection, the input that each input signal is concentrated are obtained
Signal is identical.
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
That is x11=x21=xi1=xN1, x12=x22=xi2=xN2, x1i=x2i=xii=xNi, x1N=x2N=xiN=xNN。
Step 1.2, when i=1,2 ..., N-1 when, to i-th of input signal collection Si={ xi1,xi2,…,xii,…,xiN}
Grouping obtains i-th of first signal collection C to be processedi={ xi1,xi2,…,xiiAnd i-th of postpones signal collection Di={ xii+1,
xii+2,…,xiN}；
As i=N, to n-th input signal collection SN={ xN1,xN2,…,xNi,…,xNNGrouping, obtain n-th first
Signal collection C to be processedN=SNAnd n-th postpones signal collection
Step 1.2 is repeated until obtaining the N number of first signal collection to be processed of this processing and N number of delay of this processing
Signal collection；
In this step, in order to improve the speed of signal processing, all signals that input signal is concentrated are grouped place
Reason, that is to say, that the N number of input signal concentrated for N number of input signal is grouped processing.
For example, in the 1st execution step 1.1- step 1.6, to all letters of N number of input signal concentration as follows
It number is grouped, specifically includes:
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
For the 1st input signal collection S1={ x11,x12,…,x1i,…,x1N, preceding 1 input signal therein is made
For the first signal to be processed of this processing, the postpones signal that other remaining signals are handled as this, then first
Input signal collection is divided into first the first signal collection C to be processed1={ x11And first postpones signal collection D1={ x12,…,
x1i,…,x1N}；
For the 2nd input signal collection S2={ x21,x22,…,x2i,…,x2N, preceding 2 input signals therein are made
For the first signal to be processed of this processing, the postpones signal that other remaining signals are handled as this, then second
Input signal collection is divided into second the first signal collection C to be processed2={ x21,x22And second postpones signal collection D2=
{x23,…,x2N}；
According to above sequence, for n-th input signal collection SN={ xN1,xN2,…,xNi,…,xNN, it will be therein
The first signal to be processed that top n input signal is handled as this, the delay that other remaining signals are handled as this
Signal, then n-th input signal collection is divided into the signal collection C to be processed of n-th firstN=SNAnd n-th postpones signal collection
In the 2nd execution step 1.1 to step 1.6, N number of input signal collection is respectively as follows:
S1={ y11,y12,…,y1i,…,y1N}
S2={ y21,y22,…,y2i,…,y2N}
…
Si={ yi1,yi2,…,yii,…,yiN}
…
SN={ yN1,yN2,…,yNi,…,yNN}
The first signal collection to be processed of above multiple 2nd processing and the postpones signal of the 2nd processing can equally be obtained
Collection, is respectively as follows:
First the first signal collection to be processed of the 2nd processingAnd first postpones signal collection
2nd the first signal collection to be processed of the 2nd processingAnd the 2nd postpones signal collection
The signal collection to be processed of n-th first of 2nd processingAnd n-th is prolonged
Slow signal collection
Step 1.3, i-th of postpones signal collection for handling i-th of first signal collection to be processed of this processing and last time
Merge, obtains i-th of second signal collection to be processed, when this processing is the 1st processing, each postpones signal of last time processing
Collection is empty set；
Step 1.3 is repeated, until obtaining N number of second signal collection to be processed；
In the present embodiment, when the 1st execution step 1.1- step 1.6, by step 1.2, obtain N number of first to
Signal collection and N number of postpones signal collection are handled, then when obtaining N number of second signal collection to be processed, directly by N number of first wait locate
Signal collection is managed as the N number of second signal collection to be processed.
When the 2nd execution step 1.1- step 1.6, by step 1.2, obtain the N number of first signal collection to be processed with
And N number of postpones signal collection, the signal collection to be processed of N number of first at this time obtain when being the 2nd processing, when by the 2nd processing
The the N number of first signal collection to be processed obtained is merged with the N number of postpones signal collection obtained when the 1st processing, such as:
The 1st the first signal collection to be processed obtained when by the 2nd processingIt is obtained when being handled with the 1st time
1st postpones signal collection D1={ x21,x31,…,xN1Merge, obtain the 1st the second signal collection { y to be processed12,x21,
x31,…,xN1}；
The 2nd the first signal collection to be processed obtained when by the 2nd processingIt is obtained when with the 1st processing
The 2nd postpones signal collection D obtained2={ x31,…,xN1Merge, obtain the 2nd the second signal collection { y to be processed12,y22,x31,…,
xN1}。
Step 4 concentrates all second signals to be processed to be moved parallel each of described second signal to be processed simultaneously
Position processing, obtains N number of third signal collection to be processed；
In this step, when carrying out parallel shift processing to signal, the common method of the prior art is that each signal is same
When shift to right or left 1.
In the present invention, in order to improve the efficiency of processing, processing method as one preferred is the step 1.4, same
When concentrating all second signals to be processed to carry out parallel shift processing each of described second signal to be processed, mobile list
Position is N, obtains N number of third signal collection to be processed；
In the present embodiment, when carrying out N parallel shift processing, in the original state that third signal to be processed is concentrated
Each signal is random signal.
Parallel shift processing is further explained below, wherein the original state such as table of third signal collection to be processed
Shown in 1, it is 12 that third signal to be processed, which concentrates the number of signal, and input signal number is 3.
1 third of table signal collection original state table to be processed
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| A | B | C | D | E | F | G | H | I | J | K | L |
For need to carry out parallel shift processing the second signal collection to be processed be { 1 }, i.e., wherein have one second to
It handles signal and the signal D on the position D3 is displaced to D6 then the signal A on the position D0 is displaced to D3 when being shifted
Position, is displaced to D9 for the signal G on the position D6, and the signal J on the position D9 is overflowed；The letter that the second signal to be processed is concentrated at this time
Number 1 is placed on D0, obtains third signal collection to be processed at this time and is shown in Table 2.
2 third of table signal collection state table to be processed
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| 1 | B | C | A | E | F | D | H | I | G | K | L |
It is { 1,2 } for the second signal collection to be processed for needing to carry out parallel shift processing, i.e., wherein there are two second for tool
Signal to be processed, then when being shifted, in table 1 by D0, the position D1 signal A and signal B be displaced to D3 and D4
Position, is displaced to D6 and D7 for signal D, F on D3 and the position D4, and signal G, H on D6 and the position D7 are displaced to D9
With D10, by the signal J and signal K spilling on D9 and the position D10；The signal 1 and letter that the second signal to be processed is concentrated at this time
Numbers 2 are placed on D0 and D1, obtain third signal collection to be processed at this time and are shown in Table 3.
3 third of table signal collection state table to be processed
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| 1 | 2 | C | A | B | F | D | E | I | G | H | L |
It is { 1,2,3 } similarly, for the second signal collection to be processed for needing to carry out parallel shift processing, i.e., wherein has
There are three the second signal to be processed, the third of acquisition signal to be processed is shown in Table 4.
4 third of table signal collection original state table to be processed
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | D10 | D11 |
| 1 | 2 | 3 | A | B | C | D | E | F | G | H | I |
Therefore, the road N input data is stored in top n data bit by parallel shift facture, and by sequence in next period
It number is stored in for data in 1+k × N~N+k × N data bit in the data bit of serial number 1+ (1+k) × N~N+ (k+1) × N,
Middle k=0,1 ..., Y/N, wherein Y is the sum of data bit or the sum of third signal concentration signal to be processed.
Step 1.5, all thirds signal to be processed for simultaneously concentrating each third signal to be processed are using the side filtered
Formula merges into an output signal；
In this step, all thirds signal to be processed that third signal to be processed is concentrated is merged into an output letter
Number, combined method specifically includes:
By each third processing signal respectively and after filter factor dot product, the third after obtaining multiple dot products handles signal；
Third processing signal after all dot products is summed, an output signal is obtained.
In the present embodiment, if third signal collection to be processed is { t1,t2,t3,…,tN, filtering coefficient sets are { k1,k2,
k3,…,kN, then output signal is
Step 1.6, the N number of output signal of output.
Step 2 gathers multiple output signals according to the sequence that step 1 executes, and obtains the filtered signal of N string
Sequence.
Multiple output signals of acquisition are merged according to the sequence that step 1.1-1.6 is performed a plurality of times, obtain output letter
Number sequence.
Method provided by the invention can be realized in FPGA, SCM Based system, especially in FPGA, due to
FPGA highest operating rate C is mainly limited by manufacturing process, and it is N*C that output speed, which may be implemented, in the method for parallel processing of this patent
Filtering processing, conventional method can only realize output speed be C filtering processing, improve FPGA processing high speed signal frequency
Range.
Embodiment two
In the present embodiment, 3 tunnels are inputted parallel for 3 road parallel process models, are done to method of the invention and are further retouched
It states.
3 string input signal sequences are filtered, wherein a string of input signal sequences include multiple input signals.
In the present embodiment, 3 string input signal sequences are respectively as follows:
Y1={ x11,x12,x13}
Y2={ x21,x22,x23}
Y3={ x31,x32,x33}
It include 3 input signals in every string input signal sequence, therefore 3 execution step 1.1-1.6 obtain 3 string outputs
Signal sequence:
Step 1.1, simultaneously input it is every string input signal sequence in an input signal, obtain input signal collection, it is described
Input signal collection include 3 input signals；
Input signal collection described in duplication 2 times, obtains 3 input signal collection altogether；
In the present embodiment, when the 1st execution step 1.1, input signal integrates as S1={ x11,x21,x31, it holds for the 2nd time
When row step 1.1, input signal integrates as S2={ x12,x22,x32, when the 3rd execution step 1.1, input signal integrates as S3=
{x13,x23,x33}。
When the 1st execution step 1.1,2 input signal collection are replicated, obtaining 3 input signal collection is respectively
When the 2nd execution step 1.1,2 input signal collection are replicated, obtaining 3 input signal collection is respectively
Similarly, the 3rd execution step 1.1 obtains
Step 2, all input signals for simultaneously concentrating each input signal are divided into the first signal collection to be processed and prolong
Slow signal collection obtains the N number of first signal collection to be processed of this processing and N number of postpones signal collection of this processing；
In the present embodiment, when the 1st execution step 1.2, by 3 input signal collectionMiddle institute
Some input signals are grouped, wherein being divided into first the first signal collection to be processed for the 1st input signal collectionAnd first postpones signal collection2nd first is divided into for the 2nd input signal collection
Signal collection to be processedAnd the 2nd postpones signal collectionFor the 3rd input signal collection point
For the 3rd the first signal collection to be processedAnd the 3rd postpones signal collection
When the 2nd execution step 1.2, by 3 input signal collectionIn all input signal into
Row grouping, wherein being divided into first the first signal collection to be processed for the 1st input signal collectionAnd first prolonged
Slow signal collection2nd the first signal collection to be processed is divided into for the 2nd input signal collectionAnd the 2nd postpones signal collection3rd first is divided into for the 3rd input signal collection
Signal collection to be processedAnd the 3rd postpones signal collection
When the 3rd execution step 1.2, by 3 input signal collectionIn all input signal into
Row grouping, wherein being divided into first the first signal collection to be processed for the 1st input signal collectionAnd first prolonged
Slow signal collection2nd the first signal collection to be processed is divided into for the 2nd input signal collectionAnd the 2nd postpones signal collection3rd first is divided into for the 3rd input signal collection
Signal collection to be processedAnd the 3rd postpones signal collection
Step 1.3, each postpones signal for simultaneously handling the first signal collection to be processed of each of this processing and last time
Collection merges, and obtains 3 the second signal collection to be processed；
When in the present embodiment, for the 1st execution step 1.3, first the second signal collection { x to be processed11, the 2nd
Second signal collection { x to be processed11, x21And the 3rd the second signal collection { x to be processed11, x21,x31}。
When for the 2nd execution step 1.3, first the first signal collection to be processed of this processingAnd
1st first postpones signal collectionMerge, obtains the 1st the 2nd signal collection { x to be processed12,x21,x31}；
For the 2nd the first signal collection to be processed of this processingAnd the 1st the 2nd postpones signal collectionMerge, obtains the 2nd the 2nd signal collection { x to be processed12, x22,x31}；For this processing the 3rd first to
Handle signal collectionAnd the 1st the 3rd postpones signal collectionMerge, obtains the 3rd
2nd signal collection { x to be processed12, x22,x32}。
When for the 3rd execution step 1.3, first the first signal collection to be processed of this processingAnd
2nd first postpones signal collectionMerge, obtains the 1st the second signal collection { x to be processed13,x22,
x32}；For the 2nd the first signal collection to be processed of this processingAnd the 2nd the 2nd postpones signal
CollectionMerge, obtains the 2nd the second signal collection { x to be processed32, x13, x23}；For the 3rd first of this processing
Signal collection to be processedAnd the 1st the 3rd postpones signal collectionMerge, obtains the 3rd
A second signal collection { x to be processed13, x23,x33}。
Step 1.4 concentrates all second signals to be processed to carry out parallel each of described second signal to be processed simultaneously
Shifting processing obtains N number of third signal collection to be processed；
When in the present embodiment, for the 1st execution step 1.4, to first the second signal collection { x to be processed11, the 2nd
A second signal collection { x to be processed11, x21And the 3rd the second signal collection { x to be processed11, x21,x31Carry out at parallel shift
Reason, acquisition the results are shown in Table 5.
5 third of table signal collection state table to be processed
When in the present embodiment, for the 2nd execution step 1.4, to first the second signal collection { x to be processed12,x21,
x31, the 2nd the second signal collection { x to be processed12, x22,x31And the 3rd the second signal collection { x to be processed12, x22,x32Carry out
Parallel shift processing, acquisition the results are shown in Table 6.
6 third of table signal collection state table to be processed
In the present embodiment, for the 3rd execution step 1.4, the 1st the second signal collection { x to be processed13,x22,x32}、
2nd the second signal collection { x to be processed32, x13, x23And the 3rd the second signal collection { x to be processed13, x23,x33Carry out parallel
Shifting processing, acquisition the results are shown in Table 7.
7 third of table signal collection state table to be processed
Step 1.5, all thirds signal to be processed for simultaneously concentrating each third signal to be processed are using the side filtered
Formula merges into an output signal；
In the present embodiment, the 3 thirds signal collection to be processed obtained for the 1st time merges, and obtains 3 output letters
Number；
The 3 thirds signal collection to be processed obtained for the 2nd time merges, and obtains 3 output signals；
The 3 thirds signal collection to be processed obtained for the 3rd time merges, and obtains 3 output signals；
Step 1.6, the N number of output signal of output；
When the 1st execution step 1.6,3 output signals { X1, Y1, Z1 } are obtained；
When the 2nd execution step 1.6,3 output signals { X2, Y2, Z2 } are obtained；
When the 3rd execution step 1.6,3 output signals { X3, Y3, Z3 } are obtained；
Step 2 gathers multiple output signals, obtains the filtered signal sequence of N string.
In the present embodiment, X1, X2 and X3 are merged by the output signal of 3 acquisitions according to merging, is obtained
First string output signal sequence, Y1, Y2 and Y3 are merged, and obtain the second string output signal sequence, Z1, Z2 and Z3 are closed
And third string output signal sequence is obtained, 3 string output signal sequences are obtained altogether.
Embodiment three
In the present embodiment as shown in Figure 1, disclosing a kind of FIR filter of multidiameter delay input parallel processing, including
Input module and output module, the FIR filter further include PHM packet handling module, signal merging module, caching displacement
Register and filter module；
The input module is used for while inputting an input signal in every string input signal sequence, obtains the 1st
Input signal collection S1={ x11,x12,…,x1i,…,x1N, wherein the 1st input signal collection includes N number of input signal, x1iIt is the 1st
I-th of input signal that a input signal is concentrated, i ∈ N；
It is also used to replicate N-1 and returns the input signal collection, obtain N number of input signal collection altogether:
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
Wherein, SiFor i-th of input signal collection, xiiI-th input signal concentrated for i-th of input signal；
The PHM packet handling module for judge when i=1,2 ..., N-1 when, to i-th of input signal collection Si={ xi1,
xi2,…,xii,…,xiNGrouping, obtain i-th of first signal collection C to be processedi={ xi1,xi2,…,xiiAnd i-th of delay
Signal collection Di={ xii+1,xii+2,…,xiN}；
As i=N, to n-th input signal collection SN={ xN1,xN2,…,xNi,…,xNNGrouping, obtain n-th first
Signal collection C to be processedN=SNAnd n-th postpones signal collection
Obtain the N number of first signal collection to be processed of this processing and N number of postpones signal collection of this processing；
In the present embodiment, PHM packet handling module posts different displacements according to each caching shift register group serial number
N number of input of storage group is postponed respectively, will be in the road the N input that cache shift register to i-th of caching shift LD group
Input data delay one of the serial number greater than i inputs number as the road N for caching shift register simultaneously with the input of the preceding road i again after clapping
According to.
The signal merging module is used for the of i-th first signal collection to be processed of this processing and last time processing
I postpones signal collection merges, and obtains i-th of second signal collection to be processed, when this processing is the 1st processing, last time processing
Each postpones signal collection be empty set；
Obtain the N number of second signal collection to be processed；
The caching shift register for simultaneously to each of described second signal to be processed concentrate all second to
It handles signal and carries out parallel shift processing, obtain N number of third signal collection to be processed；
In the present embodiment, caching shift register has N number of input port, and caching in shift register has Y register,
It is identical as filter coefficient number, and have Y output port.
In the present embodiment, as shown in Fig. 2, the parallel shift operation of caching shift register is to deposit the road N input data
Enter in top n register, signal in serial number 1+k × N~N+k × N register is stored in serial number 1+ in next period
In (1+k) × N~N+ (k+1) × N register, wherein k=0,1 ..., Y/N.
Such as caching shift register the 1st, 2,3 tunnels input be stored respectively in register D0, register D1, register D2
In, each period is performed simultaneously following operation all in accordance with parallel shift method, and the data in register D0 are stored in register D3, are posted
The data in data deposit register D6, register D6 in storage D3 are stored in register D9, the data deposit in register D1
The data in data deposit register D7, register D7 in register D4, register D4 are stored in register D10, register D2
In data deposit register D5, the data in data deposit register D8, register D8 in register D5 be stored in register
D11。
The filter module is for simultaneously adopting all thirds signal to be processed that each third signal to be processed is concentrated
An output signal is merged into the mode of filtering；
The output module is used to export N number of output signal；
It is also used to gather the output signal, obtains the filtered signal sequence of N string.
It optionally, include multiple data bit in the caching shift register, each data bit is for depositing one the
Two signals to be processed.
Optionally, the filter module includes dot product module and summation module；
It include multiple filter factors in the dot product module, the dot product module is used to each third handling signal
Respectively and after filter factor dot product, the third after obtaining multiple dot products handles signal；
The summation module is used to sum the third processing signal after all dot products, obtains an output letter
Number.
In the present embodiment, Y data cached and Y coefficient points of filter in shift register are cached in filter module
Multiply and sums.
Optionally, the number of the data bit of the caching shift register and of filter factor in the filter module
Number is identical.
In the present embodiment, 12 register datas cached in shift register are all output to filter by each period
Wave module, stores 12 filter taps coefficients in filter module, 12 filter taps coefficients and 12 register datas phase one by one
Multiply, and sum, by the result output as parallel filtering of summing.3 caching shift registers are identical in Fig. 1,3 filters
Wave module is also identical.
Claims (7)
1. a kind of FIR filtering method of multidiameter delay input parallel processing, for being filtered to N string input signal sequence,
In a string of input signal sequences include multiple input signals, N is the integer greater than 1, which is characterized in that is held according to the following steps
Row:
Step 1 after step 1.1-1.6 is performed a plurality of times, obtains multiple output signals:
Step 1.1, simultaneously input it is every string input signal sequence in an input signal, obtain the 1st input signal collection S1=
{x11,x12,…,x1i,…,x1N, wherein the 1st input signal collection includes N number of input signal, x1iFor the 1st input signal collection
In i-th of input signal, i ∈ N；
It replicates N-1 and returns the input signal collection, obtain N number of input signal collection altogether:
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
Wherein, SiFor i-th of input signal collection, xiiI-th of the input signal concentrated for i-th of input signal；
Step 1.2, when i=1,2 ..., N-1 when, to i-th of input signal collection Si={ xi1,xi2,…,xii,…,xiNGrouping,
Obtain i-th of first signal collection C to be processedi={ xi1,xi2,…,xiiAnd i-th of postpones signal collection Di={ xii+1,
xii+2,…,xiN}；
As i=N, to n-th input signal collection SN={ xN1,xN2,…,xNi,…,xNNGrouping, n-th first is obtained wait locate
Manage signal collection CN=SNAnd n-th postpones signal collection
Step 1.2 is repeated until obtaining the N number of first signal collection to be processed of this processing and N number of postpones signal of this processing
Collection；
Step 1.3 merges this i-th of first signal collection to be processed handled with i-th of postpones signal collection that last time is handled,
I-th of second signal collection to be processed are obtained, when this processing is the 1st processing, last time each postpones signal collection of processing is equal
For empty set；
Step 1.3 is repeated, until obtaining N number of second signal collection to be processed；
Step 1.4 concentrates all second signals to be processed to carry out parallel shift each of described second signal to be processed simultaneously
Processing, obtains N number of third signal collection to be processed；
Step 1.5, simultaneously by each third signal to be processed concentrate all thirds signal to be processed using filter by the way of merge
For an output signal；
Step 1.6, the N number of output signal of output；
Step 2 gathers multiple output signals according to the sequence that step 1 executes, and obtains the filtered signal of N string
Sequence.
2. the FIR filtering method of multidiameter delay input parallel processing as described in claim 1, which is characterized in that the step
Rapid 1.4, when concentrating all second signals to be processed to carry out parallel shift processing each of described second signal to be processed simultaneously,
Mobile unit is N, obtains N number of third signal collection to be processed.
3. the FIR filtering method of multidiameter delay input parallel processing as claimed in claim 2, which is characterized in that the step
Rapid 1.5, all thirds signal to be processed is concentrated to merge into one by the way of filtering each third signal to be processed simultaneously
Output signal specifically includes:
By each third processing signal respectively and after filter factor dot product, the third after obtaining multiple dot products handles signal；
Third processing signal after all dot products is summed, an output signal is obtained.
4. a kind of FIR filter of multidiameter delay input parallel processing, including input module and output module, feature exist
In the FIR filter further includes PHM packet handling module, signal merging module, caching shift register and filter module；
The input module is used for while inputting an input signal in every string input signal sequence, obtains the 1st input
Signal collection S1={ x11,x12,…,x1i,…,x1N, wherein the 1st input signal collection includes N number of input signal, x1iIt is defeated for the 1st
Enter i-th of input signal of signal concentration, i ∈ N；
It is also used to replicate N-1 and returns the input signal collection, obtain N number of input signal collection altogether:
S1={ x11,x12,…,x1i,…,x1N}
S2={ x21,x22,…,x2i,…,x2N}
…
Si={ xi1,xi2,…,xii,…,xiN}
…
SN={ xN1,xN2,…,xNi,…,xNN}
Wherein, SiFor i-th of input signal collection, xiiI-th of the input signal concentrated for i-th of input signal；
The PHM packet handling module for judge when i=1,2 ..., N-1 when, to i-th of input signal collection Si={ xi1,
xi2,…,xii,…,xiNGrouping, obtain i-th of first signal collection C to be processedi={ xi1,xi2,…,xiiAnd i-th of delay
Signal collection Di={ xii+1,xii+2,…,xiN}；
As i=N, to n-th input signal collection SN={ xN1,xN2,…,xNi,…,xNNGrouping, n-th first is obtained wait locate
Manage signal collection CN=SNAnd n-th postpones signal collection
Obtain the N number of first signal collection to be processed of this processing and N number of postpones signal collection of this processing；
The signal merging module is used for i-th by i-th of first signal collection to be processed of this processing and last time processing
Postpones signal collection merges, and obtains i-th of second signal collection to be processed, and when this processing is the 1st processing, last time is handled every
A postpones signal collection is empty set；
Obtain the N number of second signal collection to be processed；
The caching shift register is for be processed to each of described second signal concentration all second to be processed simultaneously
Signal carries out parallel shift processing, obtains N number of third signal collection to be processed；
All thirds to be processed signal of the filter module for simultaneously concentrating each third signal to be processed is using filter
The mode of wave merges into an output signal；
The output module is used to export N number of output signal；
It is also used to gather the output signal, obtains the filtered signal sequence of N string.
5. the FIR filter of multidiameter delay input parallel processing as claimed in claim 4, which is characterized in that the caching
It include multiple data bit in shift register, each data bit is for depositing second signal to be processed.
6. the FIR filter of multidiameter delay input parallel processing as claimed in claim 5, which is characterized in that the filtering
Module includes dot product module and summation module；
It include multiple filter factors in the dot product module, the dot product module is used for each third processing signal difference
After filter factor dot product, the third after obtaining multiple dot products handles signal；
The summation module is used to sum the third processing signal after all dot products, obtains an output signal.
7. the FIR filter of multidiameter delay input parallel processing as claimed in claim 6, which is characterized in that the caching
The number of the data bit of shift register is identical as the number of filter factor in the filter module.
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