CN101360087B - Low-complexity implementing method and apparatus for base-band forming SRRC digital filter - Google Patents

Abstract

The invention relates to a device and a method of realizing low complexity of the base band forming SRRC digital filter. The device comprises the following: a double channel reuse tap delay line unit delays a double channel composite input signal to obtain an input vector x; an order inverting unit inverts the order of the input vector x; an input strobing unit time-sharing strobes the input vector x and an order inverted vector x`; a number of M weighted sum units reuse in time division a weighted sum arithmetic device of the x and a half coefficient hia of a sub-filter, and the x` and the half coefficient hia of the sub-filter; after a summation delaying unit completes setting delaying of the output of the x`. hia operation, the summation delaying unit sums with the output of the x. hiaoperation which is synchronous with the x`. hia operation; and an adapter unit time-sharing strobes the filter operation result of each sub-filter to obtain a double channel forming filter result of the SRRC digital filter. The device retrenches the length of the tap delay line as 1/(2M) of the original length, so the hardware resources needed by the base band forming SRRC digital filter to realize low complexity are remarkably reduced, the complexity is lowered, the filter operation can work in lower frequency, and the aim that I/Q double channel reuse the same filter device is realized.

Description

The low complex degree implement device and the method for base-band forming SRRC digital filter

Technical field

The invention belongs to digital signal processing technique field, relate to the realization of digital filter, relate in particular to the low complex degree implement device and the method for base-band forming SRRC digital filter.

Background technology

The baseband postprocessing part of digital communication system transmitting terminal need be carried out the time domain shaping filter usually.According to the optimum detection theory, the filter of transmitting-receiving two-end is answered conjugate impedance match, and the system function of the matched filter of therefore make a start forming filter and its receiving end should be designed to satisfy the undistorted criterion of Nyquist, i.e. H _T(f) .H _R(f)=H (f), wherein, H _T(f) be the frequency response of transmitting terminal forming filter, H _R(f) be the frequency response of receiving terminal matched filter, H (f) is for satisfying the system function of the undistorted criterion of sampled point, as the raised cosine roll off filter.Correspondingly, make a start forming filter and receiving end matched filter select usually square root raised cosine (Square RootRaised Cosine, SRRC) filter, promptly $H_T\left(f\right)=H_R\left(f\right)=\sqrt{H\left(f\right)}=H_{\mathrm{srrc}}\left(f\right).$ H _Srrc(f) be the frequency response of SRRC filter, be expressed as follows:

$H_{\mathrm{srrc}}\left(f\right)=\left\{\begin{array}{cc}1,& 0\&le;\left|f\right|\&le;\frac{1-\mathrm{\&alpha;}}{2\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="H2008102225146E00012.png,H2008102225146E00021.png"\; state="\{\{state\}\}">T</figure-callout>}}\\ \sqrt{\frac{1}{2}[1+\cos \left[\frac{\mathrm{\&pi;}\left(2T\right|f|-1+\mathrm{\&alpha;})}{2\mathrm{\&alpha;}}\right]]},& \frac{1-\mathrm{\&alpha;}}{2T}\&le;\left|f\right|\&le;\frac{1+\mathrm{\&alpha;}}{2\mathrm{<figure-callout\; id="0"\; label="T"\; filenames="H2008102225146E00021.png"\; state="\{\{state\}\}">T</figure-callout>}}\\ 0,& \left|f\right|\&GreaterEqual;\frac{1+\mathrm{\&alpha;}}{2T}\end{array}\right.$

Its time domain impulse response is expressed as follows:

$h\left(t\right)=\frac{(4\mathrm{\&alpha;t}/T)\cos [\mathrm{\&pi;}(1+\mathrm{\&alpha;})t/T]+\sin [\mathrm{\&pi;}(1-\mathrm{\&alpha;})t/T]}{(\mathrm{\&pi;t}/T)[1-{(4\mathrm{\&alpha;t}/T)}^2]}$

Wherein α is a rolloff-factor, 0≤α≤1, and T is a signal sampling period.Under sampling period T, SRRC filter discrete system impulse response is expressed as h _I[n]=h (n _T).h _I[n] is the infinite impulse response of system, and (Finite Impulse Response, FIR) filter is approximate, adopts the window function method to h in the design usually for available finite impulse response _I[n] blocks, and the finite impulse response after blocking is h[n]=h _I[n] .w[n], w[n wherein] be window function.Square root raised cosine Finite Impulse Response filter (hereinafter to be referred as the SRRC digital filter) coefficient is by the impulse response h[n of discrete system] describe.

In digital communication system, adopt the SRRC filter carry out base band shaping filtering effectively the inhibition zone external leakage, reduce interference and inhibition intersymbol interference (ISI) to the adjacent band, can obtain emission spectrum preferably at transmitting terminal, and guarantee the performance of modulation.In China Digital TV terrestrial broadcasting transmission national standard (GB20600-2006 is called for short DTMB), it is that 0.05 SRRC filter carries out base-band signal spectrum and is shaped that the regulation baseband postprocessing adopts rolloff-factor α.

Rolloff-factor is very little, means that the transition band of SRRC filter is very narrow, and the availability of frequency spectrum is very high, but filter order is had high requirements, and for hardware is realized, has directly caused very high complexity.The SRRC digital filter in the DTMB GB transmitter for example, its exponent number is usually designed to hundreds of rank even higher, when so the SRRC digital filter of high-order was realized in various programmable logic devices, digital signal processor spare or application-specific integrated circuit (ASIC), the optimization that is embodied as purpose with low complex degree was exactly a very real problem.

The base-band forming SRRC digital filter that is used for baseband postprocessing is actually an interpolation filter, before filtering, at first need input signal is carried out the doubly interpolation (Interpolation of (M is a positive integer) of M, or be called up-sampling, and Upsampling), M=f/f _sBe interpolation factor, f wherein _sBe the sample frequency (being character rate) of input signal, f=Mf _sBe the sample frequency of SRRC digital filter, get M=2 or M=4 usually.The conventional structure of base-band forming SRRC digital filter as shown in Figure 1, sample frequency is f _sInput signal x[n] through M times of interpolation, obtaining sample frequency is the M sampling sequence s[n of f], s[n] behind SRRC digital filter shaping filter, obtain exporting y[n] as follows:

$y\left[n\right]=s\left[n\right]*h\left[n\right]=\underset{m=0}{\overset{N}{\mathrm{\&Sigma;}}}s[n-m].h\left[m\right]$

Wherein N and h[n] be respectively the exponent number and the coefficient of SRRC digital filter.

In the modulated terminal of digital communication system, the symbol that the information source input signal obtains after mapping and modulation generally comprises I, Q two paths of data, and two-way is parallel, corresponds respectively to real part and imaginary signals that symbol-modulated produces.For the baseband postprocessing part, parallel input of actual needs I, Q two-way and line output, because the SRRC digital filter is the real coefficient filter, so two-way finishes that base band shaping filtering uses is identical device.

The above-mentioned SRRC digital filter that is used for base band shaping filtering, traditional implement device generally is to be become with a direct I type (directly type) or the conventional SRRC digital filter cascaded series of direct II type (the direct type of transposition) structure by a M times of interpolater, as shown in Figure 1, FIR (Finite Impulse Response for direct I type and direct II type structure, finite impulse response) the general optimization method of digital filter all can apply to SRRC digital filter herein, comprise the tap that merges symmetry on the tapped delay line, adopt CSD (Canonical Signed Digit, the canonical signed number) split coefficient and optimization adder quantity and output bit wide etc., but the shortcoming of above-mentioned traditional implement device is:

1. for the realization of high-order SRRC digital filter, its tapped delay line is very long, and the weighted sum unit complexity is very high, and the hardware resource that totally takies is very high;

2.SRRC digital filter is operated in the upper frequency after the up-sampling, its hard-wired power consumption and load are all higher;

3. existing optimization means can only self be optimized the SRRC digital filter of routine, and it is limited to optimize effect;

4.I, the Q two-way need take the same device of two covers, not only the demand of hardware resource is huge, and service efficiency is very low.

Summary of the invention

The object of the present invention is to provide a kind of new base-band forming SRRC digital filter low complex degree implementation method and implement device, overcome particularly many weak points such as the big and operating frequency height of the complexity height, the hardware resource occupancy that exist of the traditional implement device of higher order filter in various programmable logic devices, digital signal processor spare or application-specific integrated circuit (ASIC) of base-band forming SRRC digital filter.

For achieving the above object, the present invention adopts following technical scheme:

A kind of base-band forming SRRC digital filter low complex degree implement device, the exponent number of this SRRC digital filter is N, is broken down into M subfilter, and wherein M 〉=2 are interpolation factor, and this device comprises:

The clock source unit provides 2f _s, 4f _sAnd Mf _sThe clock of three kinds of frequencies is if M=2 or M=4 then only need the clock of two kinds of frequencies, wherein f _sSample frequency for input signal;

The multiplexing tapped delay line of two-way unit is at frequency 2f _sClock drive down, two-way input signal timesharing gating is formed the two-way composite input signal, alternately time-delay output and time-delay are deposited, and obtain input vector by its tap

The inverted order unit is with described input vector

Carry out inverted order, be converted to the inverted order vector

The input gating unit is at frequency 4f _sClock drive down, to input vector

With the inverted order vector

Carry out the timesharing gating;

M weighted sum unit is at frequency 4f _sClock drive down time division multiplexing

With With subfilter half coefficient vector

The weighted sum arithmetic unit, finish respectively

With The weighted sum computing, 0≤i≤M-1 wherein;

Postpone sum unit, at frequency 2f _sClock drive down, weighted sum unit is carried out

After the output output of computing is finished and set delay, synchronous with it with weighted sum unit again

The output output of computing is sued for peace, and obtains the filtering operation result of each subfilter;

The adapter unit is at frequency Mf _sClock drive down, to the filtering operation of each subfilter timesharing gating as a result, wherein the two-way perseverance differs 2 gating points, obtains the two-way shaping filter result of SRRC digital filter respectively.

Wherein, between per two taps of the multiplexing tapped delay line of two-way unit the two-stage register is arranged, in the two-way composite input signal that described two-way input signal forms, wherein one the tunnel to put forward previous frequency than another road input be 2f _sClock cycle.

Wherein, the coefficient of M subfilter being broken down into of described SRRC digital filter is:

h _k[n]＝h[k+nM]，k＝0，1，...，M-1； $n=\mathrm{0,1},...,\frac{N}{M}-1$

In the following formula, k represents the label of each subfilter, and N is the exponent number of described SRRC digital filter.

Wherein, described weighted sum unit comprises that partial product is decomposed merge order through transport calculation unit and output unit is adjusted in gain, wherein said partial product is decomposed the computing that merge order through transport calculation unit closes Integral Solution step by step, closes long-pending merging and the long-pending merging of letter, its operation result is adjusted output unit by gain and is finished gain adjustment and position intercept operation, obtains the output of weighted sum unit.

Wherein, described delay sum unit is to the inverted order vector of weighted sum unit output

With the weighted sum operation result of first subfilter half coefficient vector, the individual frequency f of N/ during the single channel input delay (2M) _sClock cycle, N/M frequency 2f delays time altogether during the compound input of two-way _sClock cycle; Described delay sum unit is to the inverted order vector of weighted sum unit output With the weighted sum operation result of second to M subfilter half coefficient vector, respectively postpone N/ (2M)-1 frequency f during single channel input _sClock cycle, N/M-2 frequency 2f respectively delays time during the compound input of two-way _sClock cycle.

Wherein, the time-delay of described delay sum unit preferably realizes with memory.

The present invention also provides a kind of low complex degree implementation method of utilizing said apparatus to reach base-band forming SRRC digital filter, and this method may further comprise the steps:

The two-way input signal is input to the multiplexing tapped delay line of two-way unit, at frequency 2f _sClock drive down, the timesharing gating forms the two-way composite input signal, and its time-delay is obtained input vector

Utilize heterogeneous structure that this SRRC digital filter is resolved into the bank of filters that M sub-filter formed;

Utilize subfilter mirror image symmetry or complementary symmetry characteristic, the weighted sum unit of each subfilter is reduced half;

By the inverted order unit with described input vector

Carry out inverted order, be converted to the inverted order vector

At frequency 4f _sClock drive down, by the input gating unit to input vector

With the inverted order vector

Carry out the timesharing gating;

At frequency 4f _sClock drive down, by the weighted sum unit time division multiplexing

With

With subfilter half coefficient vector

The weighted sum arithmetic unit, finish respectively

With The weighted sum computing, 0≤i≤M-1 wherein;

At frequency 2f _sClock drive down, by the time-delay sum unit weighted sum unit is carried out

After the output output of computing is finished and set delay, synchronous with it with weighted sum unit again

The output output of computing is sued for peace, and obtains the filtering operation result of each subfilter;

At frequency Mf _sClock drive down, to the filtering operation of each subfilter timesharing gating as a result, wherein the two-way perseverance differs 2 gating points, obtains the two-way shaping filter result of SRRC digital filter respectively by the adapter unit.

Wherein, described weighted sum unit time division multiplexing With

With subfilter half coefficient vector

Weighted sum arithmetic unit step in, utilize partial product decompose to merge optimization method and finish

With

The weighted sum computing.

The low complex degree implement device of base-band forming SRRC digital filter provided by the invention and the beneficial effect of method are: the present invention has fully utilized the multiplexing tapped delay line structure of two-way, heterogeneous structure, mirror image symmetry and complementary symmetrical subfilter optimization realize, and the weighted sum unit partial product is decomposed multiple optimisation techniques such as merging the optimization realization, deeply excavate the symmetry of each subfilter of heterogeneous structure or the similar characteristic between similar characteristic and each subfilter self coefficient, multiplexing to greatest extent quantity and the bit wide that takies the more weighted sum computing of resource and optimize adder in the weighted sum computing.Compare with traditional implementation method, the tapped delay line length is simplified be original 1/ (2M), significantly reduce the high-order base-band forming SRRC digital filter and realized required hardware resource, reduced complexity, make filtering operation be operated in lower frequency, and realized the multiplexing same set of filter of I/Q two-way.

Description of drawings

Fig. 1 is a base-band forming SRRC digital filter schematic diagram conventional in the prior art;

Fig. 2 a is the heterogeneous structure principle schematic of base-band forming SRRC digital filter provided by the invention;

Fig. 2 b is the heterogeneous structure specific implementation device schematic diagram of base-band forming SRRC digital filter provided by the invention when getting M=4;

Fig. 3 a is the segmentation implement device schematic diagram that has the subfilter of mirror symmetry under the heterogeneous structure provided by the invention;

Fig. 3 b is the optimization implement device schematic diagram that has the subfilter of mirror symmetry under the heterogeneous structure provided by the invention;

Fig. 4 a is the segmentation implement device schematic diagram that has complementary symmetric subfilter under the heterogeneous structure provided by the invention;

Fig. 4 b is the optimization implement device schematic diagram that has complementary symmetric subfilter under the heterogeneous structure provided by the invention;

Fig. 5 a is that weighted sum unit partial product provided by the invention is decomposed merging optimization implement device schematic diagram;

Fig. 5 b is that partial product provided by the invention is decomposed merge order through transport calculation cellular construction schematic diagram;

Fig. 6 is the multiplexing tapped delay line structural representation of two-way provided by the invention;

Fig. 7 is the low complex degree implementation method operating process schematic diagram of base-band forming SRRC digital filter provided by the invention;

Fig. 8 is the low complex degree implement device schematic diagram (M=4) of base-band forming SRRC digital filter provided by the invention.

Embodiment

The low complex degree implement device and the method for the base-band forming SRRC digital filter that the present invention proposes are described as follows in conjunction with the accompanying drawings and embodiments.

The invention provides the low complex degree implementation method and the device of base-band forming SRRC digital filter.Realize being optimized at the hardware of the SRRC digital filter that is used for base band shaping.With reference to Fig. 1, the conventional structure schematic diagram of expression base-band forming SRRC digital filter as interpolation filter, is actually the cascade of interpolater and digital filter.Be that example elaborates technical scheme of the present invention with interpolation factor M=4 below.

With reference to Fig. 2 a, Fig. 2 b, the heterogeneous structure specific implementation device schematic diagram when representing the heterogeneous structure principle schematic of base-band forming SRRC digital filter provided by the invention and M=4 respectively.If the exponent number of former SRRC digital filter is N, coefficient is h[n].Heterogeneous structure requires when the design digital filter, and its exponent number N must be designed to the multiple of M.Adopt heterogeneous structure, interpolater is removed, and former filter is broken down into M subfilter, and its coefficient table is shown:

$h_k\left[n\right]=h[k+\mathrm{nM}],k=\mathrm{0,1},...,M-1;n=\mathrm{0,1},...,\frac{N}{M}-1$

Subfilter is operated in low sample frequency f _sDown, a tapped delay line is shared in their concurrent operations, makes the tapped delay line length reduce by interpolation factor M, shortens to original 1/M.For the input signal vector that obtains through tapped delay line, each subfilter is in lower frequency f _sUnder finish the weighted sum computing and obtain an output signal because the additional phase shift difference of each subfilter, total output signal is with higher frequency f=Mf _sOutput signal addition summation gained after 0 to M-1 time-delay such as the clock cycle of not waiting to each subfilter.Get M=4, be without loss of generality, the exponent number N that establishes former filter is the multiple of 2M, and the coefficient that then former filter decomposes M the subfilter that obtains is respectively:

$h_0\left[n\right]=\{h_0\left[0\right],h_0[1]),...,h_0\left[\frac{N}{4}\right]\}=\{h\left[0\right],h\left[4\right],h\left[8\right],...,h\left[N\right]\};$

$h_1\left[n\right]=\{h_1\left[0\right],h_1\left[1\right],...,h_1[\frac{N}{4}-1]\}=\{h\left[1\right],h\left[5\right],h\left[9\right],...,h[N-3]\};$

$h_2\left[n\right]=\{h_2\left[0\right],h_2\left[1\right],...,h_2[\frac{N}{4}-1]\}=\{h\left[2\right],h\left[6\right],h\left[10\right],...,h[N-2]\};$

$h_3\left[n\right]=\{h_3\left[0\right],h_3\left[1\right],...,h_3[\frac{N}{4}-1]\}=\{h\left[3\right],h\left[7\right],h\left[11\right],...,h[N-1]\},$

Because former filter is a linear phase FIR filter, is not difficult to draw h according to the symmetry of former filter coefficient ₀[n] and h ₂[n] self has mirror symmetry, h ₁[n] and h ₃[n] has complementary symmetry, that is:

$h_0\left[i\right]=h_0[\frac{N}{4}-i],$ $h_2\left[i\right]=h_2[\frac{N}{4}-1-i],$

$h_1\left[i\right]=h_3[\frac{N}{4}-1-j],$ Wherein $0\&le;i\&le;\frac{N}{8}-1,$ $0\&le;j\&le;\frac{N}{4}-1.$

With reference to Fig. 3 a, Fig. 3 b, represent respectively to have under the heterogeneous structure provided by the invention mirror symmetry subfilter segmentation implement device schematic diagram with and optimize the implement device schematic diagram.For coefficient h ₀[n] and h ₂[n] self has the subfilter of mirror symmetry, its coefficient can be divided to be two sections of front and back equally order

$h_{0a}\left[n\right]=\{h_0\left[0\right],h_0\left[1\right],...,h_0[\frac{N}{8}-1],\frac{h_0\left[\frac{N}{8}\right]}{2}\},$ $h_{0b}\left[n\right]=\{\frac{h_0\left[\frac{N}{8}\right]}{2},h_0[\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8}+1],...,h_0\left[\frac{N}{4}\right]\};$

$h_{2a}\left[n\right]=\{h_2\left[0\right],h_2\left[1\right],...,h_2[\frac{N}{8}-1]\},$ $h_{2b}\left[n\right]=\{h_2\left[\frac{N}{8}\right],h_2[\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8}+1],...,h_2[\frac{N}{4}-1]\},$

Wherein $h_{0b}\left[n\right]=h_{0a}[\frac{N}{8}-n],$ $0\&le;n\&le;\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8};$ $h_{2b}\left[n\right]=h_{2a}[\frac{N}{8}-1-n],$ $0\&le;n\&le;\frac{N}{8}-1.$

According to the mirror symmetry between two segmentation, in fact only need to realize h _0a[n] and h _2a[n] realizes h by upset then _0b[n] and h _2b[n] is again by time domain translation h _0b[n] and h _2b[n] postpones a N/8 and N/8-1 frequency f respectively _sClock cycle, can realize the mirror image of subfilter self.Because a tapped delay line is shared in two segmentations, this segmentation implement device can utilize symmetry that the tapped delay line length is shortened 1/2 again.On this basis further by multiplexing h _0a[n] and h _0b[n] and h _2a[n] and h _2bThe weighted sum unit of [n] has realized nearly half logical resource optimization.With the coefficient is h ₀The 0th work song filter of [n] is an example, concerns according to linear convolution:

$y_{0b}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}}{\mathrm{\&Sigma;}}}x[n-m]\&CenterDot;h_{0b}\left[m\right],$ And $h_{0b}\left[n\right]=h_{0a}[\frac{N}{8}-n],$ $0\&le;n\&le;\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8},$

Can get following new linear convolution relation

$y_{0b}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}}{\mathrm{\&Sigma;}}}x[n-\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8}+m]\&CenterDot;h_{0a}\left[m\right],$ Associating $y_{0a}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}}{\mathrm{\&Sigma;}}}x[n-m]\&CenterDot;h_{0a}\left[m\right],$

Then described optimization implement device can specifically describe as follows: input signal x[n] obtain delay input signal sequence x[n-m through tapped delay line], 0≤m≤N/8, vector representation is $\stackrel{\&RightArrow;}{x}=\left(x\left[n\right]\right),x[n-1],...,x[n-N/8])$ Again above-mentioned sequence is carried out inverted order and handles, obtain new delayed sequence x[n-N/8+m], 0≤m≤N/8, vector representation is $\stackrel{\&RightArrow;}{x}\&prime;=(x[n-N/8],x[n-N/8+1],...,x\left[n\right]);$ With frequency 2f _sTo two groups of sequences

With Carry out gating, being input to operating frequency is 2f _s, coefficient is h _0aIn the weighted sum unit of [n], finish above-mentioned two groups of weighted sum computings respectively, obtain y _0a[n] and y _0b[n]; And y _0b[n] then needs to postpone N/8 frequency f _sClock cycle, again with y _0a[n] summation, y is exported in the filtering that obtains the 0th work song filter ₀[n], i.e. y ₀[n]=y _0a[n]+y _0b[n] δ [n-N/8].Coefficient is h ₂The optimization implement device of the 2nd work song filter of [n] is same as above, and difference is that it is the N/8-1 rank.

With reference to Fig. 4 a, Fig. 4 b, the segmentation implement device schematic diagram of representing to have under the heterogeneous structure provided by the invention complementary symmetric subfilter respectively with and optimize the implement device schematic diagram.For coefficient h ₁[n] and h ₃[n] has complementary symmetric subfilter, its coefficient divided to be two sections of front and back equally equally order

$h_{1a}\left[n\right]=\{h_1\left[0\right],h_1\left[1\right],...,h_1[\frac{N}{8}-1]\},$ $h_{1b}\left[n\right]=\{h_1\left[\frac{N}{8}\right],h_1[\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8}+1],...,h_1[\frac{N}{4}-1]\};$

$h_{3a}\left[n\right]=\{h_3\left[0\right],h_3\left[1\right],...,h_3[\frac{N}{8}-1]\},$ $h_{3b}\left[n\right]=\{h_3\left[\frac{N}{8}\right],h_3[\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8}+1],...,h_3[\frac{N}{4}-1]\},$

H wherein _3b[n]=h _1a[N/8-1-n], h _1b[n]=h _3a[N/8-1-n], 0≤n≤N/8-1.According to the segmentation complementary symmetry each other of two subfilters, in fact only need to realize h _1a[n] and h _3a[n] realizes h by upset then _3b[n] and h _1b[n] is again by time domain translation h _1b[n] and h _3b[n] postpones N/8-1 frequency f _sClock cycle, can realize the complementary symmetrical structure between the subfilter.As previously mentioned, the tapped delay line of same 1/2 length of using of this segmentation implement device.On this basis, further by multiplexing h _1a[n] and h _3b[n] and h _1b[n] and h _3aThe weighted sum unit of [n] has realized nearly half logical resource optimization.Concern according to linear convolution:

$y_{1b}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}-1}{\mathrm{\&Sigma;}}}x[n-m]\&CenterDot;h_{1b}\left[m\right]$ With $y_{3b}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}-1}{\mathrm{\&Sigma;}}}x[n-m]\&CenterDot;h_{3b}\left[m\right],$

And $h_{1b}\left[n\right]=h_{3a}[\frac{N}{8}-1-n]$ With $h_{3b}\left[n\right]=h_{1a}[\frac{N}{8}-1-n],$ $0\&le;n\&le;\frac{N}{8}-1,$

Can get following new linear convolution relation

$y_{1b}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}-1}{\mathrm{\&Sigma;}}}x[n-\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8}+1+m]\&CenterDot;h_{3a}\left[m\right]$ With $y_{3b}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}-1}{\mathrm{\&Sigma;}}}x[n-\frac{\mathrm{<figure-callout\; id="8"\; label="N"\; filenames="H2008102225146E00021.png,H2008102225146E00031.png"\; state="\{\{state\}\}">N</figure-callout>}}{8}+1+m]\&CenterDot;h_{1a}\left[m\right],$

Associating $y_{1a}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}-1}{\mathrm{\&Sigma;}}}x[n-m]\&CenterDot;h_{1a}\left[m\right]$ With $y_{3a}\left[n\right]=\underset{m=0}{\overset{\frac{N}{8}-1}{\mathrm{\&Sigma;}}}x[n-m]\&CenterDot;h_{3a}\left[m\right],$

Then described optimization implement device can specifically describe as follows: input signal x[n] obtain delay input signal sequence x[n-m through tapped delay line], 0≤m≤N/8-1, vector representation is $\stackrel{\&RightArrow;}{x}=(x\left[n\right],x[n-1],...,x[n-N/8+1]);$ Again above-mentioned sequence is carried out inverted order and handles, obtain new delayed sequence x[n-N/8+1+m], 0≤m≤N/8-1, vector representation is $\stackrel{\&RightArrow;}{x}\&prime;=(x[n-N/8+1],x[n-N/8+2],...,x\left[n\right]);$ With frequency 2f _sTo two groups of sequences

With ' carry out gating, being input to operating frequency respectively is 2f _s, coefficient is h _1a[n] and h _3aIn the weighted sum unit of [n], finish above-mentioned four groups of weighted sum computings respectively, obtain y _1a[n], y _1b[n] and y _3a[n], y _3b[n]; And y _1b[n] and y _3b[n] then needs to postpone N/8-1 frequency f _sClock cycle, more respectively with y _1a[n] and y _3a[n] summation, y is exported in the filtering that obtains the 1st work song filter and the 3rd work song filter ₁[n] and y ₃[n], i.e. y ₁[n]=y _1a[n]+y _1b[n] δ [n-N/8+1] and y ₃[n]=y _3a[n]+y ₃B[n] δ [n-N/8+1].

What deserves to be explained is y _0b[n] postpones N/8 frequency f _sClock cycle, y _1b[n], y _2b[n] and y _3b[n] respectively postpones N/8-1 frequency f _sClock cycle, delay herein is different with the delay of tapped delay line.In the middle of hardware was realized, delay herein can realize with memory, just uses memory resource to substitute more valuable register resources, when reducing the tapped delay line complexity, had improved the comprehensive service efficiency of various types of hardware resource.

With reference to Fig. 5 a, Fig. 5 b, represent that respectively weighted sum unit partial product provided by the invention is decomposed merging optimization implement device schematic diagram and partial product is wherein decomposed merge order through transport calculation cellular construction schematic diagram.As previously mentioned, four subfilters are shared a tapped delay line, in fact only need to realize that coefficient is respectively h _0a[n], h _1a[n], h _2a[n] and h _3aFour sectionally weighting sum unit of [n].With reference to patent " direct type implementation method of a kind of Finite Impulse Response filter and implement device " (number of patent application 200810101448.7), for each group coefficient h _Ka[n], k=0,1,2,3, adopt optimisation technique at similar characteristic between coefficient---partial product is decomposed and is merged optimisation technique, further weighted sum unit is optimized.With the coefficient is h _0aThe weighted sum unit of [n] is an example, and described optimization implement device specifically describes as follows: this weighted sum unit decomposes merge order through transport calculation unit by partial product and the submodules such as adjusting output unit that gains constitutes.Input vector through tapped delay line (comprise what the process inverted order was handled

), be input to partial product and decompose merge order through transport calculation unit, combine the conversion of finishing partial product with coefficient in the first order, close Integral Solution at each grade successively then, close long-pending the merging and the long-pending computing that merges of letter, a letter that obtains at last is long-pending promptly to be the result of weighted sum computing, be entered into gain again and adjust output unit, finish corresponding gain adjustment and position intercept operation, obtain the final output y of this weighted sum unit according to required precision of output and gain _0a[n] (comprises y _0b[n]).Coefficient is h _1a[n], h _2a[n] and h _3aIt is same as above that the weighted sum unit partial product of [n] is decomposed merging optimization implement device.

With reference to Fig. 6, represent the multiplexing tapped delay line structural representation of two-way provided by the invention.If former single channel tapped delay line is operated in f _sFrequency, the multiplexing tapped delay line of then described two-way is operated in 2f _sFrequency has the two-stage register between per two taps, and two frequency 2f promptly delay time _sClock cycle.Described tapped delay line be input as I road input signal x _I[n] and Q road input signal x _Q[n] establishes x by the compound alternately input of the two-way after the gating _IThe input of [n] is than x _QPrevious frequency 2f is carried in the input of [n] _sClock cycle, the tap time delayed signal x when each tap output I road _IWhen [n-m], deposit the second level that each time delayed signal on Q road just in time enters between the tap; Otherwise tap time delayed signal x when each tap output Q road _QWhen [n-m], deposit the second level that each time delayed signal on I road also just in time enters between the tap.Adopt described tapped delay line, realized the multiplexing same set of filter of I/Q two-way, latter linked all devices in the tap of this delay line, its operating frequency all need rise to original 2 times, and the memory latency unit after weighted sum unit, its memory capacity also needs correspondingly to expand and is twice, and is used to store the I/Q two paths of data to realize I/Q two-way time division multiplexing.

With reference to Fig. 7, Fig. 8, base-band forming SRRC digital filter low complex degree implement device (M=4) schematic diagram of representing the operating process schematic diagram of base-band forming SRRC digital filter low complex degree implementation method provided by the invention respectively and adopting this method.This realization transposition comprises: the clock source unit provides 2f _sAnd 4f _sThe clock of two kinds of frequencies, wherein f _sEmploying frequency for input signal; The multiplexing tapped delay line of two-way unit is at frequency 2f _sClock drive down, by timesharing gating formation I/Q two-way composite input signal, the line delay of going forward side by side obtains input vector with I, Q two-way input signal $\stackrel{\&RightArrow;}{x}=(x\left[n\right],x[n-1],...,x[n-N]);$ The inverted order unit is with input vector Carry out inverted order, be converted to the inverted order vector $\stackrel{\&RightArrow;}{x}\&prime;=(x[n-N],x[n-N+1],...,x\left[n\right]);$ The input gating unit is at frequency 4f _sClock drive down, to two groups of input vectors With

Carry out the timesharing gating; M weighted sum unit belongs to an above-mentioned M subfilter respectively, and the weighted sum unit of each subfilter is at frequency 4f _sClock drive down the time division multiplexing input vector

With

With subfilter half coefficient vector

The weighted sum arithmetic unit, finish respectively

With The weighted sum computing, 0≤i≤M-1, the sequence number of expression subfilter, wherein, comprise in the weighted sum unit that partial product is decomposed merge order through transport calculation unit and output unit is adjusted in gain, partial product is decomposed the computing that merge order through transport calculation unit closes Integral Solution step by step, closes long-pending merging and the long-pending merging of letter, and its operation result is finished gain by gain adjustment output unit and adjusted and the position intercept operation, obtains the output of weighted sum unit; Postpone sum unit, at frequency 2f _sClock drive down, weighted sum unit is carried out The output of the output of computing is finished specific delay again and synchronous with it The output output summation of computing obtains the filtering operation result of each subfilter; The adapter unit is at frequency 4f _sClock drive down, to the filtering operation of each subfilter timesharing gating as a result, wherein I, Q two-way perseverance differ 2 gating points, the I, the Q two-way that obtain this SRRC digital filter are respectively finally exported the result.

The low complex degree implement device of the described base-band forming SRRC digital filter of present embodiment has adopted the multiplexing tapped delay line structure of two-way, heterogeneous structure, mirror image symmetry and complementary symmetrical subfilter optimization realization and weighted sum unit partial product are decomposed and are merged multiple optimisation techniques such as optimizing realization, the tapped delay line length is simplified be original 1/ (2M), deeply excavate the symmetry of each subfilter of heterogeneous structure or the similar characteristic between similar characteristic and each subfilter self coefficient, multiplexing to greatest extent quantity and the bit wide that takies the more weighted sum computing of resource and optimize adder in the weighted sum computing, significantly reduce the high-order base-band forming SRRC digital filter and realized required hardware resource, reduced complexity, make filtering operation be operated in lower frequency, and realized the multiplexing same set of filter of I/Q two-way.

As shown in Figure 7, utilize said apparatus to reach the low complex degree implementation method of base-band forming SRRC digital filter, may further comprise the steps:

Steps A adopts the multiplexing tapped delay line technology of I/Q two-way, realizes the multiplexing same set of filter of I/Q two-way, the two-way input signal is input to the multiplexing delay line of two-way, at frequency 2f _sClock drive down, the timesharing gating forms the two-way composite input signal, and its time-delay is obtained input vector

Step B adopts the heterogeneous structure filtering technique, and former SRRC digital filter is resolved into the bank of filters that a plurality of subfilters are formed;

Step C utilizes subfilter mirror image symmetry or complementary symmetrical characteristic optimizing realization technology, and the weighted sum unit of each subfilter is reduced half;

Step D, by the inverted order unit with described input vector

Carry out inverted order, be converted to the inverted order vector

Step e is by importing gating unit to input vector

With the inverted order vector

Carry out the timesharing gating;

Step F is at frequency 4f _sClock drive down, by the weighted sum unit time division multiplexing

With

With subfilter half coefficient vector

The weighted sum arithmetic unit, finish respectively

With

The weighted sum computing, 0≤i≤M-1 wherein;

Step G is at frequency 2f _sClock drive down, by the time-delay sum unit weighted sum unit is carried out

After the output output of computing is finished and set delay, synchronous with it with weighted sum unit again

The output output of computing is sued for peace, and obtains the filtering operation result of each subfilter;

Step H is at frequency Mf _sClock drive down, to the filtering operation of each subfilter timesharing gating as a result, wherein the two-way perseverance differs 2 gating points, obtains the two-way shaping filter result of SRRC digital filter respectively by the adapter unit.

Among the above-mentioned steps F, adopt the similar bank of filters optimization of FIR to realize technology, by the conversion input vector

The weighted sum unit of each subfilter of time division multiplexing, and adopt direct type optimization to realize technology at Finite Impulse Response filter coefficient similitude, promptly partial product is decomposed and is merged optimization realization technology, realizes the weighted sum unit of each subfilter.

The present invention proposes the low complex degree implementation method and the device of base-band forming SRRC digital filter, the directly type direct type that realizes (being called for short direct type), adopt the direct type of heterogeneous structure to realize (being called for short heterogeneous direct type), adopt heterogeneous structure and utilize the symmetry of subfilter group the to be optimized direct type realization (being called for short heterogeneous subfilter coefficient optimization type) that realizes (being called for short heterogeneous subfilter group optimization type) and adopt heterogeneous structure and utilize the similitude of filter self coefficient to be optimized of the tradition that is used for comprising the SRRC digital filter with reference to relatively implementation method.With reference to table 1, represent that the low complex degree implementation method (being called for short heterogeneous complex optimum type) that above-mentioned four kinds of implementation methods and the present invention propose contrasts at the logical resource that FPGA realizes.The SRRC digital filter exponent number of wherein being realized is 384, and rolloff-factor is 0.05, and filter coefficient adopts 14-bit to quantize, and the input bit wide is 14-bit; Being used for logic analysis and comprehensive platform is Quartus II, and FPGA device model is Altera Stratix II EP2S90F1020C5.The combinational logic and the register logical resource that take when FPGA realizes of the implementation method that proposes of the present invention is all minimum as can be seen from Table 1, and shared memory resource only accounts for 4/1000 of the whole memory resources of this FPGA.

Table 1

SRRC digital filter implementation method	LC?Combinationals	LC?Registers	Memory?bits
				Direct type	10246	10810	0
Heterogeneous direct type	11575	2906	0
				Heterogeneous subfilter group optimization type	6633	2262	18432
Heterogeneous subfilter coefficient optimization type	8494	2842	0
				Heterogeneous complex optimum type	5161	2192	18432

The low complex degree implementation method and the device of the base-band forming SRRC digital filter that the present invention proposes are the complex optimums that carries out on the basis of interpolation or decimation filter polyphase implementation structure.Therefore but technical scheme expanded application of the present invention realizes in the common interpolation of all interpolations or extraction factor M 〉=2 or the hardware of extraction Finite Impulse Response filter.

Above execution mode only is used to illustrate the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.

Claims (8)

1. the low complex degree implement device of base-band forming SRRC digital filter, the exponent number of this SRRC digital filter is N, is broken down into M subfilter, and wherein M 〉=2 are interpolation factor, it is characterized in that, and this device comprises:

The clock source unit provides 2f _s, 4f _sAnd Mf _sThe clock of three kinds of frequencies is if M=2 or M=4 then only need the clock of two kinds of frequencies, wherein f _sSample frequency for input signal;

The multiplexing tapped delay line of two-way unit is at frequency 2f _sClock drive down, two-way input signal timesharing gating is formed the two-way composite input signal, alternately time-delay output and time-delay are deposited, and obtain input vector by its tap

The inverted order unit is with described input vector

Carry out inverted order, be converted to the inverted order vector

The input gating unit is at frequency 4f _sClock drive down, to input vector

With the inverted order vector

Carry out the timesharing gating;

M weighted sum unit is at frequency 4f _sClock drive down time division multiplexing

With With subfilter half coefficient vector

The weighted sum arithmetic unit, finish respectively

With

The weighted sum computing, 0≤i≤M-1 wherein;

Postpone sum unit, at frequency 2f _sClock drive down, weighted sum unit is carried out

After the output output of computing is finished and set delay, synchronous with it with weighted sum unit again

The output output of computing is sued for peace, and obtains the filtering operation result of each subfilter;

The adapter unit is at frequency Mf _sClock drive down, to the filtering operation of each subfilter timesharing gating as a result, wherein the two-way perseverance differs 2 gating points, obtains the two-way shaping filter result of SRRC digital filter respectively.

2. the low complex degree implement device of base-band forming SRRC digital filter as claimed in claim 1, it is characterized in that, between per two taps of the multiplexing tapped delay line of two-way unit the two-stage register is arranged, in the two-way composite input signal that described two-way input signal forms, wherein one the tunnel to put forward previous frequency than another road input be 2f _sClock cycle.

3. the low complex degree implement device of base-band forming SRRC digital filter as claimed in claim 1 is characterized in that, the coefficient of M the subfilter that described SRRC digital filter is broken down into is:

$h_k\left[n\right]=h[k+\mathrm{nM}],k=\mathrm{0,1},...,M-1;n=\mathrm{0,1},...,\frac{N}{M}-1$

In the following formula, k represents the label of each subfilter, and N is the exponent number of described SRRC digital filter.

4. the low complex degree implement device of base-band forming SRRC digital filter as claimed in claim 1, it is characterized in that, described weighted sum unit comprises that partial product is decomposed merge order through transport calculation unit and output unit is adjusted in gain, wherein said partial product is decomposed the computing that merge order through transport calculation unit closes Integral Solution step by step, closes long-pending merging and the long-pending merging of letter, its operation result is adjusted output unit by gain and is finished gain adjustment and position intercept operation, obtains the output of weighted sum unit.

5. the low complex degree implement device of base-band forming SRRC digital filter as claimed in claim 1 is characterized in that, described delay sum unit is to the inverted order vector of weighted sum unit output

With the weighted sum operation result of first subfilter half coefficient vector, the individual frequency f of N/ during the single channel input delay (2M) _sClock cycle, N/M frequency 2f delays time altogether during the compound input of two-way _sClock cycle; Described delay sum unit is to the inverted order vector of weighted sum unit output With the weighted sum operation result of second to M subfilter half coefficient vector, respectively postpone N/ (2M)-1 frequency f during single channel input _sClock cycle, N/M-2 frequency 2f respectively delays time during the compound input of two-way _sClock cycle.

6. the low complex degree implement device of base-band forming SRRC digital filter as claimed in claim 5 is characterized in that, the time-delay of described delay sum unit preferably realizes with memory.

7. low complex degree implementation method of utilizing the described device of claim 1 to reach base-band forming SRRC digital filter is characterized in that this method may further comprise the steps:

The two-way input signal is input to the multiplexing tapped delay line of two-way unit, at frequency 2f _sClock drive down, the timesharing gating forms the two-way composite input signal, and its time-delay is obtained input vector

Utilize heterogeneous structure that this SRRC digital filter is resolved into the bank of filters that M sub-filter formed;

Utilize subfilter mirror image symmetry or complementary symmetry characteristic, the weighted sum unit of each subfilter is reduced half;

By the inverted order unit with described input vector

Carry out inverted order, be converted to the inverted order vector

At frequency 4f _sClock drive down, by the input gating unit to input vector

With the inverted order vector Carry out the timesharing gating;

At frequency 4f _sClock drive down, by the weighted sum unit time division multiplexing

With With subfilter half coefficient vector

The weighted sum arithmetic unit, finish respectively

With

The weighted sum computing, 0≤i≤M-1 wherein;

At frequency 2f _sClock drive down, by the time-delay sum unit weighted sum unit is carried out

After the output output of computing is finished and set delay, synchronous with it with weighted sum unit again

The output output of computing is sued for peace, and obtains the filtering operation result of each subfilter;

At frequency Mf _sClock drive down, to the filtering operation of each subfilter timesharing gating as a result, wherein the two-way perseverance differs 2 gating points, obtains the two-way shaping filter result of SRRC digital filter respectively by the adapter unit.

8. the low complex degree implementation method of base-band forming SRRC digital filter as claimed in claim 7 is characterized in that, described weighted sum unit time division multiplexing

With With subfilter half coefficient vector

Weighted sum arithmetic unit step in, utilize partial product decompose to merge optimization method and finish

With

The weighted sum computing.

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