CN102035503B - Filtering device and filtering method of cascaded integral comb filter - Google Patents
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Abstract
本发明涉及通信领域，公开了一种滤波装置及级联积分梳状滤波器的滤波方法。本发明中，通过对级联积分梳状滤波器中包含的级联积分器和级联梳状滤波器的复用，使得同一个级联积分梳状滤波器既可以作为级联积分梳状抽取滤波器进行工作，也可以作为级联积分梳状插值滤波器进行工作，从而无需在接收通道和发送通道各设置一个级联积分梳状滤波器，在达到性能指标的同时，较好地节省逻辑资源，降低了成本。
The invention relates to the communication field, and discloses a filtering device and a filtering method of a cascaded integral comb filter. In the present invention, by multiplexing the cascaded integrators and cascaded comb filters included in the cascaded integral comb filter, the same cascaded integral comb filter can be used as a cascaded integral comb filter The filter can also work as a cascaded integral comb interpolation filter, so that there is no need to set a cascaded integral comb filter in the receiving channel and the transmitting channel, and it can save logic while achieving the performance index. resources, reducing costs.
Description
Technical field
The present invention relates to the communications field, particularly the upper and lower converter technique in the communications field.
Background technology
Digital Down Convert (Digital Down Conversion is called for short " DDC ") and Digital Up Convert (Digital Up Conversion is called for short " DUC ") are one of key technologies in communication system.As shown in Figure 1, in digital transmitter, base band data is through DUC, sample rate is improved, pass through again CFR (crest factor decay) and DPD (digital pre-distortion), then pass through mixing and DAC (digital to analog converter), useful signal is moved to RF (radio frequency) and send; At receiving terminal, signal, after analog-to-digital conversion (AD), through DDC, is delivered to Base-Band Processing.
Wherein, DDC mainly comprises mixing and filtering extraction process, wherein decimation filter is generally by cascade integral comb filter (Cascaded Integrator Comb filter, be called for short " cic filter "), half-band filter (Half Band filter, be called for short " HB filter ") and finite impulse response filter (Finite Impulse Response is called for short " FIR filter ") formation.The effect of decimation filter, is the sample rate of signal after reduction mixing, the line frequency of going forward side by side compensation and low-pass filtering, thus useful signal is moved to base band, and make this signal in lower sample frequency, thus the burden of follow-up Base-Band Processing greatly reduced.Cic filter has good low-frequency filter characteristics.In view of cic filter has without multiplier, can be applied to wider frequency translation scope without coefficient storage unit, simple in structure and regular, same structure, etc. advantage, cic filter is as the essential elements of DDC, usually be used as the first order of decimation filter, as shown in Figure 2, the NCO in Fig. 2 represents digital controlled oscillator (Number Controlled Oscillator).
As shown in Figure 3, wherein module 320 is abstraction module to cic filter structure in DDC, in every R sampling, extracts a sampling, thereby completes R down-conversion doubly, and wherein R is extraction yield, i.e. down-conversion multiple.Module 310 is cascade integrator, exports for input signal being carried out after cascade integral is processed, and is made up of, as shown in Figure 4 N integrator cascade.Signal sampling frequency is f
s.Wherein, the exponent number that N is cic filter, transfer function is:
module 330 is cascade comb filter, exports for input signal being carried out after comb filtering is processed, and is made up of, as shown in Figure 5 N comb filter cascade.Signal sampling frequency is f
s/ R.Wherein, M is delay factor, is generally 1 or 2.N is the exponent number of cic filter, and transfer function is: H
c(z)=(1-z
-M)
n.
DUC is the inverse process of DDC.DUC uses CIC interpolation filter to carry out filtering interpolation.As shown in Figure 6, wherein module 620 is interpolating module to CIC interpolation filter, inserts R-1 0 between two adjacent sampled values, thereby sample rate is improved to R doubly.Module 310 is above-mentioned cascade integrator, and module 330 is above-mentioned cascade comb filter.
In half-duplex operation, receive and share a carrier channel with sending, but synchronization can only send and maybe can only receive data.Therefore, half-duplex communication device, sending and receiving function is that timesharing is effective.Under sending mode, sending function is effective; Under receiving mode, receiving function is (as shown in Figure 7) effectively.In existing design, the sending mode function of equipment and receiving mode function be design respectively often.Therefore, in sending function module, there is CIC interpolation filter, in receiving module, have CIC decimation filter.That is to say, in traditional design, in reception and sendaisle, have 2 cic filters.
But the present inventor finds, in traditional design, does not make full use of CIC interpolation filter and CIC decimation filter in characteristic and structural similitude, has caused the waste of logical resource.
Summary of the invention
The object of the present invention is to provide the filtering method of a kind of filter and cascade integral comb filter, make in reaching performance index, save preferably logical resource, reduce costs.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of filter, comprise cascade integral comb filter, and this cascade integral comb filter for carrying out after filtering extraction is processed exporting to the signal of input in the time need carrying out down-conversion; And for the signal of input being carried out after filtering interpolation is processed exporting in the time need carrying out up-conversion.
Embodiments of the present invention also provide a kind of filtering method of cascade integral comb filter, comprise following steps:
Multiplexing by cascade integrator and cascade comb filter, in the time that need carry out down-conversion, cascade integral comb filter carries out after filtering extraction is processed exporting to the signal of input, in the time that need carry out up-conversion, cascade integral comb filter carries out after filtering interpolation is processed exporting to the signal of input.
Compared with prior art, the main distinction and effect thereof are embodiment of the present invention:
In the time that need carry out down-conversion, cascade integral comb filter carries out filtering extraction to the signal of input and processes rear output, and in the time that need carry out up-conversion, cascade integral comb filter carries out after filtering interpolation is processed exporting to the signal of input.The processing that both can become for upper frequency due to cascade integrator and cascade comb filter, the processing that also can become for lower frequency, make same cic filter both can under receiving mode, carry out work as CIC decimation filter, also can under sending mode, carry out work as CIC interpolation filter, thereby without at receive path and sendaisle, a cic filter being respectively set, in reaching performance index, save preferably logical resource, reduce cost.
Further, utilize several data selectors, realize the multiplexing of cascade integrator and cascade comb filter, make in the time that needs carry out lower frequency change, the operating state of cic filter is equal to CIC decimation filter; While frequently change on needs carry out, the operating state of cic filter is equal to CIC interpolation filter, thereby realizes the multiplexing of cic filter with less cost.
Further, in the time there is the switching between receiving mode and sending mode and/or need Global reset, by reseting module, cascade integrator, abstraction module, cascade comb filter, interpolating module are resetted, to avoid in pattern transfer process, the impact of the data of having stored on new arithmetic operation.
Accompanying drawing explanation
Fig. 1 is the processing schematic diagram according to DDC of the prior art and DUC;
Fig. 2 is according to the structural representation of DDC module of the prior art;
Fig. 3 is according to the cic filter structural representation in DDC of the prior art;
Fig. 4 is the structural representation according to cascade integrator of the prior art;
Fig. 5 is according to the structural representation of cascade comb filter of the prior art;
Fig. 6 is according to the cic filter structural representation in DUC of the prior art;
Fig. 7 receives and sends the schematic diagram that shares a carrier channel according to half-duplex communication device of the prior art;
Fig. 8 is the filter structural representation according to first embodiment of the invention;
Fig. 9 is according to the structural representation of the reseting module in first embodiment of the invention.
Figure 10 is the filtering method flow chart according to the cascade integral comb filter of third embodiment of the invention.
Embodiment
In the following description, in order to make reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs and the many variations based on following execution mode and modification, also can realize the each claim of the application technical scheme required for protection.
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
Because the frequency characteristic of cic filter is only subject to its 3 parameter influences: extract or interpolation multiple the R mentioning in above; The exponent number of CIC, the N mentioning in above; Delay factor, the M mentioning in above.Therefore, when above-mentioned 3 parameters are fixed, the frequency characteristic of cic filter, or claim filtering characteristic just fixing.That is to say, for same application, signal bandwidth is relatively-stationary, and the DUC carrying out under sending mode is the inverse process of the DDC that carries out under receiving mode.Therefore can use the cic filter of identical parameters (R, N, M).CIC interpolation filter and CIC decimation filter that comparative parameter (R, N, M) is identical, visible, both cascade integrator are identical, and are operated in identical clock frequency.Equally, both cascade comb filter are also identical, and are operated in identical clock frequency.Just, in the process of DUC, need to use CIC interpolation filter structure (Fig. 6), and use an interpolating module 620; And under receiving mode, need to use CIC decimation filter structure (Fig. 4), and use an abstraction module 320.
Based on above analysis, in the present invention, by the time-sharing multiplex to cascade integrator and cascade comb filter, make the same cic filter in half-duplex apparatus both can under receiving mode, carry out work as CIC decimation filter, also can under sending mode, carry out work as CIC interpolation filter.
First embodiment of the invention relates to a kind of filter, comprises cic filter.The core of present embodiment is, cic filter for carrying out after filtering extraction is processed exporting to the signal of input when need carry out down-conversion; And for the signal of input being carried out after filtering interpolation is processed exporting in the time need carrying out up-conversion.
Specifically, as shown in Figure 8, this cic filter comprises the structure of this cic filter:
Cascade integrator 310, exports for input signal being carried out after cascade integral is processed.
Cascade comb filter 330, exports for input signal being carried out after comb filtering is processed.
Interpolating module 620, for input signal is carried out exporting after interpolation, the frequency conversion multiple of this interpolating module is R2.
The first data selector 810, for the output signal of the output signal in cic filter front stage circuits and interpolating module, selects a kind of input signal as cascade integrator.
The second data selector 820, for the output signal in cascade integrator and low level, selects a kind of input signal as abstraction module.
The 3rd data selector 830, for the output signal of the output signal at abstraction module and cic filter front stage circuits, selects a kind of input signal as cascade comb filter.
The 4th data selector 840, for the output signal of the output signal in cascade comb filter and cascade integrator, selects a kind of output signal as cic filter.
Reseting module, for resetting to cascade integrator, abstraction module, cascade comb filter, interpolating module.This reseting module, in the time the switching between receiving mode and sending mode occurring and/or need Global reset, resets to cascade integrator, abstraction module, cascade comb filter, interpolating module.
Specifically, data selector 810,820,830 and 840 all, according to for representing the current id signal in reception or the state of transmission, is selected.In the present embodiment, take id signal as 0 o'clock, represent currently in sending mode, in the time that id signal is 1, representing current is example in receiving mode, is specifically described.
If id signal is 1, illustrate currently in receiving mode, the first data selector 810 selects the output signal of cic filter front stage circuits as the input signal of cascade integrator; The second data selector 820 selects the output signal of cascade integrator as the input signal of abstraction module; The output signal of the 3rd data selector 830 selecting extraction modules is as the input signal of cascade comb filter; The 4th data selector 840 selects the output signal of cascade comb filter as the output signal of cic filter.
If id signal is 0, illustrate current in sending mode, the 3rd data selector 830 selects the output signal of cic filter front stage circuits as the input signal of cascade comb filter, the input signal that the output signal of cascade comb filter is interpolating module; The first data selector 810 selects the output signal of interpolating module as the input signal of cascade integrator; The 4th data selector 840 selects the output signal of cascade integrator as the output signal of cic filter.The second data selector 820 is selected the input signal of low level as abstraction module.
As shown in Figure 8, the line that sending mode and receiving mode are shared and module, used and add thick lines mark; The line and the module that only under sending mode, use, used dotted line mark; The line and the module that only under receiving mode, use, used solid line.Rec_tran signal indication id signal in Fig. 8, the selection of sending mode and receiving mode is by this rec_tran signal controlling.(Low level effective, resets interlock circuit to reset signal indication reset signal in Fig. 8; High level, circuit is normally worked).Data_in signal is data input signal, from the data output signal of the front stage circuits of this cic filter.Data_out signal is data output signal, and this data_out signal is gone to the late-class circuit of this cic filter through a 1 tunnel-2 circuit-switched data distributor 850.Such as if under receiving mode (being that rec_tran signal is 1), this cic filter is equal to a CIC decimation filter, data_out signal will be input to the late-class circuit of CIC decimation filter of the prior art so; If under sending mode (being that rec_tran signal is 0), this cic filter is equal to a CIC interpolation filter, and data_out signal will be input to the late-class circuit of CIC interpolation filter of the prior art so.That is to say, the output signal of the cic filter in present embodiment will be through a 1 tunnel-2 circuit-switched data distributor, select the data input signal using the output signal of this cic filter as the late-class circuit of CIC decimation filter, the maybe data input signal using the output signal of this cic filter as the late-class circuit of CIC interpolation filter by this 1 tunnel-2 circuit-switched data distributor.
It is worth mentioning that, in the present embodiment, utilize reseting module at Global reset with in pattern transfer process, provide reset signal reset, can effectively avoid in pattern transfer process the impact of the data of having stored on new arithmetic operation.In actual applications, this reseting module only can be realized with two d type flip flops and few combinational logic circuit, and as shown in Figure 9, wherein, rst_n signal is that (Low level effective, resets interlock circuit to global reset signal; High level, circuit is normally worked), module 910 and 920 is d type flip flop, and module 930 is XOR gate, and module 940 is not gate, and module 950 is and door.When rst_n is low level, or rec_tran occur reversion change time, reset produces low level signal, exports to cascade integrator, abstraction module, cascade comb filter and interpolating module as reset signal; When rst_n is high level, and rec_tran is while remaining unchanged, and reset signal is high level, and cascade integrator, abstraction module, cascade comb filter and interpolating module are normally worked.
Be not difficult to find, in the present embodiment, the processing that both can become for upper frequency due to cascade integrator and cascade comb filter, the processing that also can become for lower frequency, make same cic filter both can under receiving mode, carry out work as CIC decimation filter, also can under sending mode, carry out work as CIC interpolation filter, thereby without at receive path and sendaisle, a cic filter being respectively set, in reaching performance index, save preferably logical resource, reduce cost, can be applicable to low-voltage powerline carrier communication chip.That is to say, use cic filter as shown in Figure 8, save the cascade integrator of a cic filter and the resource of cascade comb filter with respect to traditional design, saved the adder of 2N B position and (N+NM) resource of individual d type flip flop.
And, by utilizing several data selectors, realize the multiplexing of cascade integrator and cascade comb filter, make in the time that needs carry out lower frequency change, the operating state of cic filter is equal to CIC decimation filter.While frequently change on needs carry out, the operating state of cic filter is equal to CIC interpolation filter, thereby realizes the multiplexing of cic filter with less cost.Make a concrete analysis of as follows:
With cic filter conventional in communication (12 bit inputs, 12 bit outputs, N=6) be example, if use full precision model (full accuracy model, in design process, every one-level is all used the wide register of most significant digit, thereby avoid spillover), be the middle maximum bit wide 46bit that all use at different levels of cic filter, be truncation (cut-out) at output port data_out place, the resource that 4 data selectors take in chip hejian 0.18um 3.3V lib is about 0.56K door, and (the shared resource of reseting module is very little, can ignore), and 1 cic filter saving, the resource taking in chip hejian 0.18um 3.3V lib is about 9.6K door, that is to say, income is 9.6K door-0.56K door, be about 9K door.
With cic filter conventional in communication (12 bit inputs, 12 bit outputs, N=6) be example, if use min bit-width model, be the rounding and truncation (rounding off and cut position) that all use at different levels in the middle of CIC, to reduce resource occupation, the resource that 4 data selectors take in chip hejian0.18um 3.3V lib is about 0.28K door, and (the shared resource of reseting module is very little, can ignore), and 1 cic filter saving, the resource taking in chip hejian 0.18um 3.3V lib is about 6.2K door, that is to say, income is 6.2K door-0.28K door, be about 6K door.
More known by above analysis, use present embodiment, the resource that can save about 1 CIC filer circuit.In conventional design, the resource of this saving is approximately 6K door to 9K door.And, along with the increase of the progression N of required cic filter in design, the increase that will be directly proportional of the resource of this saving.
Second embodiment of the invention relates to a kind of filter.The second execution mode and the first execution mode are basic identical, and difference is mainly:
In the first embodiment, id signal is 0 o'clock, represents currently in sending mode, in the time that id signal is 1, represents current in receiving mode.And in the present embodiment, id signal is 0 o'clock, represent currently in receiving mode, in the time that id signal is 1, represent current in sending mode.
That is to say, in the time that rec_tran signal is 0, illustrate currently in receiving mode, the first data selector 810 selects the output signal of cic filter front stage circuits as the input signal of cascade integrator; The second data selector 820 selects the output signal of cascade integrator as the input signal of abstraction module; The output signal of the 3rd data selector 830 selecting extraction modules is as the input signal of cascade comb filter; The 4th data selector 840 selects the output signal of cascade comb filter as the output signal of cic filter.
When rec_tran signal is 1, illustrate current in sending mode, the 3rd data selector 830 selects the output signal of cic filter front stage circuits as the input signal of cascade comb filter, the input signal that the output signal of cascade comb filter is interpolating module; The first data selector 810 selects the output signal of interpolating module as the input signal of cascade integrator; The 4th data selector 840 selects the output signal of cascade integrator as the output signal of cic filter.The second data selector 820 is selected the input signal of low level as abstraction module.
Third embodiment of the invention relates to a kind of filtering method of cic filter.In the present embodiment, utilize the first data selector, the second data selector, the 3rd data selector and the 4th data selector, realization is multiplexing to cascade integrator and cascade comb filter.Wherein, the first data selector, in the output signal of cic filter front stage circuits and the output signal of interpolating module, is selected a kind of input signal as cascade integrator; The second data selector, in the output signal and low level of cascade integrator, is selected a kind of input signal as abstraction module; The 3rd data selector, in the output signal of abstraction module and the output signal of cic filter front stage circuits, is selected a kind of input signal as cascade comb filter; The 4th data selector, in the output signal of cascade comb filter and the output signal of cascade integrator, is selected a kind of output signal as cic filter.The first data selector, the second data selector, the 3rd data selector and the 4th data selector, all, according to for representing the current id signal in reception or the state of transmission, select.In the present embodiment, take id signal as 0 o'clock, represent currently in sending mode, in the time that id signal is 1, representing current is example in receiving mode, is specifically described.
Idiographic flow as shown in figure 10, in step 1000, judges current mode of operation, if work at present at receiving mode, id signal is 1; If work at present is at sending mode, id signal is 0.
If id signal is 1, illustrate currently in receiving mode, the first data selector selects the output signal of cic filter front stage circuits as the input signal of cascade integrator, enters step 1001.If current in sending mode, if id signal is 0, illustrate currently in sending mode, the 3rd data selector selects the output signal of cic filter front stage circuits as the input signal of cascade comb filter, enters step 1007.
In step 1001, by cascade integrator, the output signal of cic filter front stage circuits is carried out to cascade integral processing.
Then, in step 1002, the second data selector selects the output signal of cascade integrator as the input signal of abstraction module, by abstraction module, the signal of cascade integrator output is extracted to sampling.The frequency conversion multiple of this abstraction module is R1.
Then,, in step 1003, the output signal of the 3rd data selector selecting extraction module, as the input signal of cascade comb filter, is carried out comb filtering processing by cascade comb filter to the signal of abstraction module output.
Then,, in step 1004, the 4th data selector selects the output signal of cascade comb filter as the output signal output of cic filter.The output signal of this cic filter, through a 1 tunnel-2 circuit-switched data distributor, is exported to the output signal of this cic filter by this 1 tunnel-2 circuit-switched data distributor the late-class circuit of CIC decimation filter.That is to say, under receiving mode (being that id signal is 1), this cic filter is equal to a CIC decimation filter, and the output signal of cic filter will be input to the late-class circuit of CIC decimation filter of the prior art so.
Then, in step 1005, judge whether to occur the switching between receiving mode and sending mode and/or needed Global reset, if there is pattern switching and/or needed Global reset, enter step 1006, cascade integrator, abstraction module, cascade comb filter and interpolating module are resetted, and enter step 1000 after reset.If emergence pattern does not switch and do not need Global reset yet, get back to step 1001.
In step 1007, by cascade comb filter, the output signal of cic filter front stage circuits is carried out to comb filtering processing.
Then, in step 1008, by interpolating module, the output signal of cascade comb filter is carried out to interpolation, the frequency conversion multiple of this interpolating module is R2.In the present embodiment, the frequency conversion multiple R1 of abstraction module can equal the frequency conversion multiple R2 of interpolating module, also can be not equal to the frequency conversion multiple R2 of interpolating module.
Then, in step 1009, the first data selector selects the output signal of interpolating module as the input signal of cascade integrator, by cascade integrator, the signal of interpolating module output is carried out to cascade integral processing.
Then,, in step 1010, the 4th data selector selects the output signal of cascade integrator as the output signal of cic filter.The second data selector is selected the input signal of low level as abstraction module.The output signal of this cic filter, through a 1 tunnel-2 circuit-switched data distributor, is exported to the output signal of this cic filter by this 1 tunnel-2 circuit-switched data distributor the late-class circuit of CIC interpolation filter.That is to say, under sending mode (being that id signal is 0), this cic filter is equal to a CIC interpolation filter, and the output signal of cic filter will be input to the late-class circuit of CIC interpolation filter of the prior art so.
Then, in step 1011, judge whether to occur the switching between receiving mode and sending mode and/or needed Global reset, if there is pattern switching and/or needed Global reset, enter step 1012, cascade integrator, abstraction module, cascade comb filter, interpolating module are resetted, and enter step 1000 after reset.If emergence pattern does not switch and do not need Global reset yet, get back to step 1007.
Be not difficult to find, present embodiment is the method execution mode corresponding with the first execution mode, present embodiment can with the enforcement of working in coordination of the first execution mode.The correlation technique details of mentioning in the first execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first execution mode.
Four embodiment of the invention relates to a kind of filtering method of cascade integral comb filter.The 4th execution mode and the 3rd execution mode are basic identical, and difference is mainly:
In the 3rd execution mode, id signal is 0 o'clock, represents currently in sending mode, in the time that id signal is 1, represents current in receiving mode.And in the present embodiment, id signal is 0 o'clock, represent currently in receiving mode, in the time that id signal is 1, represent current in sending mode.
Be not difficult to find, present embodiment is the method execution mode corresponding with the second execution mode, present embodiment can with the enforcement of working in coordination of the second execution mode.The correlation technique details of mentioning in the second execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the second execution mode.
It should be noted that, each method execution mode of the present invention all can be realized in modes such as software, hardware, firmwares.No matter the present invention realizes with software, hardware or firmware mode, instruction code can be stored in the memory of computer-accessible of any type (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium etc.).Equally, memory can be for example programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), read-only memory (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, be called for short " DVD ") etc.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and described, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
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| CN102780469B (en) * | 2012-08-16 | 2015-04-22 | 钜泉光电科技(上海)股份有限公司 | Cascade integrator comb filter and implementation method thereof |
| CN103078606B (en) * | 2012-12-28 | 2016-03-16 | 京信通信系统（中国）有限公司 | Multichannel CIC interpolation filter system and its implementation |
| CN106470022A (en) * | 2015-08-14 | 2017-03-01 | 中兴通讯股份有限公司 | A kind of filter circuit and method |
| CN107359868A (en) * | 2016-05-10 | 2017-11-17 | 深圳市中兴微电子技术有限公司 | Pulse density modulated change-over circuit and method |
| CN106209265B (en) * | 2016-06-24 | 2018-10-12 | 武汉虹信通信技术有限责任公司 | A kind of the band wave calibration method and device of broadband signal |
| KR101878651B1 (en) * | 2017-01-09 | 2018-07-16 | 주식회사 이노와이어리스 | CIC Filter Having an Improved Structure |
| CN106849904A (en) * | 2017-01-17 | 2017-06-13 | 广州致远电子股份有限公司 | Digital filtering equipment |
| CN114584108A (en) * | 2020-11-30 | 2022-06-03 | 深圳市中兴微电子技术有限公司 | Filter unit and filter array |
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|---|---|---|---|---|
| US5835390A (en) * | 1995-12-27 | 1998-11-10 | Asahi Kasei Microsystems Co., Ltd | Merged multi-stage comb filter with reduced operational requirements |
| CN1592103A (en) * | 2003-08-30 | 2005-03-09 | 华为技术有限公司 | N step half-band interpolating filter |
| CN101262240A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | A method and device for all-digital frequency conversion that is easy to realize by hardware |
-
2010
- 2010-11-19 CN CN201010554649.XA patent/CN102035503B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5835390A (en) * | 1995-12-27 | 1998-11-10 | Asahi Kasei Microsystems Co., Ltd | Merged multi-stage comb filter with reduced operational requirements |
| CN1592103A (en) * | 2003-08-30 | 2005-03-09 | 华为技术有限公司 | N step half-band interpolating filter |
| CN101262240A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | A method and device for all-digital frequency conversion that is easy to realize by hardware |
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