CN1592103A - N step half-band interpolating filter - Google Patents
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Abstract
This invention relates to N-stage interpolation filter which utilizes the adding of multiphase filtration with shift register string to save logic resource and simplifies a phase into the multiplication of only one data with one factor to further simplify it to a simple shift adder. The filter includes the following modules: a weight module, a shift register time delay module, an addition module, a look up module and a one from two selection module.
Description
Technical field
The present invention relates to semi-band filter, particularly based on the semi-band filter of leggy filtering.
Background technology
Interpolation is to replenish some data between discrete data, makes this group discrete data can meet certain continuous function.Interpolation is the most frequently used means and the method for fundamental sum in the Digital Signal Processing, for example, can realize the improvement of image definition in the image processing by interpolation.
In actual applications, the interpolation of digital signal, comparatively easy method are earlier digital signal to be carried out 0 interpolation, pass through low pass filter (Low Pass Filter is called for short " LPF ") then and obtain interpolated signal.For example, can be that the discrete signal of fs carries out following interpolation processing to sample rate: at first will insert 0 in the middle of per two centrifugal pumps, this moment, the discrete signal samples rate be a twice before the interpolation, was 2fs, and this is referred to as two times of interpolation; Signal after then the signal after 0 interpolation being obtained handling by corresponding low pass filter.
Filter has two kinds: finite impulse response (Finite Impulse Response is called for short " FIR ") filter and infinite impulse response (Infinite Impulse Response is called for short " IIR ") filter.Iir filter is used for tolerating the system of phase distortion, and the FIR filter then uses in the system of rock-steady structure in needing linear phase, possessing.Just because of this, the FIR filter has all been adopted in a lot of system designs.
The processing of digital signal interpolation needs linear phase usually, so the FIR filter is adopted in the processing of interpolated signal usually.Figure 1 shows that the FIR Filter Structures form that the N rank are traditional, in Fig. 1, device 11 expression shift registers, 12 expression multipliers, 13 expression adders.Wherein, shift register is realized with trigger usually.Input signal x (n) respectively by N coefficient h (0)～h (N-1) weighting, adds up as output after the N level postpones mutually again.The actual convolution algorithm of having finished input data and N coefficient of finite impulse response filter, the number N of coefficient is defined as filter order.Finite impulse response filter generally adopts the even symmetry coefficient in the real system, promptly satisfies h (i)=h (N-1-i), i=0～N-1, and exponent number N is generally odd number.
In the processing of two times of interpolation, half-band filter (Half Band Filter is called for short " HBF ") is more commonly used, and HBF is a kind of low-pass FIR filter that extensively uses in digital processing field, and its pass band width just in time equals half of its Nyquist territory.General field programmable gate array (Field Programmable Gate Array is called for short " FPGA ") or application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit is called for short " the ASIC ") logical circuit of adopting realized in the real system.Be used for two times of interpolation and be called semi-band filter with the half-band filter that improves signal sampling rate.Semi-band filter generally has following 4 essential characteristics:
Coefficient even symmetry h (i)=h (N-1-i), i=0～N-1;
Coefficient is that (other even number dot factors h (i) except that h (0) is 0 to sparse array, i=± 2,4 wherein, 6 ...);
Data are sparse array (data alternately be 0 and non-0 value);
Exponent number N is an odd number.
In FPGA or ASIC design, if directly the theory structure according to Fig. 1 introduction carries out logic realization, the parallel multiplication computing will consume a large amount of logical resources, therefore in the practical design, usually adopt following two kinds of technical schemes, be R with data input rate after the interpolation of two kinds of technical schemes below, filter order N is 15 and introduces two kinds of technical scheme schemes for example:
Technical scheme one:
Lookup table schemes, its principle is constant for the coefficient that utilize to participate in multiplying, by in advance the various possible outcomes of data and multiplication being stored in the method in the look-up table (Look Up Table, abbreviation " LUT "), avoids the complicated and parallel multiplying.Fig. 2 is that example has illustrated that LUT look-up table method realizes filter with 15 rank.Wherein device 21 is a shift register, and device 22 is a look-up table, and device 23 is an adder.
Consider the design feature of FPGA or ASIC, usually it is 1 group with per 4 taps, 1 bit of data is taken out in each tap, all 16 kinds of possible outcomes of 4 tap data of totally 4 bits and 4 coefficient weighted sums are stored in the look-up table in advance, can calculate the local filtering result of 4 taps like this by simple lookup.The output of look-up table is by the corresponding input Data Control of this table, and a lookup result is exported in corresponding every group of input.If data are many bits bit wide, every group of look-up table need walk abreast or calculate the local filtering result of all bits serially, and shifter-adder all look-up table results added, obtains filter and finally exports again together again.
For 15 rank filters, need 4 groups of look-up tables.Shift register needs 15 grades, is operated on the input data transmission rate R, and data of promptly every input need be shifted once.
The number of shift register stages of this technical scheme is N, and the operating rate of shift register is R, and the quantity of look-up table is [N/4], and the operating rate of look-up table is R.Wherein [] expression is to big several direction rounding operations.
Technical scheme two:
This scheme is called the leggy filters solutions, is a kind of improvement project of scheme one, discloses this scheme in application number is 00125310 Chinese patent application " digital shaping filter in the Wideband Code Division Multiple Access (WCDMA) communication system ".Sampling point in the every interval of input data of considering semi-band filter has one to be 0, and the therefore multiplying that can omit 0 data and coefficient only is input to shift register with non-0 data.Such one is that shift register only needs half resource, the 2nd, and the LUT of same quantity table can parallel computation goes out the output result of 2 sampling points, has improved operation efficiency.
Fig. 3 is the realization that example has illustrated leggy filtering semi-band filter with 15 rank.Two times of 0 discrete series before the interpolation carried out in X among the figure (n) expression.Wherein device 31 is a shift register, and device 32 is a look-up table, and device 33 is an adder, and device 34 is the alternative selector.In this scheme, only non-zero is moved into shift register, data per two are clapped and once are shifted, and the speed that promptly is shifted is R/2, and wherein R is the data rate after the interpolation.Every displacement once, have the parallel LUT table logical block of two covers (being called the LUT table of phase place 1 and phase place 2 correspondences) respectively calculated data and even-numbered coefficient weighted sum and with the weighted sum of odd-numbered coefficient, select 1 selector basis phase place at that time to export the filtering result of two phase places in turn with 2 at last.Here " phase place " is meant the diverse location that data move in the shift register, and then phase change is once also can to regard centrifugal pump of the every output of filter output sequence as.
For example, the computing formula of the output y (n) of 15 rank FIR filters is:
y(n)＝x(n)h(0)+x(n-1)h(1)+……+x(n-14)h(14)，
If x (0) is a nonzero value, promptly the discrete data of the even-numbered among the x (n) is the data of the discrete series before the interpolation, and the discrete data of the technology numbering among the x (n) is 0 value that interpolation is inserted.Suppose that phase place 1 is the output of n when being even number, phase place 2 is the output of n when being odd number.The look-up table group LUT (0) of phase place 1 and LUT (2) are the corresponding look-up table that is designated as the weight coefficient h (n) of even number down, look-up table LUT (0) is the look-up table of h (0), h (2), h (4) and h (6) for weight coefficient, and look-up table LUT (2) is the look-up table of h (8), h (10), h (12) and h (14) for weight coefficient; The look-up table group LUT (1) of phase place 2 and LUT (3) are the corresponding look-up table that is designated as the weight coefficient h (n) of odd number down, look-up table LUT (1) is the look-up table of h (1), h (3), h (5) and h (7) for weight coefficient, and look-up table LUT (3) is the look-up table of h (9), h (11) and h (13) for weight coefficient.Work as n=M, when M was even number, be phase place 1 this moment, since the existence of 0 value in the data, y (M)=x (M) h (0)+x (M-2) h (2)+... x (M-N+1) h (N-1) selects the results added output of the LUT table group of phase place 1 as can be seen this moment.Can reason out equally and work as n=M, when M is odd number, select the results added output of the LUT table group of phase place 2.
The number of shift register stages of this technical scheme is (N+1)/2, and the operating rate of shift register is R/2, and the quantity of look-up table is [N/4], and the operating rate of look-up table is R/2.Wherein [] expression is to big several direction rounding operations.
In actual applications, there is following problem in such scheme: two kinds of schemes all need to consume more system resources and power consumption, have increased the cost of system.For each technical scheme, the number of shift register stages of the lookup table schemes of technical scheme one and LUT table quantity are more, and operating rate is higher, is unfavorable for logic serialization stream treatment respectively; Though the leggy filters solutions of technical scheme two has reduced the quantity of shift register, reduced the operating rate of working shift register and look-up table, consumption of natural resource is still more.
Cause a main cause of this situation to be, existing two schemes all do not make full use of the characteristics such as coefficient even symmetry, many zero-sums of coefficient data many zero of semi-band filter when the logic realization of the circuit of semi-band filter, cause look-up table quantity more, system power dissipation is more, resource consumption is more, thereby further cause when realizing with FPGA, resource utilization is low, and chip area is big when realizing with ASIC, cost is higher.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of N rank semi-band filter, makes the employed logical resource of this filter significantly reduce, and power consumption reduces.
In order to solve the problems of the technologies described above, the invention provides a kind of N rank semi-band filter, comprise shift register time delay module, look-up table means and selector module, wherein said shift register time delay module is used for (N+1)/2 data before the sequence interpolation of input are carried out shift LD; Described look-up table means is used to calculate the result behind input value and the corresponding filter coefficient weighting summation; Described selector module is used for selecting the output of corresponding input data according to different phase places, and described system also comprises:
Addition module is used for the addition of turning back of will dividing into groups from the serial data of described shift register time delay module input;
Weighting block is used for the data of input are computed weighted; And,
Described shift register time delay module, described addition module, described look-up table means and described selector module are connected successively, are used for the data processing of first phase place;
Described shift register time delay module, described weighting block and described selector module are connected successively, are used for the data processing of second phase place.
Wherein, described shift register time delay module is made of (N+1)/2+1 d type flip flop, wherein (N+1)/2 d type flip flop is connected in series successively, is used to preserve (N+1)/2 data of the described shift register time delay module of nearest input, and these data are outputed to described look-up table means; One in another one d type flip flop and described (N+1)/2 d type flip flop connected in series successively is connected, is used to preserve [(N+1)/4]+1 data of the described shift register time delay module of nearest input, and these data are outputed to described weighting block.
Described weighting block is the displacement adder.
Described look-up table means comprises the look-up table that stores the result that institute might obtain behind input value and the corresponding filter coefficient weighting summation, and described look-up table means is directly found out corresponding operation result according to described input value and exported in described look-up table.
Described selector module comprises the selector of an alternative, its input connects the output of described look-up table means and described weighting block respectively, be used for when first phase place, exporting the output valve of described look-up table means, when second phase place, export the output valve of described weighting block.
By relatively finding, technical scheme difference with the prior art of the present invention is, it is that sparse array, data are that sparse array and exponent number N are 4 essential characteristics of odd number that this programme has made full use of semi-band filter coefficient even symmetry, coefficient, the turn back method of addition of employing reduces the number of look-up table, a phase place in leggy filtering replaces multiplier with multistage shifter-adder, make logical resource that semi-band filter uses still less, power consumption is lower.
Difference on this technical scheme, brought comparatively significantly beneficial effect, it is N level semi-band filter, data rate after the interpolation of input is under the situation of R, if with technical scheme one, the operating rate of shift register and look-up table is R, and number of shift register stages is N, and the quantity of look-up table is [N/4]; If with technical scheme two, the operating rate of shift register and look-up table is R/2, and number of shift register stages is (N+1)/2, and the quantity of look-up table is [N/4]; And utilize this programme, the operating rate of shift register and look-up table is R/2, and number of shift register stages is (N+1)/2+1, and the quantity of look-up table is [[N/4]/4].Wherein [] expression is to big several direction rounding operations.Therefore the present invention effectively reduced the logical resource that system consumed, thereby can reduce the power consumption of system, and operating rate is lower thereby make system easier of the multiplexing further minimizing resource of serialization flowing water.Practice result shows that it is over half that the present invention program can save logical resource.
Description of drawings
Fig. 1 is the traditional FIR Filter Structures schematic diagrames in N rank;
Fig. 2 is the schematic diagram that 15 rank look-up table methods realize semi-band filter;
Fig. 3 is the schematic diagram that 15 rank leggy filtering realize semi-band filter;
Fig. 4 is the schematic diagram of semi-band filter according to an embodiment of the invention;
Fig. 5 is the schematic diagram of the multistage displacement adder in the semi-band filter according to an embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
The present invention is the improvement project on background technology scheme two bases.This programme makes full use of semi-band filter coefficient even symmetry, coefficient is that sparse array, data are that sparse array and exponent number N are 4 essential characteristics of odd number, reaches the purpose of effective saving logical resource by circuit logic more cleverly.
The total design of this programme comprises following key technology point:
1. according to the characteristics of semi-band filter coefficient even symmetry, with the shift register addition of turning back, promptly will adding up earlier with the data that same factor multiplies each other in the shift register, with the table look-up number of times of computing of minimizing.
2. according to many zero the characteristics of semi-band filter coefficient, a phase place in the leggy filtering is reduced to simple adder, like this look-up table logic is reduced to a phase place.
Below in conjunction with a specific embodiment of the present invention, the present invention program is described.
The semi-band filter exponent number of this embodiment is 15, its logic realization principle such as Fig. 4.The discrete series before 0 interpolation is carried out in X among the figure (n) expression.This system comprises with lower module: shift register time delay module 40, addition module 50, look-up table means 60, weighting block 70 and alternative selector module 80.Wherein shift register time delay module 40 is made up of (N+1)/2+1 identical submodule shift register 41, and wherein N is the exponent number of semi-band filter.Addition module 50 is made up of several same submodule adder 51.
Weighting block 70 is responsible for the data of input are computed weighted, and the result after the weighting is outputed to the selective output of data input pin of alternative selector module 80.Its weight coefficient is the h ((N-1)/2) of N rank semi-band filter.Can realize with multiplier or multistage displacement adder.Realize with multistage displacement adder among this embodiment.The output of weighting block 70 is imported into alternative selector module 80.
The nonzero value of shift register time delay module 40 input interpolating sequences, promptly the data before the sequence interpolation are shifted once every 2 beats, and wherein each beat is the data input beat after the interpolation.Shift register time delay module 40 provides the tap of the output of each submodule shift register 41 to export for data simultaneously.For example, in the present embodiment, be in the middle data of shift register string and will import weighting block 70 as the input data.
Series of discrete value before the interpolation that addition module 50 inputs obtain from the tap of shift register time delay module 40.Corresponding to each submodule in the addition module 50, the data of input all are the data that will multiply each other with same factor.The dateout of addition module 50 is imported into look-up table means 60.
Store all possible outcomes of good related data of calculated in advance and corresponding filter coefficient weighting summation in the look-up table means 60, and select a data input that outputs to alternative selector module 80 of look-up table data according to the output result of addition module 50.In this programme, this module stores after the data addition that will multiply each other with identical filter coefficient with all possible outcomes of filter coefficient weighting summation, the non-zero before the interpolation after the addition of promptly turning back and all possible outcomes of filter coefficient weighting summation.This module has different implementations according to different circuit design in actual applications, and it comes down to a storage matrix, exports as the corresponding storage matrix node of address choice according to the data of input.The result of calculation of look-up table means 60 is imported into alternative selector module 80.
Alternative selector module 80 is responsible for selecting the output of corresponding input data according to different phase places.For example phase place 1 corresponding nonzero value and the filter weight multiplication of non-zero and the situation of addition are then selected the dateout output of look-up table means 60 during phase place 1; The situation of middle weight coefficient h ((N-1)/2) weighting of non-zero and filter in the middle of phase place 2 correspondences have only then selects the dateout of weighting block 70 to export during phase place 2.
The method of the addition of turning back has been adopted in this invention, promptly will adding up earlier with the data that same factor multiplies each other in the shift register, with the table look-up number of times of computing of minimizing.Because shift register is turned back after the addition generally speaking, possible 0 data and non-0 data addition, can destroy the original sparse characteristic of data, make leggy filtering not realize, so do not see in the prior art and in leggy filtering implementation, carry out the turn back method of addition of shift register simultaneously.But the interpolation rate of semi-band filter is 2, just in time 0 data and 0 data addition of two parts shift register data about this particularity makes, and non-0 data and non-0 data addition have still kept the original sparse characteristic of data.With 15 rank semi-band filters is that example is owing to the sequence of exporting after the filtering is
y(n)＝x(n)h(0)+x(n-1)h(1)+……+x(n-14)h(14)
Because the even symmetry characteristic of the sparse h of filter (n),
h(i)＝h(N-1-i)?i＝0～N-1
So
y(n)＝[x(n)+x(n-14)]h(0)+[x(n-1)+x(n-13)]h(1)+……[x(n-6)+x(n-8)]h(6)+x(n-7)h(7)。
Wherein the sequence after every promptly can turn back addition and the addition in the bracket still satisfies the characteristic of sparse array, thereby can use the method for leggy filtering, simultaneously owing to the total way that has reduced the input data of look-up table after the addition of turning back, the therefore number of having saved look-up table.
Each module that the following describes this embodiment is how to realize half band filtering interpolation, for easy, is that 9 semi-band filter is an example with exponent number:
Suppose that the data after the interpolation of input are X (0), 0, X (1), 0, X (2), 0, X (3) ..., also can be write as x (0), 0, x (2), 0, x (4), 0, x (6) ...As input x (n), when n is odd number phase place 1, n is a phase place 2 when being even number.H (n) is the impulse response of semi-band filter, also is weighted value, satisfies the characteristics of even symmetry and sparse array characteristics by the coefficient h (n) of semi-band filter, and they are followed successively by 0, h (1), 0, h (3), h (4), h (5), 0, h (7), 0.
Because output
y(n)＝x(n)h(0)+x(n-1)h(1)+……+x(n-8)h(8)
Because the sparse array characteristics of the coefficient h (n) of semi-band filter,
y(n)＝x(n-1)h(1)+x(n-3)h(3)+x(n-4)h(4)+x(n-5)h(5)+x(n-7)h(7)。
In phase place 1, when promptly n was odd number, shift register time delay module 40 was failure to actuate, and promptly shift register is not shifted.Because when n is odd number, x (n) is 0, so,
y(n)＝x(n-1)h(1)+x(n-3)h(3)+x(n-5)h(5)+x(n-7)h(7)。
Adopt this moment the method for look-up table to select corresponding data output in the look-up table means 60, alternative selector 80 is selected the dateout output of look-up table means 60 when phase place 1, be n when being odd number filtering export y (n).
Become in 2 in phase place, when promptly n is even number, shift register time delay module 40 action, with non-zero be before the interpolation data X (n) displacement once.Because when n is odd number, x (n) is 0, so y (n)=x (n-4) h (4).Weighting block 50 is weighted x (n-4), and alternative selector module 80 is selected the dateout output of weighting block 70 when phase place 2, is n filtering output y (n) when being even number.
The weighting block 70 of present embodiment adopts multistage displacement adder to realize, as Fig. 5.Wherein module 71 is a shift unit, and this module is the data bit that moves to left of input, and the data bit that moves to left is equaled to take advantage of 2; Module 72 is an adder.Realize multiplication by multistage shifter-adder.The progression of multistage adder and shift unit depends on the multiplier that multiplies each other.For example the multiplier that will take advantage of is 7, and the numerical value of the bit that then data moved to left adds that the numerical value of the dibit that moves to left adds do not have the numerical value of displacement can obtain the result.
Though by reference some preferred embodiment of the present invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that, can do various changes to it in the form and details, and the spirit and scope of the present invention that do not depart from appended claims and limited.
Claims (5)
1. a N rank semi-band filter comprises shift register time delay module, look-up table means and selector module, wherein
Described shift register time delay module is used for (N+1)/2 data before the sequence interpolation of input are carried out shift LD;
Described look-up table means is used to calculate the result behind input value and the corresponding filter coefficient weighting summation;
Described selector module is used for selecting the output of corresponding input data according to different phase places,
It is characterized in that described system also comprises:
Addition module is used for the addition of turning back of will dividing into groups from the serial data of described shift register time delay module input;
Weighting block is used for the data of input are computed weighted; And,
Described shift register time delay module, described addition module, described look-up table means and described selector module are connected successively, are used for the data processing of first phase place;
Described shift register time delay module, described weighting block and described selector module are connected successively, are used for the data processing of second phase place.
2. N according to claim 1 rank semi-band filter is characterized in that,
Described shift register time delay module is made of (N+1)/2+1 d type flip flop, wherein
(N+1)/2 a d type flip flop is connected in series successively, is used to preserve (N+1)/2 data of the described shift register time delay module of nearest input, and these data are outputed to described look-up table means;
One in another d type flip flop and described (N+1)/2 d type flip flop connected in series successively is connected, is used to preserve [(N+1)/4]+1 data of the described shift register time delay module of nearest input, and these data are outputed to described weighting block.
3. N according to claim 1 rank semi-band filter is characterized in that, described weighting block is the displacement adder.
4. N according to claim 1 rank semi-band filter, it is characterized in that, described look-up table means comprises a look-up table, wherein store the result that institute might obtain behind input value and the corresponding filter coefficient weighting summation, described look-up table means is directly found out corresponding operation result according to described input value and is exported in described look-up table.
5. N according to claim 1 rank semi-band filter, it is characterized in that, described selector module comprises the selector of an alternative, its input connects the output of described look-up table means and described weighting block respectively, be used for when first phase place, exporting the output valve of described look-up table means, when second phase place, export the output valve of described weighting block.
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| CN100463457C (en) * | 2005-06-16 | 2009-02-18 | 中兴通讯股份有限公司 | Multi-channel multiplexing cascade integrating comb filter |
| CN101442297B (en) * | 2007-11-23 | 2011-06-08 | 深圳Tcl工业研究院有限公司 | Digital decimation filter |
| CN102035503A (en) * | 2010-11-19 | 2011-04-27 | 钜泉光电科技(上海)股份有限公司 | Filtering device and filtering method of cascaded integral comb filter |
| CN102035503B (en) * | 2010-11-19 | 2014-05-28 | 钜泉光电科技(上海)股份有限公司 | Filtering device and filtering method of cascaded integral comb filter |
| CN102928031A (en) * | 2012-11-08 | 2013-02-13 | 昆山北极光电子科技有限公司 | Quick measurement method of dynamic flow |
| CN105846794B (en) * | 2016-03-24 | 2018-12-18 | 中国人民解放军国防科学技术大学 | A kind of interpolation FIR filter achieving method stopping control bit with starting |
| CN105846794A (en) * | 2016-03-24 | 2016-08-10 | 中国人民解放军国防科学技术大学 | Interpolated FIR filtering realizing method with starting and stopping control bit |
| CN108270416A (en) * | 2016-12-30 | 2018-07-10 | 北京圣非凡电子系统技术开发有限公司 | A kind of high-order interpolation wave filter and method |
| CN106897020A (en) * | 2017-01-13 | 2017-06-27 | 深圳市鼎阳科技有限公司 | A kind of data signal fixes the linear interpolation method and device of interpolation multiple |
| CN108631752A (en) * | 2017-03-16 | 2018-10-09 | 航天信息股份有限公司 | Forming filter and its manufacturing process |
| CN108631752B (en) * | 2017-03-16 | 2021-12-24 | 航天信息股份有限公司 | Shaping filter and shaping method thereof |
| CN111510110A (en) * | 2020-04-30 | 2020-08-07 | 上海大学 | Interpolation matched filtering method and filter for parallel processing |
| CN111510110B (en) * | 2020-04-30 | 2023-10-20 | 上海大学 | Interpolation matched filtering method and filter for parallel processing |
| CN111988018A (en) * | 2020-08-31 | 2020-11-24 | 中国电子科技集团公司第五十八研究所 | Automatic generation method for RTL model of half-band interpolation filter |
| CN111988018B (en) * | 2020-08-31 | 2022-08-16 | 中国电子科技集团公司第五十八研究所 | Automatic generation method for RTL model of half-band interpolation filter |
| CN112187215A (en) * | 2020-10-16 | 2021-01-05 | 中国电子科技集团公司第五十八研究所 | Cascaded half-band interpolation filter structure |
| CN116132232A (en) * | 2021-11-15 | 2023-05-16 | 西安电子科技大学 | Multipath parallel up-sampling method for high-speed digital communication |
| CN116132232B (en) * | 2021-11-15 | 2024-04-19 | 西安电子科技大学 | Multipath parallel up-sampling method for high-speed digital communication |
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