CN111988018B - Automatic generation method for RTL model of half-band interpolation filter - Google Patents
Automatic generation method for RTL model of half-band interpolation filter Download PDFInfo
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Abstract
The invention discloses an automatic generation method of a half-band interpolation filter RTL model, and belongs to the field of digital filters. The RTL model generator reads the configuration information of the filter from the files coefficient.txt and parameter _ input.txt, calculates all parameters of the filter component model, and stores the generated parameters in the file parameter _ output.txt; the RTL model generator reads the filter coefficient file, and generates RTL models of all filter components according to the parameters of the filter component model calculated in the step 1; and capturing an RTL source code, printing a testbench file, and generating a test environment.
Description
Technical Field
The invention relates to the technical field of digital filters, in particular to an automatic generation method of a half-band interpolation filter RTL model.
Background
In a signal transmission system, a baseband signal generally needs to be up-converted to an intermediate frequency band in a DUC module, and the DUC module includes three steps of interpolation, filtering and mixing. A half-band interpolation filter (half band interpolator) can perform filtering while interpolating; in addition, as the coefficient is close to half of zero, the method can greatly reduce the calculation amount compared with a common filter, ensure the calculation precision and function, and reduce the hardware overhead and save the power consumption. Due to the characteristics, the half-band interpolation filter is widely applied to the DAC.
For a high-speed DAC, the calculation rate of the interpolation filter can reach or even exceed 1Ghz, and the interpolation filter is usually realized by adopting a multi-path parallel mode. In addition, complex multiply-add operations require the insertion of multi-stage pipeline structures. Therefore, the high-speed half-band interpolation filter needs to comprehensively consider the problems of parallel processing, interpolation operation, design of a pipeline structure and the like, and common developers are difficult to complete design verification work in a short time.
Disclosure of Invention
The invention aims to provide an automatic generation method of a RTL (real time modeling) model of a half-band interpolation filter, which aims to solve the problems of complex design process and long development period of the conventional high half-band interpolation filter.
In order to solve the technical problem, the invention provides an automatic generation method of a half-band interpolation filter RTL model, which comprises the following steps:
and 3, capturing an RTL source code, printing a testbench file, and generating a test environment.
Txt is a filter coefficient file, which contains all fixed-point coefficients of the half-band filter, but does not contain 0 coefficient;
the file parameter _ input.txt is a filter configuration file and comprises a filter input data bit width, an output data bit width, a fixed point coefficient bit width and a filter length; the filter length L satisfies L4N +3, and is centrosymmetric, wherein N is a non-negative integer;
all parameters of the filter component model comprise the addition pipeline stage number, the delay period number, the adder bit width, the multiplier bit width, the truncation width and all information in the filter configuration file parameter _ input.
Optionally, the specific steps in step 1 are:
step 1.1, reading all information in the file parameter _ input.txt, storing the information in an array parameter _ in _ array, and removing invalid information in the array parameter _ in _ array; respectively storing the bit width of input data, the bit width of output data, the bit width of a fixed point coefficient and the length of a filter in variables data _ in _ width, data _ out _ width, coeffient _ width and filter _ length;
step 1.2, calculating the number of required multipliers product _ num, and calculating the number of required addition pipeline stages sum _ stage according to the number of the multipliers; calculating delay cycle delay _ cycle required by a delay unit according to the length of the filter; calculating the bit width adder _ width of the adder; calculating the bit width product _ width of the multiplier; calculating truncation width structation _ width;
step 1.3, firstly, all the parameter _ in _ array groups in step 1.1 are printed into a file parameter _ output.txt; all the parameters calculated in step 1.2 are then printed to the file parameter _ output.
Optionally, the RTL model generator includes a parameter calculation module, a delay unit generator, an addition unit generator, a multiplication unit generator, a summation unit generator, an overflow processing unit generator, a single-channel unit generator, and a top-level unit generator.
Optionally, the specific steps of generating the RTL model in step 2 are:
step 2.1, operating a delay unit generator to generate a delay module hbfir _ delay, and printing the delay module hbfir _ delay in a file hbfir _ delay.v;
step 2.2, operating the addition unit generator to generate an addition module hbfir _ order, and printing the addition module hbfir _ order in a file hbfir _ order.v;
step 2.3, operating the multiplication unit generator, generating a multiplication module hbfir _ mult, and printing the multiplication module hbfir _ mult in a file hbfir _ mult.v;
step 2.4, operating the summation unit generator to generate an addition module hbfir _ sum, and printing the addition module hbfir _ sum in a file hbfir _ sum.v;
step 2.5, operating an overflow processing unit generator, generating an overflow processing module hbfir _ overflow _ handle, and printing the overflow processing module hbfir _ overflow _ handle.v in a file hbfir _ overflow _ handle.v;
step 2.6, operating the single-channel unit generator to generate a single-channel module hbfir _ sign _ channel, and printing the single-channel module hbfir _ sign _ channel in a file hbfir _ sign _ channel.v; the method comprises the following steps that single channels respectively instantiate submodels of hbfir _ adder, hbfir _ mult, hbfir _ sum and hbfir _ overlay _ handle, wherein the instantiations are u _ hbfir _ adder, u _ hbfir _ mult, u _ hbfir _ sum and u _ hbfir _ overlay _ handle;
step 2.7, operating a top-level unit generator, generating a top-level model of the half-band filter, and printing the top-level model in a file hbfir _ top.v; the top-level unit instantiates two hbfir _ sign _ channel modules, wherein the instantiations are hbfir _ sign _ channel _ odd and hbfir _ sign _ channel _ even respectively; the top unit instantiates a delay module hbfir _ delay at the same time.
Optionally, the step 2.1 includes:
step 2.1.1, reading the input data bit width data _ in _ width and the delay cycle delay _ cycle in the file parameter _ output.txt;
step 2.1.2, printing input and output signals: the input signals are clk, din _ n _0, din _ n _2, respectively; the output signals are din _ n _4, din _ n _6, din _ n _8 and din _ n _10 …; the output has 2 × delay _ cycle;
step 2.1.3, print always timing architecture produces all output signals, where din _ n _4, din _ n _8, din _ n _12 … are produced by din _ n _0 delay, and din _ n _6, din _ n _10, din _ n _14 … are produced by din _ n _2 delay.
Optionally, step 2.2 specifically includes:
step 2.2.1, reading the input data bit width data _ in _ width and the filter length filter _ length in the file parameter _ output.txt;
step 2.2.2, printing input and output signals: the input clock signal is clk; there are (filter _ length +1)/2 input data signals, which are din _ n _0, din _ n _2, din _ n _4, and din _ n _6 … …; the output signals are (filter _ length +1)/4, and are respectively an address _00, an address _02 and an address _04 … …;
and 2.2.3, printing an always time sequence structure to generate all output signals, processing input and output according to signed numbers, and adding the output signals into delay data corresponding to a half-band folding structure.
Optionally, the step 2.3 includes:
step 2.3.1, reading the adder bit width adder _ width, the filter length filter _ length and the fixed point coefficient bit width coeffient _ width of the filter in the file parameter _ output.txt; reading the filter fixed point coefficient in the file coefficient.
Step 2.3.2, printing input and output signals: the input clock signal is clk; there are (filter _ length +1)/4 input data signals, which are respectively the adder _00, the adder _02 and the adder _04 … …; the output signals are also (filter _ length +1)/4, which are mult _ h00, mult _ h02 and mult _ h04 … … respectively;
step 2.3.3, printing filter coefficients (filter _ length +1)/4 in total; the coefficients are all defined as signed numbers, the bit width is coefficient _ width, and the coefficients are h00, h02 and h04 … … respectively;
and 2.3.4, printing an always time sequence structure to generate all output signals, processing input and output according to signed numbers, and taking the value of the output signal as the product of the coefficient of the corresponding half-band filter and the adder.
Optionally, the step 2.4 includes:
step 2.4.1, reading multiplier bit width product _ width, filter length filter _ length, truncation length trunk _ width and addition pipeline stage number sum _ stage in file parameter _ output.txt;
step 2.4.2, printing an input and output signal, wherein the input clock signal is clk; the number of input signals is (filter _ length +1)/4, which are respectively mult _ h00, mult _ h02 and mult _ h04 … …, and the output signal is sum;
step 2.4.3, printing adders according to the number of stages of an adder assembly line, wherein each adder only adds two data; the number of adders of each stage is 2^ (sum _ stage-1), 2^ (sum _ stage-2) … … until the adder of the last stage is only a single adder; the first-stage adder adds the input signals mult _ h00, mult _ h02 and mult _ h04 … …, and if the input data is not enough than 2^ sum _ stage, the input signals are filled with 0;
and 2.4.4, truncating and outputting the calculation result of the last-stage adder in the step 2.4.3.
Optionally, step 2.7 includes:
step 2.7.1, calculating a delay beat, and connecting corresponding values from the output port of the delay module hbfir _ delay generated in the step 2.1 to be used as two-phase outputs dout _ n _0 and dout _ n _ 2;
step 2.7.2, instantiating the delay module hbfir _ delay generated in the step 2.1 to u _ hbfir _ delay; instantiating the two single-channel modules hbfir _ single _ channel generated in step 2.6, which are hbfir _ single _ channel _ odd and hbfir _ single _ channel _ even respectively, and corresponding outputs are dout _ n _1 and dout _ n _3 respectively.
Optionally, step 3 includes:
step 3.1, opening the fh _ tb file operation handle, pointing to the new file tb _ hbfir _ top.v, and loading testbench codes printed in the subsequent step; capturing RTL source codes, and identifying input output signals and bit widths thereof;
step 3.2, printing a file header, wherein the name of the module is tb _ hbfir;
step 3.3, printing reg and wire corresponding to input and output;
step 3.4, printing an initial module, and assigning initial values to all reg type variables as 0;
step 3.5, printing a clock module to generate a clock signal clk;
step 3.6, opening a file operation handle fh _ case to point to a new file CASe0.v; printing a test case to a file CASE0.v, wherein the test case comprises a random number excitation generation and reset signal rst jump signal;
step 3.7, printing a waveform saving command to a file CASE0.v; automatically selecting and saving waveform verilog syntax according to input parameters of Design _ Auto _ Gen _ TB _ v2.3.pl, saving the shm format waveform if the input parameters of the parameters are 0, and saving the fsdb format waveform if the parameters are 1; closing the file operation handle fh _ case;
step 3.8, instantiating a printing filter;
step 3.9, printing a simulation configuration environment file list.f and a run, wherein the list.f is a simulation file directory, and the run is a simulation operation command; automatically selecting a simulator grammar according to input parameters of Design _ Auto _ Gen _ TB _ v2.3.pl, if the parameter input parameters are 0, using NC _ verilog simulation, and if the parameter input parameters are not 1, using VCS simulation;
step 3.10, newly creating directories tb, dc, format, CASE, waveform, data _ in and data _ out; move list.f, run and tb _ hbfir.v under the tb folder; CASe0.v moves under the CASE directory.
In the method for automatically generating the RTL model of the half-band interpolation filter, the RTL model generator reads the configuration information of the filter from a file coefficient.txt and a parameter _ input.txt, calculates all parameters of a filter component model, and stores the generated parameters in the file parameter _ output.txt; the RTL model generator reads the filter coefficient file, and generates RTL models of all filter components according to the parameters of the filter component model calculated in the step 1; and capturing an RTL source code, printing a testbench file, and generating a test environment. The method avoids the problems of long design and debugging period and high difficulty of the high-speed half-band filter code, and realizes the automatic generation of the RTL model design and the verification code in the development process.
Drawings
FIG. 1 is a program architecture;
figure 2 is the content of the coefficient.
Fig. 3 is the parameter _ input.txt file content in the embodiment;
fig. 4 is the parameter _ output.txt content generated in the running process in the embodiment;
FIG. 5 is a half-band filter RTL model architecture generated by an RTL model generator;
FIG. 6 is a hierarchical view of a Verdi file after a program is run;
FIG. 7 is the Makefile file contents;
FIG. 8 is a file tree structure before program execution;
fig. 9 is a file tree structure after the program is run.
Detailed Description
The following describes in detail an automatic generation method of a half-band interpolation filter RTL model according to the present invention with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides an automatic generation method of a half-band interpolation filter RTL model, and a program architecture is shown in figure 1.
The method specifically comprises the following steps:
step 1.1, reading all information in the file parameter _ input.txt, storing the information in an array parameter _ in _ array, and removing invalid information in the array parameter _ in _ array; respectively storing the bit width of input data, the bit width of output data, the bit width of a fixed point coefficient and the length of a filter in variables data _ in _ width, data _ out _ width, coeffient _ width and filter _ length;
step 1.2, calculating the number of required multipliers product _ num ═ (filter _ length +1)/4 ═ 3, and calculating the number of required addition pipeline stages sum _ stage ═ 2 according to the number of multipliers; calculating the delay period number delay _ cycle which is 8 needed by the delay unit according to the length of the filter; calculating the bit width addder _ width ═ data _ in _ width +1 ═ 17 of the adder; calculating a multiplier bit width product _ width ═ data _ in _ width + coeffient _ width ═ 28; calculating an intercept width of (11) — product _ width-data _ out _ width-1;
step 1.3, firstly, all the parameter _ in _ array groups in step 1.1 are printed into a file parameter _ output.txt; namely:
data_in_wide:16
data_out_wide:16
coefficient_wide:12
filter_length:11。
all the parameters calculated in step 1.2 are then printed to the file parameter _ output.txt, i.e.:
sum_stage:2
delay_cycle:8
adder_width:17
product_width:28
truncation_width:11。
fig. 2 is a diagram illustrating a file coefficient. txt sequentially storing N +2 fixed-point coefficients other than 0, where the coefficients in fig. 2 are 29 to 214,1209,2048, and all corresponding coefficients of the half-band filter are 29,0 to 214,0,1209,2048,1209,0 to 214,0, 29; fig. 3 is the content of parameter _ input.txt in the embodiment of the present invention, wherein:
"data _ in _ wide: 16" indicates that the configuration input bit width is 16 bits;
"data _ out _ wide: 16" indicates that the configuration output bit width is 16 bits;
"coefficient _ wide: 12" indicates that the fixed point coefficient bit width is 12 bits;
"filter _ length: 11" indicates a filter length of 11.
All parameters of the filter component model comprise the addition pipeline stage number, the delay period number, the adder bit width, the multiplier bit width, the truncation width and all information in the filter configuration file parameter _ input.
Fig. 4 is the parameter _ output.txt content generated during the run in the embodiment. Wherein:
"data _ in _ wide: 16" indicates that the configuration input bit width is 16 bits;
"data _ out _ wide: 16" indicates that the configuration output bit width is 16 bits;
"coefficient _ wide: 12" indicates that the fixed point coefficient bit width is 12 bits;
"filter _ length: 11" indicates a filter length of 11;
"sum _ stage: 2" indicates that the summation unit generator (hbfir _ sum _ gen.pl) requires two stages of running water calculation addition;
"delay _ cycle: 8" indicates that the delay unit generator (hbfir _ delay _ gen.pl) is delayed by 8 cycles;
"adder _ width: 17" indicates that the bit width of the output data of the addition unit generator (hbfir _ adder _ gen.pl) is 17 bits;
"product _ width: 28" indicates that the multiplication bit width output by the multiplication unit generator (hbfir _ mult _ gen.pl) is 28 bits;
"truncation _ width: 11" indicates that the sum unit generator (hbfir _ sum _ gen.pl) needs to truncate 11 bits of data at the final output.
step 2.1, running a delay unit generator (hbfir _ delay _ gen.pl), generating a delay module hbfir _ delay, and printing the delay module hbfir _ delay.v in a file hbfir _ delay.v;
the step 2.1 is specifically as follows:
step 2.1.1, reading an input data bit width data _ in _ width of a file parameter _ output.txt as 17 and a delay cycle delay _ cycle;
step 2.1.2, printing input and output signals: the input signals are clk, din _ n _0, din _ n _2, respectively; the output signals are din _ n _4, din _ n _6, din _ n _8, din _ n _10 …, din _ n _32 and din _ n _ 34; the output is total 2 × delay _ cycle ═ 16;
step 2.1.3, print always timing architecture produces all output signals, where din _ n _4, din _ n _8, din _ n _12 …, din _ n _32 are delayed by din _ n _0, din _ n _6, din _ n _10, din _ n _14 …, din _ n _34 are delayed by din _ n _ 2.
Step 2.2, operating an addition unit generator (hbfir _ adder _ gen.pl), generating an addition module hbfir _ adder, and printing the addition module hbfir _ adder in a file hbfir _ adder.v;
the step 2.2 specifically comprises the following steps:
step 2.2.1, reading an input data bit width data _ in _ width ═ 17 and a filter length filter _ length ═ 11 in a file parameter _ output.txt;
step 2.2.2, printing input and output signals: the input clock signal is clk; there are (filter _ length +1)/2 ═ 6 input data signals, din _ n _0, din _ n _2, din _ n _4, din _ n _6, din _ n _8, and din _ n _10, respectively; the output signals include (filter _ length +1)/4 ═ 3, which are respectively the adder _00, the adder _02 and the adder _ 04;
and 2.2.3, printing an always time sequence structure to generate all output signals, processing input and output according to signed numbers, and adding the output signals into delay data corresponding to a half-band folding structure.
Step 2.3, running the multiplication unit generator (hbfir _ mult _ gen.pl), generating the multiplication module hbfir _ mult, and printing the multiplication module hbfir _ mult in a file hbfir _ mult.v;
the step 2.3 comprises:
step 2.3.1, reading an adder bit width addr _ width ═ 17, a filter length filter _ length ═ 11 and a fixed point coefficient bit width coeffient _ width ═ 12 in a file parameter _ output.txt; read the filter fixed point coefficients in the file coefficient. txt to the coefficient array coefficient _ array ═ {29, -214,1209,2048 };
step 2.3.2, printing input and output signals: the input clock signal is clk; the number of input data signals is (filter _ length + 1)/4-3, which are respectively the adder _00, the adder _02 and the adder _ 04; the output signals are also (filter _ length +1)/4 ═ 3, which are mult _ h00, mult _ h02, mult _ h04, respectively;
step 2.3.3, printing filter coefficients, wherein (filter _ length +1)/4 is 3 in total; the coefficients are all defined as signed numbers, the bit width is coeffient _ width equal to 12, the coefficients are h00 equal to 29, h02 equal to 214, and h04 equal to 1209;
and 2.3.4, printing an always time sequence structure to generate all output signals, processing input and output according to signed numbers, and taking the value of the output signal as the product of the coefficient of the corresponding half-band filter and the adder.
Step 2.4, operating a summation unit generator (hbfir _ sub _ gen.pl), generating an addition module hbfir _ sub, and printing the addition module hbfir _ sub.v in a file hbfir _ sub.v;
the step 2.4 is specifically as follows:
step 2.4.1, reading multiplier bit width product _ width, filter length filter _ length, truncation length trunk _ width and addition pipeline stage number sum _ stage in file parameter _ output.txt;
step 2.4.2, printing an input and output signal, wherein the input clock signal is clk; the input signals are (filter _ length + 1)/4-3, which are respectively mult _ h00, mult _ h02 and mult _ h04 … …, and the output signal is sum;
step 2.4.3, printing adders according to the number of the adder production line stages, wherein each adder only adds two data; the number of adders of each stage is 2^ (sum _ stage-1) to 2, and 2^ (sum _ stage-2) to 1; the first-stage adder adds the input signals mult _ h00, mult _ h02 and mult _ h04, and if the input data is not enough than 2^ sum _ stage, the input signals are filled with 0; the first stage of addition has two adders, namely:
sum_stage1_0＝add_h00+add_h02；
sum_stage1_1＝add_h04+0；
the second-stage adder has a first-stage addition direct output, namely:
sum_stage2_0＝sum_stage1_0+sum_stage1_1。
and 2.4.4, truncating and outputting the calculation result of the last-stage adder in the step 2.4.3, namely sum [17:0] is sum _ stage2_0[28:11 ].
Step 2.5, operating an overflow processing unit generator (hbfir _ overflow _ handle _ gen.pl), generating an overflow processing module hbfir _ overflow _ handle, and printing the overflow processing module hbfir _ overflow _ handle in a file hbfir _ overflow _ handle.v;
step 2.6, operating a single-channel unit generator (hbfir _ single _ channel _ gen.pl), generating a single-channel module hbfir _ sign _ channel, and printing the single-channel module hbfir _ sign _ channel in a file hbfir _ sign _ channel.v; the single channel instantiates submodels hbfir _ adder, hbfir _ mult, hbfir _ sum and hbfir _ override _ handle respectively, and the instantiations are u _ hbfir _ adder, u _ hbfir _ mult, u _ hbfir _ sum and u _ hbfir _ override _ handle respectively;
step 2.7, operating a top-level unit generator (hbfir _ top _ gen.pl), generating a top-level model of the half-band filter, and printing the top-level model in a file hbfir _ top.v; the top-level unit instantiates two hbfir _ sign _ channel modules, wherein the instantiations are hbfir _ sign _ channel _ odd and hbfir _ sign _ channel _ even respectively; the top unit instantiates a delay module hbfir _ delay at the same time.
The step 2.7 comprises:
step 2.7.1, calculating a delay beat, and connecting corresponding values from the output port of the delay module hbfir _ delay generated in the step 2.1 to be used as two-phase outputs dout _ n _0 and dout _ n _ 2;
step 2.7.2, instantiating the delay module hbfir _ delay generated in the step 2.1 to u _ hbfir _ delay; instantiating the single-channel modules hbfir _ single _ channel generated in the two steps 2.6, which are hbfir _ single _ channel _ odd and hbfir _ single _ channel _ even respectively, and corresponding outputs are dout _ n _1 and dout _ n _3 respectively.
After all the steps 2 are performed, the generated half-band filter RTL model architecture is as shown in fig. 5.
And 3, capturing an RTL source code, printing a testbench file, and generating a test environment. The step 3 specifically includes:
step 3.1, opening the fh _ tb file operation handle, pointing to the new file tb _ hbfir _ top.v, and loading testbench codes printed in the subsequent steps; capturing an RTL source code, and identifying an input output signal and bit width thereof;
step 3.2, printing a file header, wherein the name of the module is tb _ hbfir;
step 3.3, printing reg and wire corresponding to input and output;
step 3.4, printing an initial module, and assigning initial values to all reg type variables as 0;
step 3.5, printing a clock module to generate a clock signal clk;
step 3.6, opening a file operation handle fh _ case to point to a new file CASe0.v; printing a test case to a file CASE0.v, wherein the test case comprises a random number excitation generation and reset signal rst jump signal;
step 3.7, printing a waveform storage command to a file CASEI 0.v; automatically selecting and saving waveform verilog syntax according to input parameters of Design _ Auto _ Gen _ TB _ v2.3.pl, saving the shm format waveform if the input parameters of the parameters are 0, and saving the fsdb format waveform if the parameters are 1; closing the file operation handle fh _ case;
step 3.8, instantiating a printing filter;
step 3.9, printing a simulation configuration environment file list.f and a run, wherein the list.f is a simulation file directory, and the run is a simulation operation command; automatically selecting a simulator grammar according to input parameters of Design _ Auto _ Gen _ TB _ v2.3.pl, if the parameter input parameters are 0, using NC _ verilog simulation, and if the parameter input parameters are not 1, using VCS simulation;
step 3.10, creating new directories tb, dc, format, CASE, format, data _ in and data _ out; move list.f, run and tb _ hbfir.v under the tb folder; CASe0.v moves under the CASE directory.
After the step 3 is completed, the Verdi file hierarchy view is as shown in fig. 6.
The steps 1-3 are executed in the Makefile command sequence, and the specific content is shown in fig. 7. The file tree structure before Makefile command execution is shown in fig. 8, and the file tree structure after Makefile command execution is shown in fig. 9.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A method for automatically generating a RTL model of a half-band interpolation filter is characterized by comprising the following steps:
step 1, an RTL model generator reads configuration information of a filter from a file coefficient.txt and a parameter _ input.txt, calculates all parameters of a filter component model, and stores the generated parameters in a file parameter _ output.txt;
step 2, reading the filter coefficient file by an RTL model generator, and generating RTL models of all filter components according to the parameters of the filter component model calculated in the step 1;
step 3, capturing RTL source codes, printing testbench files and generating test environments;
txt is a filter coefficient file, which contains all fixed-point coefficients of the half-band filter, but does not contain 0 coefficients; the file parameter _ input.txt is a filter configuration file and comprises a filter input data bit width, an output data bit width, a fixed point coefficient bit width and a filter length; the length L of the filter satisfies L4N +3, and the filter is centrosymmetric, wherein N is a non-negative integer;
all parameters of the filter component model comprise addition pipeline stage number, delay cycle number, adder bit width, multiplier bit width, truncation width and all information in the filter configuration file parameter _ input.txt;
the specific steps of the step 1 are as follows: step 1.1, reading all information in the file parameter _ input.txt, storing the information in an array parameter _ in _ array, and removing invalid information in the array parameter _ in _ array; respectively storing the bit width of input data, the bit width of output data, the bit width of a fixed point coefficient and the length of a filter in variables data _ in _ width, data _ out _ width, coeffient _ width and filter _ length;
step 1.2, calculating the number of required multipliers product _ num, and calculating the number of required addition pipeline stages sum _ stage according to the number of the multipliers; calculating delay period number delay _ cycle required by the delay unit according to the length of the filter; calculating bit width of the adder; calculating the bit width product _ width of the multiplier; calculating truncation width structation _ width;
step 1.3, firstly, all the parameter _ in _ array groups in step 1.1 are printed into a file parameter _ output.txt; then all the parameters calculated in the step 1.2 are printed to a file parameter _ output.txt;
the RTL model generator comprises a parameter calculation module, a delay unit generator, an addition unit generator, a multiplication unit generator, a summation unit generator, an overflow processing unit generator, a single-channel unit generator and a top-layer unit generator;
the specific steps of generating the RTL model in the step 2 are as follows: step 2.1, operating a delay unit generator to generate a delay module hbfir _ delay, and printing the delay module hbfir _ delay in a file hbfir _ delay.v;
step 2.2, operating the addition unit generator to generate an addition module hbfir _ order, and printing the addition module hbfir _ order in a file hbfir _ order.v;
step 2.3, operating the multiplication unit generator, generating a multiplication module hbfir _ mult, and printing the multiplication module hbfir _ mult in a file hbfir _ mult.v;
step 2.4, operating the summation unit generator to generate an addition module hbfir _ sum, and printing the addition module hbfir _ sum in a file hbfir _ sum.v;
step 2.5, operating the overflow processing unit generator, generating an overflow processing module hbfir _ overflow _ handle, and printing the overflow processing module hbfir _ overflow _ handle.v in a file hbfir _ overflow _ handle.v;
step 2.6, operating the single-channel unit generator to generate a single-channel module hbfir _ sign _ channel, and printing the single-channel module hbfir _ sign _ channel in a file hbfir _ sign _ channel.v; the single channel instantiates submodels hbfir _ adder, hbfir _ mult, hbfir _ sum and hbfir _ override _ handle respectively, and the instantiations are u _ hbfir _ adder, u _ hbfir _ mult, u _ hbfir _ sum and u _ hbfir _ override _ handle respectively;
step 2.7, operating a top-level unit generator, generating a top-level model of the half-band filter, and printing the top-level model in a file hbfir _ top.v; the top-level unit instantiates two hbfir _ sign _ channel modules, wherein the instantiations are hbfir _ sign _ channel _ odd and hbfir _ sign _ channel _ even respectively; the top unit instantiates a delay module hbfir _ delay at the same time.
2. The method for automatically generating a half-band interpolation filter RTL model according to claim 1, wherein said step 2.1 comprises:
step 2.1.1, reading the input data bit width data _ in _ width and the delay cycle delay _ cycle in the file parameter _ output.txt;
step 2.1.2, printing input and output signals: the input signals are clk, din _ n _0, din _ n _2, respectively; the output signals are din _ n _4, din _ n _6, din _ n _8 and din _ n _10 …; the output has 2 × delay _ cycles;
step 2.1.3, print always timing architecture produces all output signals, where din _ n _4, din _ n _8, din _ n _12 … are produced by din _ n _0 delay, and din _ n _6, din _ n _10, din _ n _14 … are produced by din _ n _2 delay.
3. The method for automatically generating the RTL model of the half-band interpolation filter according to claim 2, wherein the step 2.2 is specifically:
step 2.2.1, reading the input data bit width data _ in _ width and the filter length filter _ length in the file parameter _ output.txt;
step 2.2.2, printing input and output signals: the input clock signal is clk; there are (filter _ length +1)/2 input data signals, which are din _ n _0, din _ n _2, din _ n _4, and din _ n _6 … …; the output signals are (filter _ length +1)/4, and are respectively the adder _00, the adder _02 and the adder _04 … …;
and 2.2.3, printing an always time sequence structure to generate all output signals, processing input and output according to signed numbers, and adding the output signals by time delay data corresponding to a half-band folding structure.
4. A method for automatically generating a half-band interpolation filter RTL model according to claim 3, characterized in that said step 2.3 comprises:
step 2.3.1, reading the adder bit width adder _ width, the filter length filter _ length and the fixed point coefficient bit width coeffient _ width of the filter in the file parameter _ output.txt; reading the filter fixed point coefficient in the file coefficient.
Step 2.3.2, printing input and output signals: the input clock signal is clk; there are (filter _ length +1)/4 input data signals, which are respectively the adder _00, the adder _02 and the adder _04 … …; the output signals are also (filter _ length +1)/4, which are mult _ h00, mult _ h02 and mult _ h04 … … respectively;
step 2.3.3, printing filter coefficients (filter _ length +1)/4 in total; the coefficients are all defined as signed numbers, the bit width is coefficient _ width, and the coefficients are h00, h02 and h04 … … respectively;
and 2.3.4, printing an always time sequence structure to generate all output signals, processing input and output according to signed numbers, and taking the value of the output signal as the product of the coefficient of the corresponding half-band filter and the adder.
5. The method for automatically generating a half-band interpolation filter RTL model according to claim 4, wherein said step 2.4 comprises:
step 2.4.1, reading multiplier bit width product _ width, filter length filter _ length, truncation length trunk _ width and addition pipeline stage number sum _ stage in file parameter _ output.txt;
step 2.4.2, printing an input and output signal, wherein the input clock signal is clk; the number of input signals is (filter _ length +1)/4, which are respectively mult _ h00, mult _ h02 and mult _ h04 … …, and the output signal is sum;
step 2.4.3, printing adders according to the number of the adder production line stages, wherein each adder only adds two data; the number of adders of each stage is 2^ (sum _ stage-1), 2^ (sum _ stage-2) … … until the adder of the last stage is only a single adder; the first-stage adder adds the input signals mult _ h00, mult _ h02 and mult _ h04 … …, and if the input data is not enough than 2^ sum _ stage, the input signals are filled with 0;
and 2.4.4, truncating and outputting the calculation result of the last-stage adder in the step 2.4.3.
6. The method for automatically generating a half-band interpolation filter RTL model according to claim 5, wherein said step 2.7 comprises:
step 2.7.1, calculating a delay beat, and connecting corresponding values from the output port of the delay module hbfir _ delay generated in the step 2.1 as two-phase outputs dout _ n _0 and dout _ n _ 2;
step 2.7.2, instantiating the delay module hbfir _ delay generated in the step 2.1 to u _ hbfir _ delay; instantiating the two single-channel modules hbfir _ single _ channel generated in step 2.6, which are hbfir _ single _ channel _ odd and hbfir _ single _ channel _ even respectively, and corresponding outputs are dout _ n _1 and dout _ n _3 respectively.
7. The method for automatically generating a half-band interpolation filter RTL model according to claim 6, wherein said step 3 comprises:
step 3.1, opening the fh _ tb file operation handle, pointing to the new file tb _ hbfir _ top.v, and loading testbench codes printed in the subsequent steps; capturing RTL source codes, and identifying input output signals and bit widths thereof;
step 3.2, printing a file header, wherein the name of the module is tb _ hbfir;
step 3.3, printing reg and wire corresponding to input and output;
step 3.4, printing an initial module, and assigning initial values to all reg type variables as 0;
step 3.5, printing a clock module to generate a clock signal clk;
step 3.6, opening a file operation handle fh _ case to point to a new file CASe0.v; printing a test case to a file CASE0.v, wherein the test case comprises a random number excitation generation and reset signal rst jump signal;
step 3.7, printing a waveform storage command to a file CASEI 0.v; automatically selecting and saving waveform verilog syntax according to input parameters of Design _ Auto _ Gen _ TB _ v2.3.pl, saving shm format waveforms if the input parameters of the parameters are 0, and saving fsdb format waveforms if the input parameters of the parameters are 1; closing the file operation handle fh _ case;
step 3.8, instantiating a printing filter;
step 3.9, printing a simulation configuration environment file list.f and a run, wherein the list.f is a simulation file directory, and the run is a simulation operation command; automatically selecting a simulator grammar according to input parameters of Design _ Auto _ Gen _ TB _ v2.3.pl, if the parameter input parameters are 0, using NC _ verilog simulation, and if the parameter input parameters are not 1, using VCS simulation;
step 3.10, newly creating directories tb, dc, format, CASE, waveform, data _ in and data _ out; move list.f, run and tb _ hbfir.v under the tb folder; CASe0.v moves under the CASE directory.
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