CN113568598B - Yosys-based FPGA logic synthesis method and device for realizing summation operation - Google Patents
Yosys-based FPGA logic synthesis method and device for realizing summation operation Download PDFInfo
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Abstract
The invention provides an FPGA logic synthesis method and device for realizing summation operation based on yosys, which is characterized in that the yosys is used for analyzing a user circuit description file of the summation operation to generate a syntax tree; extracting RTL-level data objects describing the summation module according to the node types in the syntax tree to form an RTL-level data object set; converting the RTL-level data object set into a logic gate-level object set, and establishing carry chain signal connection between logic gate-level objects; and printing and extracting the logic netlist file. The method comprises the steps of splitting a multi-bit wide operand of an RTL-level Cell object, establishing a plurality of single-bit wide logic gate-level Cell object sets, and establishing a Wire type carry signal generated by summation operation while establishing a new logic gate-level Cell object.
Description
Technical Field
The invention belongs to the field of FPGA (field programmable gate array), and particularly relates to an FPGA logic synthesis method and device for realizing summation operation based on yosys.
Background
Compared with an ASIC (application specific integrated circuit), the FPGA can control the connection of an internal programmable switch in a programming mode to realize the arbitrary customization of the circuit function. And the programming speed of the FPGA is very fast, if the chip finds problems in system level test, the problem can be quickly solved by reprogramming, the FPGA has overwhelming advantages in production period, and the FPGA has a relatively large-scale industry on the global scale at present.
EDA (electronic design automation) software is development auxiliary software necessary for FPGA chip design and is responsible for compiling high-level circuit description of a user into a configuration download file for configuring a programmable switch of the FPGA chip, and a logic synthesis algorithm is an important ring in an operation flow and has the function of converting the high-level and behavioral-level circuit description file into a logic netlist file consisting of FPGA logic unit blocks.
Disclosure of Invention
The invention aims to solve the technical problem of how to realize summation operation by using fewer logic unit blocks, and provides a Ysys-based FPGA logic synthesis method and device for realizing summation operation.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
an FPGA logic synthesis method for realizing summation operation based on yosys comprises the following steps: step 1: analyzing the behavioral level user circuit description file of the summation operation by using a yosys open source program to generate a syntax tree;
step 2: traversing all nodes in the syntax tree, extracting RTL-level data objects describing a summation function module according to the node types in the syntax tree, and forming an RTL-level data object set;
and step 3: converting each RTL level object in the RTL level data object set into a logic gate level object set with carry chain signal connection;
and 4, step 4: and traversing the RTL level data object set to obtain all logic gate level object sets, and mapping the logic gate level object sets into physical gate level objects to print and extract a logic netlist file.
Further, step 3 further comprises: optimizing the set of logical gate level objects.
Further, the behavioral user circuit description file in step 1 is a user circuit design file using a Verilog format hardware description language.
Further, the method for converting each RTL level object in the RTL level data object set into a logic gate level object set with carry chain signal connection in step 3 is:
step 3.1: splitting a multi-bit wide operand of the RTL-level data object, and establishing a unit wide logic gate level Cell object corresponding to the bit width number of the operand with a larger bit width in two operands of the RTL-level data object;
step 3.2: newly building a Wire type carry signal generated by summation operation while building a unit wide logic gate Cell object;
step 3.3: sequentially assigning input/output port connection information of the RTL-level Cell object to the input/output port connection information of each newly-built unit wide logic gate-level Cell object bit by bit;
step 3.4: the logic gate level Cell object is provided with a carry input port and a carry output port, and the carry signal is connected with the carry output port of the currently newly-built logic gate level object and the carry input port of the next adjacent logic gate level object;
step 3.5: and obtaining a port connection parameter FUN value of the logic gate-level Cell object according to the input/output port connection state information of the logic gate-level Cell object, and obtaining a functional parameter value LUT of the logic gate-level Cell object according to the port connection parameter FUN value.
Further, the specific method of assigning values bit by bit in step 3.3 is:
step 3.3.1: respectively acquiring A, B input end connection signals sig _ a and sig _ b of a current RTL level cell object and a Y output end signal sig _ Y, and acquiring the minimum value of the signal bit width of sig _ a and sig _ b and recording the minimum value as N;
step 3.3.2: creating N logic gate level Cell objects, respectively assigning the ith bits sig _ a [ i ] and sig _ b [ i ] of signals connected with the A, B input end of the RTL level Cell object to the two input ends of the ith logic gate level Cell object, and assigning the ith bit Y output end signal sig _ Y [ i ] of the RTL level Cell object to the output end of the ith logic gate level Cell object.
Step 3.3.3: judging whether the bit widths of sig _ a and sig _ b signals are consistent, if so, ending, otherwise, acquiring the larger bit width of sig _ a and sig _ b, assigning the value of the larger bit width to a temporary object extra _ sig, calculating the bit width to be M, circulating i from N +1 to M ending, continuously creating M-N unit-wide logic gate level Cell objects, assigning extra _ sig [ i ] to one input port of the M-N logic gate level Cell objects, and assigning sig _ y [ i ] to an output port.
Further, the method for optimizing the set of logic gate level objects in step 3 is:
when one input port connection signal of the logic gate level object is a fixed 0, judging whether a carry signal exists:
if not, deleting the current logic gate Cell object, and connecting another input port signal with an output port signal;
if so, connecting the carry signal to an input port of a current logic gate-level object connection fixed 0 signal, and clearing the carry signal;
when one input port connection signal of the logic gate level object is a fixed 1, judging whether the same port of the logic gate level object adjacent to the next bit of the current logic gate level object is connected with a fixed 0 signal or not,
if yes, deleting the current logic gate Cell object, saving the original signal of the input signal at the other end as a carry signal for standby, and connecting the negation signal with the output port signal;
if not, clearing the input port signal of the current logic gate object connected with the fixed 1 and correspondingly modifying the LUT parameter.
Further, the specific method of step 4 is:
step 4.1: describing the mapping relation of the logic gate level object to the physical gate level object in a cells _ map.v library file in verilog format,
step 4.2: analyzing the library file to obtain the mapping relation from the logic gate level object to the physical gate level object, wherein the mapping relation comprises the number of calling physical gate level instances and the mapping relation between ports and parameters in the logic gate level module;
step 4.3: after the logical gate-level Cell object set is obtained, data conversion from the logical gate-level Cell object set to the physical gate-level object set is completed according to the mapping relation, and information transmission of ports and parameters is completed;
step 4.4: and printing a logic netlist file containing the physical gate-level object set according to a specified output format.
The invention also provides an FPGA logic comprehensive device for realizing summation operation based on yosys, which comprises the following modules:
a syntax tree generation module: the syntax tree is generated by analyzing the behavioral level user circuit description file of the summation operation by using a yosys open source program;
the RTL level data object extraction module: the system comprises a syntax tree generation module, a syntax tree generation module and a summation function module, wherein the syntax tree generation module is used for generating a syntax tree;
a logic gate level object generation module: the system comprises a RTL level data object set, a logic gate level object set and a plurality of RTL level data object sets, wherein the RTL level data object set is used for converting each RTL level object in the RTL level data object set into a logic gate level object set with carry chain signal connection, establishing carry chain signal connection between the logic gate level objects and assigning corresponding attribute information to the carry chain signal connection;
a logic netlist file output module: and the system is used for traversing the RTL level data object set to obtain all logic gate level object sets, and mapping the logic gate level object sets into physical gate level objects to print and extract a logic netlist file.
By adopting the technical scheme, the invention has the following beneficial effects:
the invention provides a Field Programmable Gate Array (FPGA) logic synthesis method and device for realizing summation operation based on yosys, which are characterized in that a plurality of bit wide operands of an RTL level Cell object are split, a plurality of logic gate level Cell object sets with single bit wide are established, a new carry signal representing a Wire type generated by the summation operation is established while the logic gate level Cell object is established, as the logic gate level object is additionally provided with a carry input port and a carry output port, a carry signal is added between the logic gate level objects, and the carry signal is used as an operand, so that logic units required for calculating carry data are saved, the number of logic unit blocks in a synthesis result is reduced, and further the logic gate level object is further optimized according to whether the operand is a constant, whether the carry signal is empty and the like, and the number of the logic unit blocks is further reduced.
Drawings
FIG. 1 is a flow chart of the system of the present invention;
FIG. 2 is an algorithmic flow chart of the process of establishing carry chain connections for logical gate-level objects in accordance with the present invention;
FIG. 3 is a comparison of results from the set of logic gate level objects generated using a carry chain approach as shown in FIG. 4 based on the circuit for the summation operation described in FIG. 2;
FIG. 4 is a flow chart of a method of optimizing operands, including constants, for a summation operation according to the present invention;
FIG. 5 is a comparison diagram of logic gate level results after optimization for a sum operation involving constant operands according to the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An FPGA logic synthesis method for realizing summation operation based on yosys, as shown in fig. 1, includes the following steps:
step 1: the behavioral level user circuit description file of the summation operation is parsed into a syntax tree using the yosys open source program. In this embodiment, the behavioral user circuit description file is a user circuit design file using a Verilog format hardware description language.
The following provides a behavioral level user circuit description file of a summation operation based on verilog format:
module add(a,b,out);
input [3:0]a;
input [3:0]b;
output [4:0]out;
wire [4:0]out;
assign out=a+b;
endmodule 。
the circuit function of the circuit description file is to realize summation operation of two input port signals 'a' and 'b' and assign a result to an output port 'out', wherein the two input port signals 'a [3:0 ]' and 'b [3:0 ]' are used as addend operands, and the signal bit width is 4; the output port signals "out [4:0 ]" are used as operation and operand, and the signal bit width is 5.
The syntax tree structure file for circuit description extraction for summation operations described in the circuit description file using yosys lexical and syntactic parsing is given below as follows:
AST_MODULE str=’\add’
AST_WIRE str=’\a’ input port=1
AST_RANGE
AST_CONSTANT bits=’000000000000000000000000000000011’(32) signed range=[31:0] int=3
AST_CONSTANT bits=’000000000000000000000000000000000’(32) signed range=[31:0]
AST_WIRE str=’\b’ input port=2
AST_RANGE
AST_CONSTANT bits=’000000000000000000000000000000011’(32) signed range=[31:0] int=3
AST_CONSTANT bits=’000000000000000000000000000000000’(32) signed range=[31:0]
AST_WIRE str=’\out’ output port=3
AST_RANGE
AST_CONSTANT bits=’000000000000000000000000000000100’(32) signed range=[31:0] int=4
AST_CONSTANT
bits=’000000000000000000000000000000000’(32) signed range=[31:0]
AST_WIRE str=’\out’
AST_RANGE
AST_CONSTANT bits=’000000000000000000000000000000100’(32) signed range=[31:0] int=4
AST_CONSTANT bits=’000000000000000000000000000000000’(32) signed range=[31:0]
AST_ASSIGN
AST_IDENTIFIER str=’\out’
AST_ADD
AST_IDENTIFIER str=’\a’
AST_IDENTIFIER str=’\b’ 。
from the circuit description file, it can be known that the type of the root node in the syntax tree is AST _ MODELE, the node corresponds to a keyword of "mode" in verilog syntax, and the node contains a str attribute "\ add" which represents the whole user circuit addition operation MODULE "add". The AST _ MODULE includes four AST _ wide child nodes respectively corresponding to "input", "output", and "WIRE" keywords in the verilog syntax, and respectively corresponding to the input/output ports and the net objects "a", "b", and "out" as can be known from the str attributes of the nodes. Wherein the first AST _ WIRE sub-node comprises an AST _ RANGE sub-node describing the signal bit width of the current port connection; the AST _ RANGE node comprises two AST _ CONSTANT sub-nodes which respectively represent CONSTANT values of an upper limit and a lower limit of a bit width; the AST _ MODULE further comprises an AST _ ASSIGN sub-node corresponding to an assignment statement "ASSIGN out = a + b" in the user circuit, the AST _ ASSIGN node comprises an AST _ IDENTIFIER sub-node representing a left value signal "out" of the assignment statement; the AST _ ASSIGN node comprises an AST _ ADD sub-node which represents an addition operation statement, and the AST _ ADD node comprises two AST _ IDENTIFIER sub-nodes which represent two addend operand signals in the addition operation process.
Step 2: and traversing all nodes in the syntax tree, and extracting RTL-level data objects describing the summation function module according to the node types in the syntax tree to form an RTL-level data object set. The RTL-level data object type mainly comprises a Design type for describing the whole circuit Design of a user; describing a single function Module type, wherein one Design can contain objects of a plurality of Module types corresponding to a 'Module' keyword in verilog syntax; the input, output and reg describing the inside of the Module specify the Wire type of the signal, the Cell type describing the calling instance of the inside of the Module and the like, and one Module type object can contain a plurality of Wire instances and Cell instances.
Traversing the syntax tree, and creating a Module class object when traversing to an AST _ Module root node; when traversing to AST _ WIRE type child node of AST _ MODEL, creating WIRE type object WIRE and assigning the bit width attribute of the WIRE object through the AST _ WIRE child node, and finally storing the WIRE object to the WIRE attribute of the MODULE object; when traversing to the AST _ ASSIGN type child node of the AST _ MODULE, creating an RTL-level Cell type Cell object, determining that the type attribute of the Cell object is "$ ADD" through the AST _ ADD child node, where "$ ADD" is a program built-in type and is used to describe summation operation, and a port definition includes an input port A, B and an output port Y. The port connection attribute of the cell object is assigned by the AST _ IDENTIFIER child node as follows: the port A is connected with an 'a' signal; a B port connection signal "B"; the Y port is connected to a signal "out".
And step 3: converting each RTL level object in the RTL level data object set into a logic gate level object set with carry chain signal connection;
the $ _ LCELL _ COMB _ type logical gate level object ports and parameters are defined as follows in this embodiment.
module \$_LCELL_COMB_(input A,B,C,D,CIN,output Y,COUT);
parameter LUT =0;
Parameter MODE =“normal”;
Parameter SUM_LUT_INPUT =0;
Parameter FUN =“NORMAL”。
The invention converts the $ add type RTL level object corresponding to summation operation into a $ _ LCELL _ COMB _ type logic gate level object, the $ _ LCELL _ COMB _ unit type comprises an input port A, B, C, D and CIN, wherein A, B, C, D is a data input port, and CIN is a carry input port; including a combination output port Y and a carry output port COUT.
In this embodiment, as shown in fig. 2, a specific method for converting the RTL-level object into the logic gate-level object set with carry chain signal connection in step 3 is as follows:
step 3.1: splitting a multi-bit wide operand of the RTL-level data object, and establishing a unit wide logic gate level Cell object corresponding to the bit width number of the operand with a larger bit width in two operands of the RTL-level data object;
step 3.2: newly building a Wire type carry signal generated by summation operation while building a unit wide logic gate Cell object;
step 3.3: sequentially assigning input/output port connection information of the RTL-level Cell object to the input/output port connection information of each newly-built unit wide logic gate-level Cell object bit by bit;
step 3.4: the logic gate level Cell object is provided with a carry input port and a carry output port, and the carry signal is connected with the carry output port of the currently newly-built logic gate level object and the carry input port of the next adjacent logic gate level object; the carry output port and the carry input port of the two logic gate level objects are connected through the carry signal, namely the connection of the carry chain, so that the carry signal is used as an operand and is connected to the next logic gate level object through the carry input port, logic units required for calculating carry data are saved, and the number of logic unit blocks in a comprehensive result is reduced.
Step 3.5: and obtaining a port connection parameter FUN value of the logic gate-level Cell object according to the input/output port connection state information of the logic gate-level Cell object, and obtaining a functional parameter value LUT of the logic gate-level Cell object according to the port connection parameter FUN value.
As shown in table 1, the value of the port connection parameter FUN is known from the connection status of the port, and the value of the functional parameter LUT of the logical gate Cell object is obtained from the value of the port connection parameter FUN.
The FUN parameter of the logic gate level Cell object is a character string type and is used for identifying the port connection condition of the logic gate level Cell object, the port connection condition depends on the number of operands of the summation operation, the number of the operands is 3 in the general case, the logic gate level Cell object is called a full adder and comprises two addend operands and a carry operand, and the first summation operation of the summation operation is usually called a half adder and only comprises the two addend operands and does not comprise the carry operand. Alternatively, when the two addend bits are not identical, a case may arise where the sum operation contains only one addend operand and one carry operand. The LUT parameters are of a 16-bit binary array type and store the functional truth table of the Cell object at the logic gate level, and the truth result is also influenced by the number and position of the operands, wherein the upper 8 bits store the truth value of the summation logic and the lower 8 bits store the truth value of the carry. On the other hand, the operand true value is usually 0 or 1, but when the operand of the summation operation of the user circuit has a constant value rather than a signal, the operand true value is also adjusted to a fixed value of 0 or 1, which also affects the true value result of the final summation or carry calculation.
FIG. 2 is a flowchart of an algorithm for establishing a carry chain connection for a logical gate level object according to the present invention. First, an RTL level $ add type data object corresponding to the summation operation is converted into a logic gate level object set of the $ _ LCELL _ COMB _ type. As shown in fig. 2, a process data source is an RTL-level data object Cell type object set Cell cells describing a mobile object of a current circuit design, a Cell set is traversed, an addd-type Cell object is selected for processing, A, B input end connection signals sig _ a, sig _ b and a Y output end signal sig _ Y of the current RTL-level data object Cell object are respectively obtained, the minimum values of sig _ a and sig _ b bit width signals are obtained and recorded as N, i is cycled from 0 for N times, N Cell objects with type LCELL _ COMB _ are created, input and output ports are respectively assigned with values of sig _ a [ i ], sig _ b [ i ] and sig _ Y [ i ], and the number of created Cell objects is counted and stored in a data object count. And creating a Wire type carry signal Wire _ COUT, inserting the set Wire type set Wire _ COUT, and assigning the Wire _ COUT signal to a COUT output port of the logic gate-level Cell object. And judging whether the currently created Cell object corresponds to the calculation of a first signal of the summation operation or not through count counting, wherein the first calculation does not have the carry information of the previous bit, if so, the function is judged to be a HALF ADDER, the FUN parameter is assigned to HALF _ ADDER, the LUT parameter value is 6688, if not, the CIN input port of the currently created Cell object is assigned to the wires _ cout [ i-1] of the previous Cell object, the carry output signal represents the carry output signal generated by the previous Cell object, the FUN parameter is NORMAL, and the LUT parameter value is assigned to 96E 8.
The number of Cell objects of LCELL _ COMB _ created in the process is N, whether signal bit widths of sig _ a and sig _ b are consistent or not is continuously judged, if yes, the end is reached, otherwise, the bit width of sig _ a and sig _ b which is larger is obtained and assigned to a temporary object extra _ sig, the bit width is calculated to be M, i circulates from N +1 to M end, M-N Cell objects with the type of LCELL _ COMB _ are continuously created, the Cell objects are known to only comprise a signal source extra _ sig representing an input operand, an input port A of each Cell object is assigned with extra _ sig [ i ], an output port is assigned with sig _ y [ i ], and Cell parameters of the Cell objects are assigned with A _ ADDEND to represent that only comprise a sum signal and a carry signal. Similarly, a carry signal wire _ COUT is created, the carry signal wire _ COUT is connected to the COUT terminal of the logic gate Cell object, a COUT output terminal signal of a logic gate Cell object is arranged on the CIN terminal of the carry input terminal of the logic gate Cell object, the LUT parameter value is assigned to be 5AA0 according to the FUN parameter assignment, the corresponding relation between the FUN parameter and the LUT parameter value is shown in table 1, and the type of the logic gate object in this embodiment is LCELL _ COMB _.
TABLE 1 FUN parameter meanings for logical gate level objects and corresponding LUT parameter values
Table 1 shows the meaning of the "FUN" parameter and the corresponding LUT parameter values for the LCELL _ COMB type logic gate level object of the present invention. The value of the FUN parameter is determined based on the port of the LCELL _ COMB object to which the add operand signal is connected. The FUN parameter and the LUT parameter are in one-to-one correspondence, and the LUT parameter is also dependent on the number and position of the operands. Taking the FUN parameter NORMAL as an example, it indicates that the current value of A, B includes an addend operand and a carry operand, and the LUT value is calculated as shown in table 2.
TABLE 2 calculation of LUT parameter values for $ LCELL _ COMB _ TYPE LOGIC DOOR LEVEL OBJECTS
Table 2 illustrates the calculation of LUT parameter values for $ _ LCELL _ COMB _ type logical gate level objects of the present invention. Taking the case that the FUN parameter of the LCELL _ COMB type logic gate level object is NORMAL as an example, as can be seen from Table 1, when the FUN parameter is NORMAL, it represents a full adder, the operand includes the addition number at the A end and the B end and the CIN carry, and the addition number and CIN carry are taken as the input of the true value calculation according to the sequence of A, B, CIN, the Y and COUT output ports of the $ LCELL _ COMB type are taken as the output of the true value calculation, wherein the Y end calculates the true value according to the summation logic, the COUT end calculates the true value according to the carry calculation logic, the true value result of the Y end is taken as the upper 8 bits of the LUT parameter value, and the hexadecimal is represented as "96"; the COUT end obtains a truth value result as the lower 8 bits of the LUT parameter value, and the hexadecimal system is expressed as 'E8', and the hexadecimal system of the LUT parameter final result is expressed as '96E 8'.
Fig. 3 is a comparison diagram of the result of the generated set of logic gate level objects for performing the summation operation based on the circuit description file by using the carry chain connection manner shown in fig. 2, and for an RTL level data object, as can be seen from the right side of fig. 3, the number of logic gate level objects of the $ _ LCELL _ COMB _ type required by the circuit by using the carry chain implementation manner is 5, 4 logic gate level objects of the $ _ LCELL _ COMB _ type are saved compared with the diagram on the left side of fig. 3 without using the carry chain manner, as the logic gate level objects add carry input ports and carry output ports, carry signals are added between the logic gate level objects, as can be seen from the diagram on the right side of fig. 3, vertical line arrows represent carry information, in the embodiment, the carry signals are used as operands, and compared with the left side of fig. 3, the logic units required for calculating carry data are saved, the number of logic unit blocks in the comprehensive result is reduced. Experiments prove that for an RTL level data object with a bit width of ten, the number of logic gate object units used without adding a carry chain is 28, and the number of logic gate object units using carry chain signals is only 11; for an RTL level data object with twenty bits wide, the number of logic gate object units used without adding carry chain is 68, and the number of logic gate object units using carry chain signal is only 21. Therefore, the carry input port and the carry output port are added on the logic gate object, the carry signal is added between the logic gate level objects, and the reduced number of logic gate object units is very obvious.
In this embodiment, the set of logic gate level objects is further optimized.
And according to the signal connection condition of the input port of the logic gate-level Cell object, performing logic gate-level optimization when the connection signal of a certain input port is fixed 0 or 1.
When one input port connection signal of the logic gate level object is a fixed 0, judging whether a carry signal exists:
if not, deleting the current logic gate Cell object, and connecting another input port signal with an output port signal;
if so, connecting the carry signal to an input port of a current logic gate-level object connection fixed 0 signal, and clearing the carry signal;
when one input port connection signal of the logic gate level object is a fixed 1, judging whether the same port of the logic gate level object adjacent to the next bit of the current logic gate level object is connected with a fixed 0 signal or not,
if yes, deleting the current logic gate Cell object, saving the original signal of the input signal at the other end as a carry signal for standby, and connecting the negation signal with the output port signal;
if not, clearing the input port signal of the current logic gate object connected with the fixed 1 and correspondingly modifying the LUT parameter.
The number of logic gate level object units can be further reduced according to the signal connection condition of the input port of the logic gate level object. FIG. 4 is a flow chart of a method of optimizing operands, including constants, for a summation operation according to the present invention. As shown in fig. 4, the optimized object is a Cell object, and the related input data includes the next summation operation operand signals next _ sig _ a and next _ sig _ b for determining whether there is a space for further optimization and the carry signal carry generated by the previous summation operation as the operand of the current summation operation, and the total number of the currently created logic gate level Cell objects is used to determine the FUN parameter and LUT parameter value of the current logic gate level Cell object.
The optimization process shown in fig. 4 is: and acquiring A, B end signal connections sig _ a and sig _ b of the current Cell object and a Y end output signal sig _ Y. And judging whether the signals sig _ a and sig _ b contain constants or not, and directly returning if the constant operands are not contained. Otherwise, specifically judging whether the constant is sig _ a or sig _ b, if the constant is sig _ b, continuously judging to be constant 0 or 1, if so, judging whether a carry signal carry is contained, if the carry signal carry is empty, directly establishing connection between the signals sig _ a and sig _ y and deleting the current Cell object, and simultaneously, counting by one; and if the containing car signal is not null, replacing the car signal with the sig _ B to assign the B end connection of the Cell object and clearing the car signal. If the Cell object is 1, judging whether next _ sig _ b is a constant 0, if so, inverting the sig _ a signal and connecting the signal to sig _ y, deleting the current Cell object, and subtracting one from the count; otherwise, the LUT parameter and the FUN parameter are updated according to the fixed value 1 of sig _ b. The sig _ a signal is a constant signal as above.
FIG. 5 is a comparison diagram of logic gate level results after optimization for a sum operation involving constant operands according to the present invention. For example, the result of the generated set of logic gate objects of the $ _ LCELL _ COMB _ type after optimization and before optimization using the optimization algorithm shown in fig. 4 is compared by taking the user circuit containing the "assign out = a + 10" and "sum assignment statement as an example. As shown in FIG. 5, the logic gate level Cell object describing the two-bit operation prior to the sum operation is optimized for deletion, instead of using the assign statement, while one operand "a [1 ]" of the second $ _ LCELL _ COMB object is assigned the B-port input port signal of the third $ _ LCELL _ COMB object. The number of $ _ LCELL _ COMB _ type logic gate objects needed by the optimized circuit is reduced by 2.
And 4, step 4: and traversing the RTL level data object set to obtain all logic gate level object sets, and mapping the logic gate level object sets into physical gate level objects to print and extract a logic netlist file.
Step 4.1: describing the mapping relation of the logic gate level object to the physical gate level object in a cells _ map.v library file in verilog format,
step 4.2: analyzing the library file to obtain the mapping relation from the logic gate level object to the physical gate level object, wherein the mapping relation comprises the number of calling physical gate level instances and the mapping relation between ports and parameters in the logic gate level module;
a logic gate level object generation module: the system comprises a RTL level data object set, a logic gate level object set and a plurality of RTL level data object sets, wherein the RTL level data object set is used for converting each RTL level object in the RTL level data object set into a logic gate level object set with carry chain signal connection, establishing carry chain signal connection between the logic gate level objects and assigning corresponding attribute information to the carry chain signal connection;
a logic netlist file output module: and the system is used for traversing the RTL level data object set to obtain all logic gate level object sets, and mapping the logic gate level object sets into physical gate level objects to print and extract a logic netlist file.
The embodiment provides a mapping file from a logic gate level \ $ LCELL _ COMB _ type to a physical gate level LCELL _ COMB type:
module \$LCELL_COMB (input A, B, C,D,CIN, output Y,COUT);
parameter LUT = 0;
parameter SUM_LUT_INPUT = 0;
parameter FUN = "NORMAL";
parameter MODE = "normal";
if(FUN == "NORMAL")begin
lcell_comb #(.lut_mask(LUT),.sum_lutc_input(SUM_LUT_INPUT),.operation_mode(MODE)) REPLACE_(.combout(Y),.cout(COUT), .dataa(A), .datab(B), .datac(),.datad(),.cin(CIN));
end
if (FUN == "A_HALF_ADDER")begin
lcell_comb #(.lut_mask(LUT),.sum_lutc_input(SUM_LUT_INPUT),.operation_mode(MODE)) REPLACE_(.combout(Y),.cout(COUT), .dataa(A), .datab(), .datac(),.datad(),.cin());
end
if (FUN == "B_HALF_ADDER")begin
lcell_comb #(.lut_mask(LUT),.sum_lutc_input(SUM_LUT_INPUT),.operation_mode(MODE)) REPLACE_(.combout(Y),.cout(COUT), .dataa(), .datab(B), .datac(),.datad(),.cin());
end
if (FUN == "HALF_ADDER")begin
lcell_comb #(.lut_mask(LUT),.sum_lutc_input(SUM_LUT_INPUT),.operation_mode(MODE)) REPLACE_(.combout(Y),.cout(COUT), .dataa(A), .datab(B), .datac(),.datad(),.cin());
end
if (FUN == "A_ADDEND")begin
lcell_comb #(.lut_mask(LUT),.sum_lutc_input(SUM_LUT_INPUT),.operation_mode(MODE)) REPLACE_(.combout(Y),.cout(COUT), .dataa(A), .datab(), .datac(),.datad(),.cin(CIN));
end
if (FUN == "B_ADDEND")begin
lcell_comb #(.lut_mask(LUT),.sum_lutc_input(SUM_LUT_INPUT),.operation_mode(MODE)) REPLACE_(.combout(Y),.cout(COUT), .dataa(), .datab(B), .datac(),.datad(),.cin(CIN));
end
if (FUN == "LAST_ADDER")begin
lcell_comb #(.lut_mask(LUT),.sum_lutc_input(SUM_LUT_INPUT),.operation_mode(MODE)) REPLACE_(.combout(Y),.cout(), .dataa(), .datab(), .datac(),.datad(),.cin(CIN));
end
endmodule。
from the mapping file, it can be known that the port definition of the \ $ LCELL _ COMB _ type and the port definition of the LCELL _ COMB are in a one-to-one correspondence relationship, as follows:
dataa (a), (b), (dac (c), (d), (cin), (c), (d), (c), (cin), (c. However, the ports are selectively connected according to the FUN parameter of the \ $ LCELL _ COMB _ type, and the rest ports are empty.
The invention also provides an FPGA logic comprehensive device for realizing summation operation based on yosys, which comprises the following modules:
a syntax tree generation module: the syntax tree is generated by analyzing the behavioral level user circuit description file of the summation operation by using a yosys open source program;
the RTL level data object extraction module: the system comprises a syntax tree generation module, a syntax tree generation module and a summation function module, wherein the syntax tree generation module is used for generating a syntax tree;
a logic gate level object generation module: the system comprises a RTL level data object set, a logic gate level object set and a plurality of RTL level data object sets, wherein the RTL level data object set is used for converting each RTL level object in the RTL level data object set into a logic gate level object set with carry chain signal connection, establishing carry chain signal connection between the logic gate level objects and assigning corresponding attribute information to the carry chain signal connection;
a logic netlist file output module: and the system is used for traversing the RTL level data object set to obtain all logic gate level object sets, and mapping the logic gate level object sets into physical gate level objects to print and extract a logic netlist file.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. An FPGA logic synthesis method for realizing summation operation based on yosys is characterized by comprising the following steps:
step 1: analyzing the behavioral level user circuit description file of the summation operation by using a yosys open source program to generate a syntax tree;
step 2: traversing all nodes in the syntax tree, extracting RTL-level data objects describing a summation function module according to the node types in the syntax tree, and forming an RTL-level data object set;
and step 3: traversing the RTL-level data object set, converting each RTL-level data object in the RTL-level data object set into a plurality of single-bit logic gate-level Cell objects with carry input ports and carry output ports, creating a Wire-type carry signal representing summation operation while creating the logic gate-level Cell objects, and taking the carry signal as an operand;
and 4, step 4: and mapping all the converted logic gate-level objects into a physical gate-level object, printing and extracting a logic netlist file.
2. The method of claim 1, wherein step 3 further comprises: and optimizing a plurality of single-bit-wide logic gate-level Cell objects with carry input ports and carry output ports converted by each RTL-level data object.
3. The method according to claim 2, wherein the behavioral user circuit description file in step 1 is a user circuit design file using Verilog format hardware description language.
4. The method according to claim 2, wherein the specific method of step 3 is:
step 3.1: splitting a multi-bit wide operand of the RTL-level data object, and establishing a unit wide logic gate level Cell object corresponding to the bit width number of the operand with a larger bit width in two operands of the RTL-level data object;
step 3.2: newly building a Wire type carry signal generated by summation operation while building a unit wide logic gate Cell object;
step 3.3: sequentially assigning input/output port connection information of the RTL-level Cell object to the input/output port connection information of each newly-built unit wide logic gate-level Cell object bit by bit;
step 3.4: the logic gate level Cell object is provided with a carry input port and a carry output port, and the carry signal is connected with the carry output port of the currently newly-built logic gate level object and the carry input port of the next adjacent logic gate level object;
step 3.5: and obtaining a port connection parameter FUN value of the logic gate-level Cell object according to the input/output port connection state information of the logic gate-level Cell object, and obtaining a functional parameter value LUT of the logic gate-level Cell object according to the port connection parameter FUN value.
5. The method of claim 4, wherein the specific method of bitwise assignment in step 3.3 is:
step 3.3.1: respectively acquiring A, B input end connection signals sig _ a and sig _ b of a current RTL level cell object and a Y output end signal sig _ Y, and acquiring the minimum value of the signal bit width of sig _ a and sig _ b and recording the minimum value as N;
step 3.3.2: creating N logic gate level Cell objects, respectively assigning the ith bit sig _ a [ i ] and sig _ b [ i ] of a signal connected to the A, B input end of the RTL level Cell object to the two input ends of the ith logic gate level Cell object, and assigning the ith bit Y output end signal sig _ Y [ i ] of the RTL level Cell object to the output end of the ith logic gate level Cell object;
step 3.3.3: judging whether the bit widths of sig _ a and sig _ b signals are consistent, if so, ending, otherwise, acquiring the larger bit width of sig _ a and sig _ b, assigning the value of the larger bit width to a temporary object extra _ sig, calculating the bit width to be M, circulating i from N +1 to M ending, continuously creating M-N unit-wide logic gate level Cell objects, assigning extra _ sig [ i ] to one input port of the M-N logic gate level Cell objects, and assigning sig _ y [ i ] to an output port.
6. The method of claim 5, wherein the optimization of the plurality of single-bit-wide logic gate level Cell objects with carry input and carry output ports per RTL level data object is performed by:
when one input port connection signal of the logic gate level object is a fixed 0, judging whether a carry signal exists:
if not, deleting the current logic gate Cell object, and connecting another input port signal with an output port signal;
if so, connecting the carry signal to an input port of a current logic gate-level object connection fixed 0 signal, and clearing the carry signal;
when one input port connection signal of the logic gate level object is a fixed 1, judging whether the same port of the logic gate level object adjacent to the next bit of the current logic gate level object is connected with a fixed 0 signal or not,
if yes, deleting the current logic gate Cell object, saving the original signal of the input signal at the other end as a carry signal for standby, and connecting the negation signal with the output port signal;
if not, clearing the input port signal of the current logic gate object connected with the fixed 1 and correspondingly modifying the LUT parameter.
7. The method according to claim 1, wherein the specific method of step 4 is as follows:
step 4.1: describing the mapping relation of the logic gate level object to the physical gate level object in a cells _ map.v library file in verilog format,
step 4.2: analyzing the library file to obtain the mapping relation from the logic gate level object to the physical gate level object, wherein the mapping relation comprises the number of calling physical gate level instances and the mapping relation between ports and parameters in the logic gate level module;
step 4.3: after the logical gate-level Cell object set is obtained, data conversion from the logical gate-level Cell object set to the physical gate-level object set is completed according to the mapping relation, and information transmission of ports and parameters is completed;
step 4.4: and printing a logic netlist file containing the physical gate-level object set according to a specified output format.
8. The Field Programmable Gate Array (FPGA) logic synthesis device for realizing summation operation based on yosys is characterized by comprising the following modules:
a syntax tree generation module: the syntax tree is generated by analyzing the behavioral level user circuit description file of the summation operation by using a yosys open source program;
the RTL level data object extraction module: the system comprises a syntax tree generation module, a syntax tree generation module and a summation function module, wherein the syntax tree generation module is used for generating a syntax tree;
a logic gate level object generation module: the system comprises a RTL level data object set, a logic gate level Cell object set and a carry signal set, wherein the RTL level data object set is used for traversing the RTL level data object set, converting each RTL level data object in the RTL level data object set into a plurality of single-bit-width logic gate level Cell objects with carry input ports and carry output ports, newly building a Wire type carry signal representing summation operation while newly building the logic gate level Cell objects, and taking the carry signal as an operand;
a logic netlist file output module: and the logic gate level object generating module is used for mapping all the logic gate level objects converted by the logic gate level object generating module into a physical gate level object printing and extracting a logic netlist file.
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