CN116132232A - Multipath parallel up-sampling method for high-speed digital communication - Google Patents
Multipath parallel up-sampling method for high-speed digital communication Download PDFInfo
- Publication number
- CN116132232A CN116132232A CN202111348600.3A CN202111348600A CN116132232A CN 116132232 A CN116132232 A CN 116132232A CN 202111348600 A CN202111348600 A CN 202111348600A CN 116132232 A CN116132232 A CN 116132232A
- Authority
- CN
- China
- Prior art keywords
- parallel
- interpolation
- sampling
- data
- paths
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 129
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004891 communication Methods 0.000 title claims abstract description 21
- 238000012545 processing Methods 0.000 claims description 5
- 238000013507 mapping Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 5
- 238000001228 spectrum Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012952 Resampling Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Analogue/Digital Conversion (AREA)
- Complex Calculations (AREA)
Abstract
The invention provides a multipath parallel up-sampling method for high-speed digital communication, which comprises the following steps: s1: determining data sampling enabling at each moment and interpolation factors at each moment according to the input sampling rate and the output sampling rate of the up-sampling system; s2: according to the data sampling enabling, carrying out cache rectification on each path of parallel input data in N paths to obtain K paths of parallel effective data; s3: shifting K paths of parallel effective data into N interpolation registers respectively according to data sampling enabling to obtain N groups of interpolation base points at the moment; s4: and (3) carrying out parallel interpolation on the N groups of interpolation base points by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results. The multipath parallel up-sampling device provided by the invention can stably work within 250MHz of the FPGA system clock, when the number N of parallel paths is increased, the resource occupancy rate of a program only linearly increases, and up-sampling conversion within extremely high sampling rate can be realized.
Description
Technical Field
The invention belongs to the technical field of digital communication, and particularly relates to a multipath parallel up-sampling method for high-speed digital communication.
Background
It is often desirable in the field of high-speed digital communications to produce signals at any symbol rate. For sample rate conversion, it is common to change the clock frequency or oversample and re-extract the signal, but both methods have high complexity in hardware implementation and consume large hardware resources, and are therefore unsuitable for generating signals with a wide range of symbol rates.
If the clock frequency is not changed, a time domain interpolation method is generally adopted to realize variable sampling, namely various curves are utilized to fit an input sampling value sequence in the time domain, so as to obtain a time-varying coefficient in a digital resampling basic equation, and further obtain the impulse response of an interpolation filter.
For any fractional-multiple transform, the use of a polyphase structure results in a large and uncontrollable number of polyphase sub-filters, and therefore a large capacity ROM memory filter is required to implement fractional-and integer-multiple filters. In order to solve the problems, a Farrow structure is generally adopted to realize resampling of any small multiple, and only one variable interpolation factor mu is required to be transmitted for calculating one interpolation value m From mu m And the interpolation value is directly calculated by the input sampling point, so that the intermediate filter coefficient is not required to be calculated, and the hardware implementation is more convenient.
The main interpolation methods mainly comprise linear interpolation, sample hold interpolation, lagrange interpolation, novel parabolic interpolation, triangular interpolation and the like. Among the various interpolation methods, cubic interpolation is closest to the ideal characteristic, while Piecewise Parabolic Interpolation (PPI) is between linear and cubic interpolation algorithms in complexity, and near ideal interpolation effects can be obtained by reasonably adjusting design parameters.
In the first prior art, 2019, patent "a method and a system for implementing an FPGA of a filter of a FARROW type" (application No. 201910124543.7, publication No. CN109905100 a) provides a method and a system for implementing an FPGA of a filter of a FARROW type. The method comprises the following steps: firstly, quantizing filter coefficients of a FARROW filter; second, calculate the error interval u in real time k Corresponding interpolationA base point, and performing multiply-accumulate operation on the interpolation base point and the coefficient; third, multiply-accumulate result and error interval u k And performing multiply-add operation to obtain output. This patent can achieve basic variable symbol rate interpolation, but has several disadvantages: firstly, the interpolator in the patent adopts a 4-order Lagrangian interpolator, and the interpolation result and the theoretical interpolation result have larger errors; second, the processing flows of the patent are all serial, and cannot meet the requirement of high-speed digital communication.
In the second prior art, 2021, patent "a variable symbol rate, arbitrary path parallel input interpolation method" (application number: 202110085533.4, publication number: CN112905946 a) discloses a variable symbol rate, arbitrary path parallel input interpolation method. The method comprises the following steps: firstly, an upper computer inputs control parameters to determine parallel numbers P; secondly, sequentially reading out P paths of data from the RAM; third, calculate the error interval u k The method comprises the steps of carrying out a first treatment on the surface of the Fourth, substituting formula
Calculating to obtain corresponding output y sum Values. The patent focuses on how to obtain a sample point by interpolation on P paths of continuous data, and for the case of N paths of parallel output, the patent performs N-1 paths on the basis, but in the actual processing process, the input data of the N-1 paths has obvious correlation with the input data of the 1 st path, the same 1-group RAM read data is not in line with the requirement of multi-path data interpolation, namely, the phase continuity cannot be ensured by only multiplexing N paths of data obtained by an interpolator for N times. Moreover, the variable sampling rate must be performed on the basis of the up-sampled signal, otherwise, in-band consistency of the wideband signal is affected, for example, under the conditions of an operating clock frequency of 200MHz and a typical 4-fold raised cosine roll-off filter, only high-speed digital signals within 400MBaud symbol rate can be processed by adopting parallel resampling of up to 8 paths.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a multipath parallel up-sampling method for high-speed digital communication, which comprises the following steps:
the invention provides a multipath parallel up-sampling method in high-speed digital communication, which is applied to an up-sampling system, wherein the up-sampling system comprises a parallel numerical control oscillator, a rectifier, an interpolation register and a segmented parabolic interpolator, and the multipath parallel up-sampling method comprises the following steps:
s1: determining data sampling enabling of the enabling rectifier and the interpolation register at each moment and an interpolation factor for interpolation of the segmented parabolic interpolator at each moment according to an input sampling rate and an output sampling rate of the up-sampling system;
s2: according to the data sampling enable at each moment, carrying out cache rectification on each path of parallel input data in N paths in the up-sampling system to obtain K paths of parallel effective data with the sampling depth of K;
s3: for each moment, according to the data sampling enabling, shifting the K paths of parallel effective data to N interpolation registers respectively to obtain N groups of interpolation base points at the moment;
s4: and carrying out parallel interpolation on the N groups of interpolation base points based on the interpolation factors by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results.
Optionally, before step S1, the multi-path parallel upsampling method further includes:
processing the mapping symbol through at least 2 times of raised cosine roll-off filter SRRC to obtain a bandwidth signal;
and taking the bandwidth signal as input data of the up-sampling system.
Optionally, step S1 includes:
s11: initializing nt s Iteration parameter R of the parallel numerical control oscillator at moment μ (n)| n＝0 =0, and calculates the sampling ratio i=f of the input and output of the up-sampling system in /f out ；
S12: calculating the accumulated result of the iteration parameters of each path of the up-sampling system
And at the same time calculate +.>
Wherein m is more than or equal to 1 and less than or equal to N;
s13: calculating intermediate variables
wherein ,
representing a downward rounding;
s14: calculating interpolation factors
S15: calculating data sample enable valid m (n) judging
And->
Whether or not to be equal, valid when equal m (n) =1 otherwise valid m (n) =0, yielding nt s Time-of-day data sampling enable and interpolation factor mu m (n)；
S16: order the
Juxtaposing n=n+1, returning to step S12 to calculate the data sampling enable and interpolation factor at the next moment;
wherein N represents the sampling time, m represents the mth path of N paths, N represents the parallel path number of the up-sampling system, t s Representing the output sampling interval, t s ＝N/f out 。
Optionally, a modulator is connected before the up-sampling system, the rectifier includes a RAM controller and a shift register, and the S2 includes:
s21: caching each path of parallel input data in N paths by using a RAM controller;
s22: the shift register determines reading enabling and an output position of the shift register according to the data sampling enabling;
s23: according to the read enabling, the up-sampling system is read according to the requirement, and the duty ratio is equal to f in /f out Is input in parallel with the input data;
s24: the shift register carries out shift caching on each path of parallel input data read by the RAM controller;
the length of the shift register is 3N to 4N;
s25: and the shift register outputs K paths of parallel effective data according to the output position.
Optionally, the method is characterized in that,
the S22 includes:
s221: the shift register initializes the data pointer position to Addr (n) | n＝0 ＝0,flag＝0；
S222: shift register computation nt s Total number of data sampling enable 1 in N paths at moment
S223: update data pointer position Addr (n+1) =addr (n) +s valid (n)+flag；
S224: judging whether addr (n+1) is larger than N, if so, setting a reading enabling value to be 1, and reading data from the RAM controller; if less than N, flag=0, the read enable is set to 0 to update flag.
Optionally, step S24 includes:
if the RAM controller reads parallel input data according to the reading enabling, the shift register shifts rightwards, and the read parallel input data are put into a memory of the shift register one by one from left to realize shift caching;
the step S25 includes:
sequentially reading N paths of data from the current pointer position Addr (N) to the address increasing direction to be output;
wherein the first K paths of the N paths of data are parallel effective data, and k=s valid (n); the flag indicates the number of pointer position jumps.
Optionally, after the step S25, the method further includes:
s26: the RAM controller receives the data block continuously sent by the modulator, and feeds back the flag bit to the modulator according to the address difference between the self write address and the read address, so that the modulator outputs the data block to the RAM controller after adjusting the duty ratio of the self output data block.
Optionally, the step S3 includes:
s31: initializing a stored value R of an interpolation register interp (n)| n＝0 ＝[0,0,0,0,0,0,0,0]；
S32: calculating nt s Number of 1 in L data sample enable before moment
1≤L≤N；
S33: for each group at each instant, the interpolation register R is executed interp (n) right shift P L Bits, N groups of interpolation base points X at the moment are obtained L (n)；
Wherein L represents any one of N groups;
s34: let the stored value R interp (n+1)＝X N (N), juxtaposing n=n+1, returning to S32, and obtaining N groups of interpolation base points at each moment.
Optionally, the S33 includes:
s331: when P L When the number of the P paths is less than or equal to 8, the lowest P is taken out from the K paths of parallel effective data L The bit data is put into an interpolation register from the left;
wherein the high order is to the left;
s332: when P L >8, take out position P L ,P L -1,P L -2，…,P L -7 the 8 bits of data are placed in sequence into an interpolation register, wherein the upper bits P L On the left;
s333: repeatedly executing S331 to S332N times with L being more than or equal to 1 and N being less than or equal to each other to obtain N groups of interpolation base points X at each moment L (n)。
Optionally, the S4 includes:
s41: calculating intermediate variables of a segmented parabolic interpolator
wherein ,Cxy Interpolation coefficient, X, representing a segmented parabolic interpolator L Representing the interpolation base point of the L group; mu (mu) L Representing interpolation factors of the L group;
s42: the segment parabolic interpolator calculates the output result y of the L-th path of the up-sampling system L ＝Mult1 L +μ L *(Mult2 L +μ L *(Mult3 L +μ L *Mult4 L ))。
The beneficial effects of the invention include:
(1) The multipath parallel up-sampling method in high-speed digital communication provided by the invention can realize the change of the interpolation parallel path number N by only changing the bit width of a register and the parallel quantity of an interpolator, has high flexibility and expandability, and can reach 64;
(2) The invention provides a multipath parallel up-sampling method in high-speed digital communication, which supports that the highest symbol rate can reach 3Gbaud under 64 paths of parallel conditions;
(3) The multi-channel parallel up-sampling method in high-speed digital communication uses a full parallel structure, calculates control parameters in real time with linear complexity, and meets the control requirement under high parallel channel number;
(4) The multipath parallel up-sampling method in high-speed digital communication provided by the invention realizes interpolation by adopting the interpolation mode of the segmented parabolic interpolator, and has higher interpolation precision compared with the prior art.
Drawings
FIG. 1 is a flow chart of a multi-path parallel upsampling method in high speed digital communication according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a sampling process implemented by an upsampling system according to an embodiment of the present invention;
FIG. 3 is a block diagram of an implementation of an interpolation shift register in a multi-path parallel upsampling method in high speed digital communication according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a 32-order segmented parabolic interpolator implementing interpolation according to an embodiment of the present invention;
FIG. 5 is a spectrum variation diagram of a multi-channel parallel upsampling method in high speed digital communication under 64APSK modulation according to an embodiment of the present invention;
fig. 6 is a graph showing MSE performance contrast between multiple interpolators under QPSK modulation in a multi-path parallel upsampling method in high-speed digital communication according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In view of the problems existing in the prior art, the present invention provides a multi-path parallel upsampling method in high-speed digital communication, and the present invention is described in detail below with reference to the accompanying drawings.
The variable N appearing in the invention is the number of parallel paths, the upper bound can reach 64, m and L both represent one path of N paths and are mutually independent, K represents superposition of sampling enabling, the relation that K is more than or equal to 1 and less than or equal to N is satisfied, N represents the number of sampling moments, and N is more than or equal to 0 and t is satisfied s To output the sampling interval, t s ＝N/f out 。
As shown in fig. 1, the multi-path parallel up-sampling method in high-speed digital communication provided by the invention is applied to an up-sampling system, the up-sampling system comprises a parallel numerically controlled oscillator, a rectifier, an interpolation register and a segmented parabolic interpolator, and the multi-path parallel up-sampling method comprises the following steps:
s1: determining the data sampling enable for enabling the rectifier and interpolation register at each time and the interpolation factor μ for interpolation by the segmented parabolic interpolator at each time based on the input and output sampling rates of the upsampling system m (1≤m≤N)；
A parallel Numerically Controlled Oscillator (NCO) implements the interpolation factor and data sample enable calculations in this step. The interpolation register comprises a controller and a memory, wherein the controller controls the memory to carry out shift storage, and the memory is used for storing data in the interpolation process.
S2: according to the data sampling enable at each moment, carrying out cache rectification on each path of parallel input data in N paths in an up-sampling system to obtain K paths of parallel effective data with the sampling depth of K;
in the concrete implementation, the rectification of the real-time variable data with the effective length and the effective position is realized by adopting the two-stage rectification of the RAM controller and the shift register, and signals are fed back to the front-stage modulator module so as to keep the consistency of data throughput.
S3: for each moment, according to data sampling enabling, shifting K paths of parallel effective data into N interpolation registers respectively to obtain N groups of interpolation base points at the moment;
s4: and (3) performing parallel interpolation on the N groups of interpolation base points based on interpolation factors by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results.
The invention provides a multipath parallel up-sampling method for high-speed digital communication, which comprises the following steps: s1: determining data sampling enabling at each moment and interpolation factors at each moment according to the input sampling rate and the output sampling rate of the up-sampling system; s2: according to the data sampling enabling, carrying out cache rectification on each path of parallel input data in N paths to obtain K paths of parallel effective data; s3: shifting K paths of parallel effective data into N interpolation registers respectively according to data sampling enabling to obtain N groups of interpolation base points at the moment; s4: and (3) carrying out parallel interpolation on the N groups of interpolation base points by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results. The multipath parallel up-sampling device provided by the invention can stably work within 250MHz of the FPGA system clock, when the number N of parallel paths is increased, the resource occupancy rate of a program only linearly increases, and up-sampling conversion within extremely high sampling rate can be realized.
As an optional embodiment of the present invention, before step S1, the multi-path parallel upsampling method further includes:
step one: processing the mapping symbol through at least 2 times of raised cosine roll-off filter SRRC to obtain a bandwidth signal;
step two: the bandwidth signal is used as input data for the up-sampling system.
Referring to fig. 2, as an alternative embodiment of the present invention, the implementation procedure of step S1 includes:
s11: initializing nt s Iteration parameter R of time-of-day parallel numerical control oscillator μ (n)| n＝0 =0, and calculates the sampling ratio i=f of the input and output of the up-sampling system in /f out ；
It should be noted that, after the first explanation of the nts time, n is used for brevity to identify the nts time in subsequent brackets for convenience of description.
S12: calculating accumulated results of each path of iteration parameters of up-sampling system
And at the same time calculate +.>
Wherein m is more than or equal to 1 and less than or equal to N;
s13: calculating intermediate variables
wherein ,
representing a downward rounding;
s14: calculating interpolation factors
S15: calculating data sample enable valid m (n) judging
And->
Whether or not to be equal, valid when equal m (n) =1 otherwise valid m (n) =0, yielding nt s Time-of-day data sampling enable and interpolation factor mu m (n)；
S16: order the
Juxtaposing n=n+1, returning to step S12 to calculate the data sampling enable and interpolation factor at the next moment;
wherein N represents the sampling time, m represents the mth path of N paths, N represents the parallel path number of the up-sampling system, and t s Representing the output sampling interval, t s ＝N/f out 。
Noteworthy are: data sampling enabled valid m And interpolation factor mu m (1.ltoreq.m.ltoreq.N) is calculated in one time, but μ N The calculation of (a) needs multiple iterations and cannot be directly realized in the FPGA, so that the calculation is realized by adopting parallel results, and the accumulated value is calculated in parallel at each sampling moment
According to adjacent two->
Whether or not to sample is judged by the carry or not of (C) and +.>
Is used as the basic interpolation factor of each path +.>
Finally, the interpolation factor->
wherein ,Rμ For the interpolation factor register, the interpolation factor of the last path of each sampling moment is stored, i=f in /f out ，f in For the input signal sampling rate, f out For the output signal sampling rate.
In one embodiment of the present invention, a modulator is connected before the up-sampling system, the rectifier includes a RAM controller and a shift register, and S2 includes:
s21: caching each path of parallel input data in N paths by using a RAM controller;
s22: the shift register determines the output position of the shift register according to the data sampling enabling;
noteworthy are: the shift register comprises a controller and a memory, wherein the shift register controller is used for controlling shift and controlling the memory to store, and the memory is used for shifting generated data.
S23: the on-demand read-on-demand input up-sampling system according to the read enable satisfies the duty ratio equal to f in /f out Is input in parallel with the input data;
s24: the shift register carries out shift caching on each path of parallel input data read by the RAM controller;
the length of the shift register is 3N to 4N;
in the step, if the RAM controller reads parallel input data according to the reading enabling, the shift register shifts rightwards, and the read parallel input data are put into a memory of the shift register one by one from left to realize shift caching;
s25: and the shift register outputs K paths of parallel effective data according to the output position.
The width of the RAM controller is the total bit width of N paths of parallel signals, and the depth is required to be larger than the length of each block of continuous data.
In this step, N paths of data may be sequentially read as output from the current pointer position Addr (N) toward the address increasing direction.
Wherein the first K paths in the N paths of data are parallel effective data, and k=s valid (n); the flag indicates the number of pointer position jumps.
Noteworthy are: when up sampling multiple f out /f in When the continuous data length is fixed at any multiple, the duty ratio of the data and f in /f out Possibly due to loss of localization in an alternative embodiment of the invention, S22 comprises:
s221: the shift register initializes the data pointer position to Addr (n) | n＝0 ＝0,flag＝0；
S222: shift register computation nt s Total number of data sampling enable 1 in N paths at moment
S223: update data pointer position Addr (n+1) =addr (n) +s valid (n)+flag；
S224: judging whether addr (n+1) is larger than N, if so, setting a reading enabling value to be 1, and reading data from the RAM controller; if less than N, flag=0, the read enable is set to 0 to update flag.
As an optional embodiment of the present invention, after S25, the multi-path parallel upsampling method of the present invention further includes:
s26: the RAM controller receives the data block continuously sent by the modulator, and feeds back the flag bit to the modulator according to the address difference between the self write address and the read address, so that the modulator outputs the data block to the RAM controller after adjusting the duty ratio of the self output data block.
Noteworthy are: when up sampling multiple f out /f in When the continuous data length is fixed at any multiple, the duty ratio of the data and f in /f out The fixed point loss can not ensure complete consistency, at this time, the controller should round down the hollow clock number in the duty ratio, so that a slight accumulation phenomenon occurs in the data, when the accumulated data is greater than a certain threshold value, the RAM controller feeds back a flag bit to the modulator according to the address difference between the RAM write address and the read address, and increases the number of the hollow clock of the current data block, so as to maintain the stability of the data amount in the RAM and consistency of throughput.
Referring to fig. 3, in an alternative embodiment of the present invention, the implementation procedure of step S3 includes:
s31: initializing a stored value R of an interpolation register interp (n)| n＝0 ＝[0,0,0,0,0,0,0,0]；
S32: calculating nt s Number of 1 in L data sample enable before moment
1≤L≤N；
S33: for each group at each instant, the interpolation register R is executed interp (n) right shift P L Bits, N groups of interpolation base points X at the moment are obtained L (n)；
In an alternative embodiment of the present invention, S33 includes:
s331: when P L When the number of the P paths is less than or equal to 8, the lowest P is taken out from the K paths of parallel effective data L The bit data is put into an interpolation register from the left;
wherein the high order is to the left;
s332: when P L >8, take out position P L ,P L -1,P L -2，…,P L -7 the 8 bits of data are placed in sequence into an interpolation register, wherein the upper bits P L On the left;
s333: repeating with 1-L-NS331 to S332 are performed N times to obtain N groups of interpolation base points X at each moment L (n)。
Wherein L represents any one of N groups;
s34: let the stored value R interp (n+1)＝X M (N), juxtaposing n=n+1, returning to S32, and obtaining N groups of interpolation base points at each moment.
K-way valid data (0<K.ltoreq.N) shift sharing into N interpolation registers
Under different conditions, when N is increased, the judgment condition is exponentially increased, and the application requirement of the highway parallelism cannot be met, so that a segmentation method is adopted, interpolation positions of K effective data are independently calculated, and the first L valid values given in the step S1 at each sampling moment are counted m The number of 1->
And according to->
The data in the interpolation register is shifted to obtain an interpolation base point X L And executing N times in parallel with L being more than or equal to 1 and less than or equal to N, so as to obtain N groups of interpolation base points.
Referring to fig. 4, in an alternative embodiment of the present invention, S4 includes:
s41: calculating intermediate variables of a segmented parabolic interpolator
wherein ,Cxy Interpolation coefficient, X, representing a segmented parabolic interpolator L Representing the interpolation base point of the L group; mu (mu) L Representing interpolation factors of the L group;
s42: calculating the output result y of the L-th path of the up-sampling system by the segmented parabolic interpolator L ＝Mult1 L +μ L *(Mult2 L +μ L *(Mult3 L +μ L *Mult4 L ))。
The fixed-point interpolation coefficient of the 32-order segmented parabolic interpolator is shown in table 1:
table 1 fixed-point interpolation coefficients for 32-order segmented parabolic interpolators
| C xy (0X) | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 1 | FF36 | 0314 | F647 | 276E | 276E | F647 | 0314 | |
| 2 | FFC9 | 00F7 | FC10 | 285F | D7A0 | 03EF | FF08 | 0036 |
| 3 | 00C9 | FCEB | 09B8 | F891 | F891 | 09B8 | FCEB | 00C9 |
| 4 | 0036 | FF08 | 03EF | F7A0 | 085F | FC10 | 00F7 | FFC9 |
The fixed bit width is 2.14, which represents a 1-bit symbol, a 1-bit integer, and 14 is a decimal.
The set of coefficients has symmetry, including:
(1)C 1j ＝-C 3j ，C 2j ＝-C 4j ，j∈{1,2,3,6,7,8}；
(2)C ij ＝C i(8-j) ，i∈{1,3}，j∈{1,2,3,4}；
(3)C ij ＝-C i(8-j) ，i∈{2,4}，j∈{1,2,3,4}；
the implementation block diagram of each path of step S4 is shown in fig. 4, and the implementation process is simplified by using the symmetry of the coefficients of table 1, and the implementation block diagram comprises the following steps:
for X L Performing butterfly addition and subtraction operations, i.e.
[Add L ] T 8*1 ＝[X L ] T 8*1 +fliplr([X L ] T 8*1 )；
[Minus L ] T 8*1 ＝[X L ] T 8*1 -fliplr([X L ] T 8*1 )；
Respectively taking the first 4 bits of the vector reverse operation and splicing the first 4 bits of the vector reverse operation as output of the step, wherein the flip (·) represents vector reverse operation;
calculation of Mult4 L ＝[C 41 C 42 C 43 C 44 ]*[Minus L ] T 4*1 ；
Mult3 L ＝[C 31 C 32 C 33 C 34 ]*[Add L ] T 4*1 ；
Mult2 L ＝[C 41 C 42 C 43 C 24 ]*[Minus L ] T 4*1 ；
Mult1 L ＝[C 31 C 32 C 33 C 14 ]*[Add L ] T 4*1 ；
Each path of step S4 requires 13 multipliers and 23 adders in total.
The technical effects of the present invention will be further described with reference to simulation experiments.
Simulation conditions:
the software simulation experiment is carried out under MATLAB 2020b software, the hardware simulation experiment is carried out under Vivado2018.3 software, an FPGA chip is selected as VC709, a QPSK/64APSK modem system is taken as an example, the roll-off factor alpha=0.35 of SRRC filtering is adopted, the up-sampling multiple is 4, the simulation channel is an additive Gaussian white noise channel, a 32-order PPI interpolation filter is adopted by an interpolator, and a cubic interpolation and a typical parabolic interpolation are adopted by a contrast interpolator.
Simulation content and result analysis:
and adopting a 64APSK modulation mode, and taking 1.8508 by up-sampling multiple. Fig. 5 is a spectrum change situation of a multi-path parallel upsampling method under a noise-free situation, where a sub-graph a in fig. 5 is a signal spectrum before upsampling, and a sub-graph b is a signal spectrum after upsampling. In fig. 5, the abscissa represents the digital frequency and the ordinate represents the power spectral density. It can be seen that the symbol rate is not changed while the sampling rate is 1.8508 times, and the side lobe attenuation of the output power spectrum is more than 40dB, thereby meeting the transmission requirement of digital signals.
By adopting a QPSK modulation mode, the up-sampling multiple is 1.11-10 times, and FIG. 6 is a mean square error comparison chart of interpolation points and ideal interpolation points obtained by the multipath parallel up-sampling method according to the embodiment of the invention, wherein the abscissa represents the iteration value I=f of the interpolation factor in /f out The ordinate represents the MSE of the interpolation point and the ideal point, and the interpolation precision of the 32-order segmented parabolic interpolator is obviously larger than that of the typical parabolic interpolation and the cubic interpolation commonly used in the current literature.
Through Vivado2018.3 comprehensive realization, when N is taken to be 16, the resources occupied by the N-path parallel up-sampling device provided by the invention are shown in the table 2, and the realization can be completed under the constraint of a 250MHz clock, so that up-sampling of any multiple under the sampling rate of 4Gsps can be satisfied. From the resource analysis, the invention can realize the parallel and above of 64 paths without changing the framework.
The modulator and the multipath parallel up-sampling device provided by the invention are realized in a VC709 board card, and when the up-sampling multiple is 1-4 times, the EVM performance can be satisfied with less than 3% through the actual measurement of an R & S FSW85 spectrometer.
Table 2 resource occupancy table
| Resource type | The occupied amount | Total amount of VC709 resources | Occupancy ratio |
| LUT | 35632 | 433200 | 8.23％ |
| FF | 24411 | 866400 | 2.82％ |
| Slice | 10962 | 108000 | 10.15％ |
| BRAM | 7.5 | 1470 | 0.51％ |
| DSP | 416 | 3600 | 11.56％ |
The foregoing is merely illustrative of specific embodiments of the present invention, and the scope of the invention is not limited thereto, but any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention will be apparent to those skilled in the art within the scope of the present invention.
Claims (10)
1. The multi-channel parallel up-sampling method in high-speed digital communication is characterized by being applied to an up-sampling system, wherein the up-sampling system comprises a parallel numerical control oscillator, a rectifier, an interpolation register and a segmented parabolic interpolator, and the multi-channel parallel up-sampling method comprises the following steps:
s1: determining data sampling enabling of the enabling rectifier and the interpolation register at each moment and an interpolation factor for interpolation of the segmented parabolic interpolator at each moment according to an input sampling rate and an output sampling rate of the up-sampling system;
s2: according to the data sampling enable at each moment, carrying out cache rectification on each path of parallel input data in N paths in the up-sampling system to obtain K paths of parallel effective data with the sampling depth of K;
s3: for each moment, according to the data sampling enabling, shifting the K paths of parallel effective data to N interpolation registers respectively to obtain N groups of interpolation base points at the moment;
s4: and carrying out parallel interpolation on the N groups of interpolation base points based on the interpolation factors by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results.
2. The multi-path parallel upsampling method according to claim 1, characterized in that before step S1, the multi-path parallel upsampling method further comprises:
processing the mapping symbol through at least 2 times of raised cosine roll-off filter SRRC to obtain a bandwidth signal;
and taking the bandwidth signal as input data of the up-sampling system.
3. The multi-path parallel upsampling method according to claim 1, wherein step S1 comprises:
s11: initializing nt s Iteration parameter R of the parallel numerical control oscillator at moment μ (n)| n＝0 =0, and calculates the sampling ratio i=f of the input and output of the up-sampling system in /f out ；
S12: calculating the accumulated result of the iteration parameters of each path of the up-sampling system
And at the same time calculate +.>
Wherein m is more than or equal to 1 and less than or equal to N;
s13: calculating intermediate variables
wherein ,
representing a downward rounding;
s14: calculating interpolation factors
S15: calculating data sample enable valid m (n) judging
And->
Whether or not to be equal, valid when equal m (n) =1 otherwise valid m (n) =0, yielding nt s Time-of-day data sampling enable and interpolation factor mu m (n)；
S16: order the
Juxtaposing n=n+1, returning to step S12 to calculate the data sampling enable and interpolation factor at the next moment;
wherein N represents the sampling time, m represents the mth path of N paths, N represents the parallel path number of the up-sampling system, t s Representing the output sampling interval, t s ＝N/f out 。
4. The multi-path parallel upsampling method according to claim 1, wherein a modulator is connected before the upsampling system, the rectifier comprises a RAM controller and a shift register, and the S2 comprises:
s21: caching each path of parallel input data in N paths by using a RAM controller;
s22: the shift register determines reading enabling and an output position of the shift register according to the data sampling enabling;
s23: according to the read enabling, the up-sampling system is read according to the requirement, and the duty ratio is equal to f in /f out Is input in parallel with the input data;
s24: the shift register carries out shift caching on each path of parallel input data read by the RAM controller;
the length of the shift register is 3N to 4N;
s25: and the shift register outputs K paths of parallel effective data according to the output position.
5. The method of multiple parallel upsampling according to claim 4, wherein,
the S22 includes:
s221: shift register initialization data pointer locationAddr (n) | n＝0 ＝0,flag＝0；
S222: shift register computation nt s Total number of data sampling enable 1 in N paths at moment
S223: update data pointer position Addr (n+1) =addr (n) +s valid (n)+flag；
S224: judging whether addr (n+1) is larger than N, if so, setting a reading enabling value to be 1, and reading data from the RAM controller; if less than N, flag=0, the read enable is set to 0 to update flag.
6. The multi-path parallel upsampling method according to claim 5, wherein step S24 comprises:
if the RAM controller reads parallel input data according to the reading enabling, the shift register shifts rightwards, and the read parallel input data are put into a memory of the shift register one by one from left to realize shift caching;
the step S25 includes:
sequentially reading N paths of data from the current pointer position Addr (N) to the address increasing direction to be output;
wherein the first K paths of the N paths of data are parallel effective data, and k=s valid (n); the flag indicates the number of pointer position jumps.
7. The multi-path parallel upsampling method according to claim 1, wherein after said S25, said method further comprises:
s26: the RAM controller receives the data block continuously sent by the modulator, and feeds back the flag bit to the modulator according to the address difference between the self write address and the read address, so that the modulator outputs the data block to the RAM controller after adjusting the duty ratio of the self output data block.
8. The multi-path parallel upsampling method according to claim 1, wherein said S3 comprises:
s31: initializing a stored value R of an interpolation register interp (n)| n＝0 ＝[0,0,0,0,0,0,0,0]；
S32: calculating nt s Number of 1 in L data sample enable before moment
1≤L≤N；
S33: for each group at each instant, the interpolation register R is executed interp (n) right shift P L Bits, N groups of interpolation base points X at the moment are obtained L (n)；
Wherein L represents any one of N groups;
s34: let the stored value R interp (n+1)＝X N (N), juxtaposing n=n+1, returning to S32, and obtaining N groups of interpolation base points at each moment.
9. The multi-path parallel upsampling method according to claim 8, wherein said S33 comprises:
s331: when P L When the number of the P paths is less than or equal to 8, the lowest P is taken out from the K paths of parallel effective data L The bit data is put into an interpolation register from the left;
wherein the high order is to the left;
s332: when P L >8, take out position P L ,P L -1,P L -2，…,P L -7 the 8 bits of data are placed in sequence into an interpolation register, wherein the upper bits P L On the left;
s333: repeatedly executing S331 to S332N times with L being more than or equal to 1 and N being less than or equal to each other to obtain N groups of interpolation base points X at each moment L (n)。
10. The multi-path parallel upsampling method according to claim 1, wherein said S4 comprises:
s41: calculating intermediate variables of a segmented parabolic interpolator
wherein ,Cxy Interpolation coefficient, X, representing a segmented parabolic interpolator L Representing the interpolation base point of the L group; mu (mu) L Representing interpolation factors of the L group;
s42: the segment parabolic interpolator calculates the output result y of the L-th path of the up-sampling system L ＝Mult1 L +μ L *(Mult2 L +μ L *(Mult3 L +μ L *Mult4 L ))。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111348600.3A CN116132232B (en) | 2021-11-15 | 2021-11-15 | Multipath parallel up-sampling method for high-speed digital communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111348600.3A CN116132232B (en) | 2021-11-15 | 2021-11-15 | Multipath parallel up-sampling method for high-speed digital communication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116132232A true CN116132232A (en) | 2023-05-16 |
| CN116132232B CN116132232B (en) | 2024-04-19 |
Family
ID=86310548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111348600.3A Active CN116132232B (en) | 2021-11-15 | 2021-11-15 | Multipath parallel up-sampling method for high-speed digital communication |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116132232B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592103A (en) * | 2003-08-30 | 2005-03-09 | 华为技术有限公司 | N step half-band interpolating filter |
| US7340024B1 (en) * | 2003-10-22 | 2008-03-04 | L3 Communications Corporation | Parallel fractional interpolator with data-rate clock synchronization |
| CN101383641A (en) * | 2007-09-06 | 2009-03-11 | 三星电机株式会社 | A digital linc transmitter with non-linear element |
| CN101458329A (en) * | 2009-01-06 | 2009-06-17 | 清华大学 | Time-domain paralleling sampling rate transformation method |
| CN102064797A (en) * | 2010-11-12 | 2011-05-18 | 清华大学 | Parallel implementation method and device for fractional sampling rate transformation |
| CN104821927A (en) * | 2015-04-27 | 2015-08-05 | 西安空间无线电技术研究所 | Multiplied-sampling-based parallel burst signal detection system in burst demodulation |
| CN106506135A (en) * | 2016-10-18 | 2017-03-15 | 华中科技大学 | A kind of digital time-domain parallel timing synchronization sytem of gigabit speed and method |
| CN111510110A (en) * | 2020-04-30 | 2020-08-07 | 上海大学 | Interpolation matched filtering method and filter for parallel processing |
| CN111767687A (en) * | 2020-06-30 | 2020-10-13 | 成都博宇利华科技有限公司 | Multi-channel parallel data sampling system and method |
-
2021
- 2021-11-15 CN CN202111348600.3A patent/CN116132232B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592103A (en) * | 2003-08-30 | 2005-03-09 | 华为技术有限公司 | N step half-band interpolating filter |
| US7340024B1 (en) * | 2003-10-22 | 2008-03-04 | L3 Communications Corporation | Parallel fractional interpolator with data-rate clock synchronization |
| CN101383641A (en) * | 2007-09-06 | 2009-03-11 | 三星电机株式会社 | A digital linc transmitter with non-linear element |
| CN101458329A (en) * | 2009-01-06 | 2009-06-17 | 清华大学 | Time-domain paralleling sampling rate transformation method |
| CN102064797A (en) * | 2010-11-12 | 2011-05-18 | 清华大学 | Parallel implementation method and device for fractional sampling rate transformation |
| CN104821927A (en) * | 2015-04-27 | 2015-08-05 | 西安空间无线电技术研究所 | Multiplied-sampling-based parallel burst signal detection system in burst demodulation |
| CN106506135A (en) * | 2016-10-18 | 2017-03-15 | 华中科技大学 | A kind of digital time-domain parallel timing synchronization sytem of gigabit speed and method |
| CN111510110A (en) * | 2020-04-30 | 2020-08-07 | 上海大学 | Interpolation matched filtering method and filter for parallel processing |
| CN111767687A (en) * | 2020-06-30 | 2020-10-13 | 成都博宇利华科技有限公司 | Multi-channel parallel data sampling system and method |
Non-Patent Citations (5)
| Title |
|---|
| DAKUA, P.K.; VARMA, A.S.N.; JHANSI, K.; NANDA, P.K.: "An optimized design of area delay power efficient architecture for reconfigurable FIR filter", 2016 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, COMMUNICATION, POWER AND EMBEDDED SYSTEM (SCOPES), 20 July 2017 (2017-07-20) * |
| 丁欣;徐以标;周洋;王兴;: "基于分段多项式拟合的数字信号插值方法", 指挥信息系统与技术, no. 04, 28 August 2018 (2018-08-28) * |
| 李浩;王志刚;王厚军;: "高速并行数字重采样控制算法研究", 微电子学与计算机, no. 03, 5 March 2017 (2017-03-05) * |
| 汪旭兴;闫江;吴旦昱;周磊;武锦;贾涵博;张飞;: "8GS/s-14bit RF-DAC中数字上变频器的ASIC实现", 微电子学与计算机, no. 01, 5 January 2020 (2020-01-05) * |
| 王祖良: "卫通高速数传解调技术研究", 中国优秀硕士学位论文全文数据库(信息科技辑), 15 June 2005 (2005-06-15) * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116132232B (en) | 2024-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9054412B2 (en) | Channel estimation filter normalization | |
| Chen et al. | Non-maximally decimated analysis/synthesis filter banks: Applications in wideband digital filtering | |
| Cooklev | An efficient architecture for orthogonal wavelet transforms | |
| Candan | An efficient filtering structure for Lagrange interpolation | |
| CN113346871B (en) | Multichannel multiphase multi-rate adaptive FIR digital filtering processing architecture | |
| WO2008034027A2 (en) | Processor architecture for programmable digital filters in a multi-standard integrated circuit | |
| CN104932992B (en) | A kind of flexible retransmission method of the variable Digital Microwave of bandwidth granularity | |
| Furtado et al. | On the design of high-complexity cosine-modulated transmultiplexers based on the frequency-response masking approach | |
| CN116132232B (en) | Multipath parallel up-sampling method for high-speed digital communication | |
| US20020013798A1 (en) | Low-power pulse-shaping digital filters | |
| CN114124034A (en) | High-speed parallel interpolation filter design based on FPGA | |
| CN111327382B (en) | Channel simulation architecture with variable amplitude, time delay bandwidth and delay and method thereof | |
| CN110957996B (en) | Multiplier-free FRM filter bank optimal design method based on ABC algorithm | |
| CN109815546B (en) | Implementation method of high-speed parallel digital matched filter | |
| US20110170639A1 (en) | Multiplier-less data processing techniques and related implementations adapted for use in polar modulator | |
| US9337805B2 (en) | Efficient digital microphone decimation filter architecture | |
| CN102420611B (en) | Sampling rate conversion method and device of digital signal | |
| CN102457251B (en) | Method and device for realizing universal digital filter | |
| US7236543B2 (en) | Method and apparatus of 8PSK modulation | |
| Yu et al. | Roundoff noise analysis of signals represented using signed power-of-two terms | |
| KR20070073462A (en) | Interpolating apparatus and method in digital communication system | |
| CN113872566B (en) | Modulation filtering device and method with continuously adjustable bandwidth | |
| JPH03235511A (en) | Automatic waveform equalizing system | |
| Bernocchi et al. | A hybrid RNS adaptive filter for channel equalization | |
| CN114337764B (en) | Universal method and system based on multiphase DFT digital channelized receiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |