CN116132232B - Multipath parallel up-sampling method for high-speed digital communication - Google Patents
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Abstract
The invention provides a multipath parallel up-sampling method for high-speed digital communication, which comprises the following steps: s1: determining data sampling enabling at each moment and interpolation factors at each moment according to the input sampling rate and the output sampling rate of the up-sampling system; s2: according to the data sampling enabling, carrying out cache rectification on each path of parallel input data in N paths to obtain K paths of parallel effective data; s3: shifting K paths of parallel effective data into N interpolation registers respectively according to data sampling enabling to obtain N groups of interpolation base points at the moment; s4: and (3) carrying out parallel interpolation on the N groups of interpolation base points by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results. The multipath parallel up-sampling device provided by the invention can stably work within 250MHz of the FPGA system clock, when the number N of parallel paths is increased, the resource occupancy rate of a program only linearly increases, and up-sampling conversion within extremely high sampling rate can be realized.
Description
Technical Field
The invention belongs to the technical field of digital communication, and particularly relates to a multipath parallel up-sampling method for high-speed digital communication.
Background
It is often desirable in the field of high-speed digital communications to produce signals at any symbol rate. For sample rate conversion, it is common to change the clock frequency or oversample and re-extract the signal, but both methods have high complexity in hardware implementation and consume large hardware resources, and are therefore unsuitable for generating signals with a wide range of symbol rates.
If the clock frequency is not changed, a time domain interpolation method is generally adopted to realize variable sampling, namely various curves are utilized to fit an input sampling value sequence in the time domain, so as to obtain a time-varying coefficient in a digital resampling basic equation, and further obtain the impulse response of an interpolation filter.
For any fractional-multiple transform, the use of a polyphase structure results in a large and uncontrollable number of polyphase sub-filters, and therefore a large capacity ROM memory filter is required to implement fractional-and integer-multiple filters. Aiming at the problems, a Farrow structure is generally adopted to realize resampling of any multiple, only one variable interpolation factor mu m is required to be transmitted for each interpolation value calculation, the interpolation value is directly calculated by mu m and an input sampling point, and the calculation of an intermediate filter coefficient is not required, so that the hardware implementation is facilitated.
The main interpolation methods mainly comprise linear interpolation, sample hold interpolation, lagrange interpolation, novel parabolic interpolation, triangular interpolation and the like. Among the various interpolation methods, cubic interpolation is closest to the ideal characteristic, while Piecewise Parabolic Interpolation (PPI) is between linear and cubic interpolation algorithms in complexity, and near ideal interpolation effects can be obtained by reasonably adjusting design parameters.
In the first prior art, 2019, patent "a method and a system for implementing an FPGA of a filter of a FARROW type" (application No. 201910124543.7, publication No. CN109905100 a) provides a method and a system for implementing an FPGA of a filter of a FARROW type. The method comprises the following steps: firstly, quantizing filter coefficients of a FARROW filter; secondly, calculating an error interval u k and a corresponding interpolation base point in real time, and performing multiply-accumulate operation on the interpolation base point and the coefficient; thirdly, the multiply-accumulate result is multiplied and added with the error interval u k to obtain output. This patent can achieve basic variable symbol rate interpolation, but has several disadvantages: firstly, the interpolator in the patent adopts a 4-order Lagrangian interpolator, and the interpolation result and the theoretical interpolation result have larger errors; second, the processing flows of the patent are all serial, and cannot meet the requirement of high-speed digital communication.
In the second prior art, 2021, patent "a variable symbol rate, arbitrary path parallel input interpolation method" (application number: 202110085533.4, publication number: CN112905946 a) discloses a variable symbol rate, arbitrary path parallel input interpolation method. The method comprises the following steps: firstly, an upper computer inputs control parameters to determine parallel numbers P; secondly, sequentially reading out P paths of data from the RAM; thirdly, calculating an error interval u k; fourth, substituting formulaAnd calculating to obtain a corresponding output y sum value. The patent focuses on how to obtain a sample point by interpolation on P paths of continuous data, and for the case of N paths of parallel output, the patent performs N-1 paths on the basis, but in the actual processing process, the input data of the N-1 paths has obvious correlation with the input data of the 1 st path, the same 1-group RAM read data is not in line with the requirement of multi-path data interpolation, namely, the phase continuity cannot be ensured by only multiplexing N paths of data obtained by an interpolator for N times. Moreover, the variable sampling rate must be performed on the basis of the up-sampled signal, otherwise, in-band consistency of the wideband signal is affected, for example, under the conditions of an operating clock frequency of 200MHz and a typical 4-fold raised cosine roll-off filter, only high-speed digital signals within 400MBaud symbol rate can be processed by adopting parallel resampling of up to 8 paths.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a multipath parallel up-sampling method for high-speed digital communication, which comprises the following steps:
the invention provides a multipath parallel up-sampling method in high-speed digital communication, which is applied to an up-sampling system, wherein the up-sampling system comprises a parallel numerical control oscillator, a rectifier, an interpolation register and a segmented parabolic interpolator, and the multipath parallel up-sampling method comprises the following steps:
S1: determining data sampling enabling of the enabling rectifier and the interpolation register at each moment and an interpolation factor for interpolation of the segmented parabolic interpolator at each moment according to an input sampling rate and an output sampling rate of the up-sampling system;
S2: according to the data sampling enable at each moment, carrying out cache rectification on each path of parallel input data in N paths in the up-sampling system to obtain K paths of parallel effective data with the sampling depth of K;
S3: for each moment, according to the data sampling enabling, shifting the K paths of parallel effective data to N interpolation registers respectively to obtain N groups of interpolation base points at the moment;
s4: and carrying out parallel interpolation on the N groups of interpolation base points based on the interpolation factors by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results.
Optionally, before step S1, the multi-path parallel upsampling method further includes:
Processing the mapping symbol through at least 2 times of raised cosine roll-off filter SRRC to obtain a bandwidth signal;
And taking the bandwidth signal as input data of the up-sampling system.
Optionally, step S1 includes:
S11: initializing an iteration parameter R μ(n)|n＝0 =0 of the parallel numerical control oscillator at the nt s moment, and calculating a sampling proportion I=f in/fout of input and output of the up-sampling system;
s12: calculating the accumulated result of the iteration parameters of each path of the up-sampling system And simultaneously calculate/>
Wherein m is more than or equal to 1 and less than or equal to N;
s13: calculating intermediate variables
Wherein,Representing a downward rounding;
S14: calculating interpolation factors
S15: calculating the data sampling enable valid m (n), judgingAnd/>Whether the data are equal or not, if the data are equal, valid m (n) =1, otherwise valid m (n) =0, and obtaining data sampling enabling at the moment of nt s and an interpolation factor mu m (n);
S16: order the Juxtaposing n=n+1, returning to step S12 to calculate the data sampling enable and interpolation factor at the next moment;
Wherein N represents a sampling time, m represents an mth path of N paths, N represents the number of parallel paths of the up-sampling system, t s represents an output sampling interval, and t s＝N/fout.
Optionally, a modulator is connected before the up-sampling system, the rectifier includes a RAM controller and a shift register, and the S2 includes:
S21: caching each path of parallel input data in N paths by using a RAM controller;
S22: the shift register determines reading enabling and an output position of the shift register according to the data sampling enabling;
S23: reading and inputting parallel input data with the duty ratio equal to f in/fout into the up-sampling system according to the reading enabling requirement;
s24: the shift register carries out shift caching on each path of parallel input data read by the RAM controller;
The length of the shift register is 3N to 4N;
s25: and the shift register outputs K paths of parallel effective data according to the output position.
Optionally, the method is characterized in that,
The S22 includes:
S221: initializing a data pointer position of a shift register to Addr (n) | n＝0 =0 and flag=0;
S222: the shift register calculates the total number of data sample enable 1 in N paths at nt s time
S223: update data pointer position Addr (n+1) =addr (n) +s valid (n) +flag;
S224: judging whether addr (n+1) is larger than N, if so, setting a reading enabling value to be 1, and reading data from the RAM controller; if less than N, flag=0, the read enable is set to 0 to update flag.
Optionally, step S24 includes:
if the RAM controller reads parallel input data according to the reading enabling, the shift register shifts rightwards, and the read parallel input data are put into a memory of the shift register one by one from left to realize shift caching;
the step S25 includes:
Sequentially reading N paths of data from the current pointer position Addr (N) to the address increasing direction to be output;
The first K paths in the N paths of data are parallel effective data, and K=S valid (N); the flag indicates the number of pointer position jumps.
Optionally, after the step S25, the method further includes:
S26: the RAM controller receives the data block continuously sent by the modulator, and feeds back the flag bit to the modulator according to the address difference between the self write address and the read address, so that the modulator outputs the data block to the RAM controller after adjusting the duty ratio of the self output data block.
Optionally, the step S3 includes:
S31: initializing a stored value R interp(n)|n＝0 = [0,0,0,0,0,0,0,0] of an interpolation register;
s32: calculate the number of 1s in the L data sample enable before nt s time 1≤L≤N；
S33: for each group at each time instant, performing right shift of the interpolation register R interp (N) by P L bits to obtain N groups of interpolation base points X L (N) at the time instant;
Wherein L represents any one of N groups;
S34: let the stored value R interp(n+1)＝XN (N), concatenate n=n+1, return to S32, and get N sets of interpolation base points at each moment.
Optionally, the S33 includes:
S331: when P L is less than or equal to 8, the lowest P L bit data is taken out of the K paths of parallel effective data and is put into an interpolation register from the left;
Wherein the high order is to the left;
S332: when P L >8, the 8 bits of data at the fetch position P L,PL-1,PL-2,…,PL -7 are placed in the interpolation register in sequence, with the upper bit P L to the left;
S333: and repeatedly executing S331 to S332N times with L being more than or equal to 1 and N being less than or equal to each other, and obtaining N groups of interpolation base points X L (N) at each moment.
Optionally, the S4 includes:
S41: calculating intermediate variables of a segmented parabolic interpolator
Wherein, C xy represents the interpolation coefficient of the segmented parabolic interpolator, X L represents the interpolation base point of the L group; mu L represents the interpolation factor of group L;
s42: calculating the output result of the L-th path of the up-sampling system by a segmented parabolic interpolator yL＝Mult1L+μL*(Mult2L+μL*(Mult3L+μL*Mult4L)).
The beneficial effects of the invention include:
(1) The multipath parallel up-sampling method in high-speed digital communication provided by the invention can realize the change of the interpolation parallel path number N by only changing the bit width of a register and the parallel quantity of an interpolator, has high flexibility and expandability, and can reach 64;
(2) The invention provides a multipath parallel up-sampling method in high-speed digital communication, which supports that the highest symbol rate can reach 3Gbaud under 64 paths of parallel conditions;
(3) The multi-channel parallel up-sampling method in high-speed digital communication uses a full parallel structure, calculates control parameters in real time with linear complexity, and meets the control requirement under high parallel channel number;
(4) The multipath parallel up-sampling method in high-speed digital communication provided by the invention realizes interpolation by adopting the interpolation mode of the segmented parabolic interpolator, and has higher interpolation precision compared with the prior art.
Drawings
FIG. 1 is a flow chart of a multi-path parallel upsampling method in high speed digital communication according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a sampling process implemented by an upsampling system according to an embodiment of the present invention;
FIG. 3 is a block diagram of an implementation of an interpolation shift register in a multi-path parallel upsampling method in high speed digital communication according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a 32-order segmented parabolic interpolator implementing interpolation according to an embodiment of the present invention;
FIG. 5 is a spectrum variation diagram of a multi-channel parallel upsampling method in high speed digital communication under 64APSK modulation according to an embodiment of the present invention;
Fig. 6 is a graph showing MSE performance contrast between multiple interpolators under QPSK modulation in a multi-path parallel upsampling method in high-speed digital communication according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In view of the problems existing in the prior art, the present invention provides a multi-path parallel upsampling method in high-speed digital communication, and the present invention is described in detail below with reference to the accompanying drawings.
The variable N appearing in the invention is the parallel path number, the upper bound can reach 64, m and L both represent one path of N paths and are mutually independent, K represents superposition of sampling enabling, the relation that K is more than or equal to 1 and less than or equal to N is satisfied, N represents the sampling time number, N is more than or equal to 0, t s is output sampling interval, and t s＝N/fout.
As shown in fig. 1, the multi-path parallel up-sampling method in high-speed digital communication provided by the invention is applied to an up-sampling system, the up-sampling system comprises a parallel numerically controlled oscillator, a rectifier, an interpolation register and a segmented parabolic interpolator, and the multi-path parallel up-sampling method comprises the following steps:
S1: determining an interpolation factor mu m (m is more than or equal to 1 is less than or equal to N) for enabling data sampling of a rectifier and an interpolation register at each moment and for interpolation of a segmented parabolic interpolator at each moment according to an input sampling rate and an output sampling rate of an up-sampling system;
A parallel Numerically Controlled Oscillator (NCO) implements the interpolation factor and data sample enable calculations in this step. The interpolation register comprises a controller and a memory, wherein the controller controls the memory to carry out shift storage, and the memory is used for storing data in the interpolation process.
S2: according to the data sampling enable at each moment, carrying out cache rectification on each path of parallel input data in N paths in an up-sampling system to obtain K paths of parallel effective data with the sampling depth of K;
In the concrete implementation, the rectification of the real-time variable data with the effective length and the effective position is realized by adopting the two-stage rectification of the RAM controller and the shift register, and signals are fed back to the front-stage modulator module so as to keep the consistency of data throughput.
S3: for each moment, according to data sampling enabling, shifting K paths of parallel effective data into N interpolation registers respectively to obtain N groups of interpolation base points at the moment;
s4: and (3) performing parallel interpolation on the N groups of interpolation base points based on interpolation factors by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results.
The invention provides a multipath parallel up-sampling method for high-speed digital communication, which comprises the following steps: s1: determining data sampling enabling at each moment and interpolation factors at each moment according to the input sampling rate and the output sampling rate of the up-sampling system; s2: according to the data sampling enabling, carrying out cache rectification on each path of parallel input data in N paths to obtain K paths of parallel effective data; s3: shifting K paths of parallel effective data into N interpolation registers respectively according to data sampling enabling to obtain N groups of interpolation base points at the moment; s4: and (3) carrying out parallel interpolation on the N groups of interpolation base points by adopting a segmented parabolic interpolator with a parallel structure to obtain N paths of output results. The multipath parallel up-sampling device provided by the invention can stably work within 250MHz of the FPGA system clock, when the number N of parallel paths is increased, the resource occupancy rate of a program only linearly increases, and up-sampling conversion within extremely high sampling rate can be realized.
As an optional embodiment of the present invention, before step S1, the multi-path parallel upsampling method further includes:
Step one: processing the mapping symbol through at least 2 times of raised cosine roll-off filter SRRC to obtain a bandwidth signal;
step two: the bandwidth signal is used as input data for the up-sampling system.
Referring to fig. 2, as an alternative embodiment of the present invention, the implementation procedure of step S1 includes:
S11: initializing an iteration parameter R μ(n)|n＝0 =0 of the parallel numerical control oscillator at the nt s moment, and calculating a sampling proportion I=f in/fout of input and output of an up-sampling system;
it should be noted that, after the first explanation of the nts time, n is used for brevity to identify the nts time in subsequent brackets for convenience of description.
S12: calculating accumulated results of each path of iteration parameters of up-sampling system And simultaneously calculate/>
Wherein m is more than or equal to 1 and less than or equal to N;
s13: calculating intermediate variables
Wherein,Representing a downward rounding;
S14: calculating interpolation factors
S15: calculating the data sampling enable valid m (n), judgingAnd/>Whether the data are equal or not, if the data are equal, valid m (n) =1, otherwise valid m (n) =0, and obtaining data sampling enabling at the moment of nt s and an interpolation factor mu m (n);
S16: order the Juxtaposing n=n+1, returning to step S12 to calculate the data sampling enable and interpolation factor at the next moment;
where N represents the sampling time, m represents the mth path of N paths, N represents the number of parallel paths of the up-sampling system, t s represents the output sampling interval, and t s＝N/fout.
Noteworthy are: the data sampling enabling valid m and the interpolation factor mu m (m is more than or equal to 1 is less than or equal to N) need to be completely calculated in one moment, but the calculation of mu N needs multiple iterations and cannot be directly realized in the FPGA, so that the parallel result is needed to be adopted, and the accumulated value is calculated in parallel at each sampling momentAccording to adjacent two/>Whether or not to sample is determined by the carry or not of (c) and will/>Is used as the basic interpolation factor/>, of each pathFinally obtain interpolation factor/> Wherein R μ is an interpolation factor register, stores the interpolation factor of the last path at each sampling time, i=f in/fout,fin is the input signal sampling rate, and f out is the output signal sampling rate.
In one embodiment of the present invention, a modulator is connected before the up-sampling system, the rectifier includes a RAM controller and a shift register, and S2 includes:
S21: caching each path of parallel input data in N paths by using a RAM controller;
S22: the shift register determines the output position of the shift register according to the data sampling enabling;
noteworthy are: the shift register comprises a controller and a memory, wherein the shift register controller is used for controlling shift and controlling the memory to store, and the memory is used for shifting generated data.
S23: reading parallel input data with the duty ratio equal to f in/fout in an input up-sampling system according to the reading enabling requirement;
S24: the shift register carries out shift caching on each path of parallel input data read by the RAM controller;
The length of the shift register is 3N to 4N;
In the step, if the RAM controller reads parallel input data according to the reading enabling, the shift register shifts rightwards, and the read parallel input data are put into a memory of the shift register one by one from left to realize shift caching;
s25: and the shift register outputs K paths of parallel effective data according to the output position.
The width of the RAM controller is the total bit width of N paths of parallel signals, and the depth is required to be larger than the length of each block of continuous data.
In this step, N paths of data may be sequentially read as output from the current pointer position Addr (N) toward the address increasing direction.
The first K paths in the N paths of data are parallel effective data, and K=S valid (N); the flag indicates the number of pointer position jumps.
Noteworthy are: when the upsampling multiple f out/fin is an arbitrary multiple, after fixing the continuous data length, the data duty cycle and f in/fout may be lost due to the fix-up in an alternative embodiment of the present invention, S22 includes:
S221: initializing a data pointer position of a shift register to Addr (n) | n＝0 =0 and flag=0;
S222: the shift register calculates the total number of data sample enable 1 in N paths at nt s time
S223: update data pointer position Addr (n+1) =addr (n) +s valid (n) +flag;
S224: judging whether addr (n+1) is larger than N, if so, setting a reading enabling value to be 1, and reading data from the RAM controller; if less than N, flag=0, the read enable is set to 0 to update flag.
As an optional embodiment of the present invention, after S25, the multi-path parallel upsampling method of the present invention further includes:
S26: the RAM controller receives the data block continuously sent by the modulator, and feeds back the flag bit to the modulator according to the address difference between the self write address and the read address, so that the modulator outputs the data block to the RAM controller after adjusting the duty ratio of the self output data block.
Noteworthy are: when the up-sampling multiple f out/fin is an arbitrary multiple, after the continuous data length is fixed, the data duty ratio and f in/fout may not be guaranteed to be completely consistent due to fixed point loss, at this time, the controller should round down the hollow clock number in the duty ratio, so that a slight accumulation phenomenon occurs in the data, when the data accumulation amount is greater than a certain threshold value, the RAM controller feeds back a flag bit to the modulator according to the address difference between the RAM writing address and the reading address, and increases the spare clock number of the current data block, so as to maintain the stability of the data amount in the RAM and the consistency of throughput.
Referring to fig. 3, in an alternative embodiment of the present invention, the implementation procedure of step S3 includes:
S31: initializing a stored value R interp(n)|n＝0 = [0,0,0,0,0,0,0,0] of an interpolation register;
s32: calculate the number of 1s in the L data sample enable before nt s time 1≤L≤N；
S33: for each group at each time instant, performing right shift of the interpolation register R interp (N) by P L bits to obtain N groups of interpolation base points X L (N) at the time instant;
in an alternative embodiment of the present invention, S33 includes:
S331: when P L is less than or equal to 8, the lowest P L bit data is taken out of the K paths of parallel effective data and is put into an interpolation register from the left;
Wherein the high order is to the left;
S332: when P L >8, the 8 bits of data at the fetch position P L,PL-1,PL-2,…,PL -7 are placed in the interpolation register in sequence, with the upper bit P L to the left;
S333: and repeatedly executing S331 to S332N times with L being more than or equal to 1 and N being less than or equal to each other, and obtaining N groups of interpolation base points X L (N) at each moment.
Wherein L represents any one of N groups;
S34: let the stored value R interp(n+1)＝XM (N), concatenate n=n+1, return to S32, and get N sets of interpolation base points at each moment.
Shift K-way effective data (0<K is less than or equal to N) into N interpolation registers for sharing In different situations, when N increases, the judgment situation will increase exponentially and cannot meet the application requirement of the highway parallelism, so that a segmentation method is adopted to independently calculate interpolation positions of K effective data, and count the number/> of 1 in the first L valid m given by step S1 at each sampling momentAnd according to/>And (3) shifting the data in the interpolation register to obtain interpolation base points X L, and executing N times in parallel with the value of L being more than or equal to 1 and less than or equal to N to obtain N groups of interpolation base points.
Referring to fig. 4, in an alternative embodiment of the present invention, S4 includes:
S41: calculating intermediate variables of a segmented parabolic interpolator
Wherein, C xy represents the interpolation coefficient of the segmented parabolic interpolator, X L represents the interpolation base point of the L group; mu L represents the interpolation factor of group L;
S42: calculating the output result of the L-th path of the up-sampling system by the segmented parabolic interpolator yL＝Mult1L+μL*(Mult2L+μL*(Mult3L+μL*Mult4L)).
The fixed-point interpolation coefficient of the 32-order segmented parabolic interpolator is shown in table 1:
Table 1 fixed-point interpolation coefficients for 32-order segmented parabolic interpolators
| Cxy(0X) | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 1 | FF36 | 0314 | F647 | 276E | 276E | F647 | 0314 | FF36 |
| 2 | FFC9 | 00F7 | FC10 | 285F | D7A0 | 03EF | FF08 | 0036 |
| 3 | 00C9 | FCEB | 09B8 | F891 | F891 | 09B8 | FCEB | 00C9 |
| 4 | 0036 | FF08 | 03EF | F7A0 | 085F | FC10 | 00F7 | FFC9 |
The fixed bit width is 2.14, which represents a 1-bit symbol, a 1-bit integer, and 14 is a decimal.
The set of coefficients has symmetry, including:
(1)C1j＝-C3j,C2j＝-C4j，j∈{1,2,3,6,7,8}；
(2)Cij＝Ci(8-j)，i∈{1,3}，j∈{1,2,3,4}；
(3)Cij＝-Ci(8-j)，i∈{2,4}，j∈{1,2,3,4}；
the implementation block diagram of each path of step S4 is shown in fig. 4, and the implementation process is simplified by using the symmetry of the coefficients of table 1, and the implementation block diagram comprises the following steps:
Butterfly addition and subtraction of X L, i.e
[AddL]T 8*1＝[XL]T 8*1+fliplr([XL]T 8*1);
[MinusL]T 8*1＝[XL]T 8*1-fliplr([XL]T 8*1);
Respectively taking the first 4 bits of the vector reverse operation and splicing the first 4 bits of the vector reverse operation as output in the step, wherein fliplr (DEG) represents vector reverse operation;
Calculating Mult4 L＝[C41 C42 C43 C44]*[MinusL]T 4*1;
Mult3L＝[C31 C32 C33 C34]*[AddL]T 4*1；
Mult2L＝[C41 C42 C43 C24]*[MinusL]T 4*1；
Mult1L＝[C31 C32 C33 C14]*[AddL]T 4*1；
Each path of step S4 requires 13 multipliers and 23 adders in total.
The technical effects of the present invention will be further described with reference to simulation experiments.
Simulation conditions:
The software simulation experiment is carried out under MATLAB 2020b software, the hardware simulation experiment is carried out under Vivado2018.3 software, an FPGA chip is selected as VC709, a QPSK/64APSK modem system is taken as an example, the roll-off factor alpha=0.35 of SRRC filtering is adopted, the up-sampling multiple is 4, the simulation channel is an additive Gaussian white noise channel, a 32-order PPI interpolation filter is adopted by an interpolator, and a cubic interpolation and a typical parabolic interpolation are adopted by a contrast interpolator.
Simulation content and result analysis:
And adopting a 64APSK modulation mode, and taking 1.8508 up-sampling multiples. Fig. 5 is a spectrum change situation of a multi-path parallel upsampling method under a noise-free situation, where a sub-graph a in fig. 5 is a signal spectrum before upsampling, and a sub-graph b is a signal spectrum after upsampling. In fig. 5, the abscissa represents the digital frequency and the ordinate represents the power spectral density. It can be seen that the symbol rate is not changed while the sampling rate is 1.8508 times, and the side lobe attenuation of the output power spectrum is more than 40dB, thereby meeting the transmission requirement of digital signals.
By adopting a QPSK modulation mode, the up-sampling multiple is 1.11-10 times, fig. 6 is a mean square error comparison graph of an interpolation point and an ideal interpolation point obtained by the multipath parallel up-sampling method provided by the embodiment of the invention, wherein the abscissa in the graph represents an iteration value I=f in/fout of an interpolation factor, the ordinate represents MSE of the interpolation point and the ideal point, and the interpolation precision of the 32-order segmented parabolic interpolator is obviously greater than that of typical parabolic interpolation and cubic interpolation commonly used in current literature.
Through Vivado2018.3 comprehensive realization, when N is taken to be 16, the resources occupied by the N-path parallel up-sampling device provided by the invention are shown in the table 2, and the realization can be completed under the constraint of a 250MHz clock, so that up-sampling of any multiple under the sampling rate of 4Gsps can be satisfied. From the resource analysis, the invention can realize the parallel and above of 64 paths without changing the framework.
The modulator and the multipath parallel up-sampling device provided by the invention are realized in a VC709 board card, and when the up-sampling multiple is 1-4 times, the EVM performance can be satisfied with less than 3% through the actual measurement of an R & S FSW85 spectrometer.
Table 2 resource occupancy table
| Resource type | The occupied amount | Total amount of VC709 resources | Occupancy ratio |
| LUT | 35632 | 433200 | 8.23％ |
| FF | 24411 | 866400 | 2.82％ |
| Slice | 10962 | 108000 | 10.15％ |
| BRAM | 7.5 | 1470 | 0.51％ |
| DSP | 416 | 3600 | 11.56％ |
The foregoing is merely illustrative of specific embodiments of the present invention, and the scope of the invention is not limited thereto, but any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention will be apparent to those skilled in the art within the scope of the present invention.
Claims (9)
1. The multi-channel parallel up-sampling method in high-speed digital communication is characterized by being applied to an up-sampling system, wherein the up-sampling system comprises a parallel numerical control oscillator, a rectifier, an interpolation register and a segmented parabolic interpolator, and the multi-channel parallel up-sampling method comprises the following steps:
S1: determining data sampling enabling of the enabling rectifier and the interpolation register at each moment and an interpolation factor for interpolation of the segmented parabolic interpolator at each moment according to an input sampling rate and an output sampling rate of the up-sampling system;
S2: according to the data sampling enable at each moment, carrying out cache rectification on each path of parallel input data in N paths in the up-sampling system to obtain K paths of parallel effective data with the sampling depth of K;
S3: for each moment, according to the data sampling enabling, shifting the K paths of parallel effective data to N interpolation registers respectively to obtain N groups of interpolation base points at the moment;
S4: a segmented parabolic interpolator with a parallel structure is adopted, and the N groups of interpolation base points are subjected to parallel interpolation based on the interpolation factors to obtain N paths of output results;
the step S1 comprises the following steps:
S11: initializing an iteration parameter R μ(n)|n＝0 =0 of the parallel numerical control oscillator at the nt s moment, and calculating a sampling proportion I=f in/fout of input and output of the up-sampling system;
s12: calculating the accumulated result of the iteration parameters of each path of the up-sampling system And simultaneously calculate/>
Wherein m is more than or equal to 1 and less than or equal to N;
s13: calculating intermediate variables
Wherein,Representing a downward rounding;
S14: calculating interpolation factors
S15: calculating the data sampling enable valid m (n), judgingAnd/>Whether the data are equal or not, if the data are equal, valid m (n) =1, otherwise valid m (n) =0, and obtaining data sampling enabling at the moment of nt s and an interpolation factor mu m (n);
S16: order the Juxtaposing n=n+1, returning to step S12 to calculate the data sampling enable and interpolation factor at the next moment;
Wherein N represents a sampling time, m represents an mth path of N paths, N represents the number of parallel paths of the up-sampling system, t s represents an output sampling interval, and t s＝N/fout.
2. The multi-path parallel upsampling method according to claim 1, characterized in that before step S1, the multi-path parallel upsampling method further comprises:
Processing the mapping symbol through at least 2 times of raised cosine roll-off filter SRRC to obtain a bandwidth signal;
And taking the bandwidth signal as input data of the up-sampling system.
3. The multi-path parallel upsampling method according to claim 1, wherein a modulator is connected before the upsampling system, the rectifier comprises a RAM controller and a shift register, and the S2 comprises:
S21: caching each path of parallel input data in N paths by using a RAM controller;
S22: the shift register determines reading enabling and an output position of the shift register according to the data sampling enabling;
S23: reading and inputting parallel input data with the duty ratio equal to f in/fout into the up-sampling system according to the reading enabling requirement;
s24: the shift register carries out shift caching on each path of parallel input data read by the RAM controller;
The length of the shift register is 3N to 4N;
s25: and the shift register outputs K paths of parallel effective data according to the output position.
4. The method of multiple parallel upsampling according to claim 3, wherein,
The S22 includes:
s221: initializing a data pointer position of a shift register to Addr (n) | n＝0 =0 and flag=0;
S222: the shift register calculates the total number of data sample enable 1 in N paths at nt s time
S223: update data pointer position Addr (n+1) =addr (n) +s valid (n) +flag;
S224: judging whether addr (n+1) is larger than N, if so, setting a reading enabling value to be 1, and reading data from the RAM controller; if less than N, flag=0, the read enable is set to 0 to update flag.
5. The multi-path parallel upsampling method according to claim 4, wherein step S24 comprises:
if the RAM controller reads parallel input data according to the reading enabling, the shift register shifts rightwards, and the read parallel input data are put into a memory of the shift register one by one from left to realize shift caching;
the step S25 includes:
Sequentially reading N paths of data from the current pointer position Addr (N) to the address increasing direction to be output;
The first K paths in the N paths of data are parallel effective data, and K=S valid (N); the flag indicates the number of pointer position jumps.
6. The multi-path parallel upsampling method according to claim 1, wherein after said S25, said method further comprises:
S26: the RAM controller receives the data block continuously sent by the modulator, and feeds back the flag bit to the modulator according to the address difference between the self write address and the read address, so that the modulator outputs the data block to the RAM controller after adjusting the duty ratio of the self output data block.
7. The multi-path parallel upsampling method according to claim 1, wherein said S3 comprises:
S31: initializing a stored value R interp(n)|n＝0 = [0,0,0,0,0,0,0,0] of an interpolation register;
s32: calculate the number of 1s in the L data sample enable before nt s time
S33: for each group at each time instant, performing right shift of the interpolation register R interp (N) by P L bits to obtain N groups of interpolation base points X L (N) at the time instant;
Wherein L represents any one of N groups;
S34: let the stored value R interp(n+1)＝XN (N), concatenate n=n+1, return to S32, and get N sets of interpolation base points at each moment.
8. The multi-path parallel upsampling method according to claim 7, wherein said S33 comprises:
S331: when P L is less than or equal to 8, the lowest P L bit data is taken out of the K paths of parallel effective data and is put into an interpolation register from the left;
Wherein the high order is to the left;
S332: when P L is more than 8, the 8-bit data of the fetch position P L,PL-1,PL-2,…,PL -7 is put into the interpolation register in sequence, wherein the high-order P L is at the left;
S333: and repeatedly executing S331 to S332N times with L being more than or equal to 1 and N being less than or equal to each other, and obtaining N groups of interpolation base points X L (N) at each moment.
9. The multi-path parallel upsampling method according to claim 1, wherein said S4 comprises:
S41: calculating intermediate variables of a segmented parabolic interpolator
Wherein, C xy represents the interpolation coefficient of the segmented parabolic interpolator, X L represents the interpolation base point of the L group; mu L represents the interpolation factor of group L;
s42: calculating the output result of the L-th path of the up-sampling system by a segmented parabolic interpolator yL＝Mult1L+μL*(Mult2L+μL*(Mult3L+μL*Mult4L)).
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