CN115549644A

CN115549644A - FIR filter

Info

Publication number: CN115549644A
Application number: CN202211293761.1A
Authority: CN
Inventors: 邱丹; 杨晓刚
Original assignee: China Key System and Integrated Circuit Co Ltd
Current assignee: China Key System and Integrated Circuit Co Ltd
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2022-12-30

Abstract

The invention discloses a FIR filter, belonging to the field of digital signal processing, comprising a memory module, a FIR operation module, an amplitude scaling module and a control logic module. The memory module is used for storing input data samples; the FIR operation module is the main body of the FIR filter and performs FIR filtering operation on the read data samples; the amplitude scaling module performs amplitude scaling on the FIR filtering operation result to obtain final filter output; the control logic module generates read-write signals to the memory module, operation control signals to the FIR operation module and scaling coefficient selection signals to the amplitude scaling module. The invention greatly reduces the hardware resources occupied by data sample storage, avoids using a hardware multiplier, and greatly reduces the hardware resources required by FIR operation; meanwhile, as a plurality of stages of shifters and accumulators are adopted, more accurate filter coefficients can be realized.

Description

FIR filter

Technical Field

The invention relates to the technical field of digital signal processing, in particular to an FIR filter.

Background

The digital filter has two types, infinite Impulse Response (IIR) and Finite Impulse Response (FIR). Compared with an IIR (infinite impulse response) device, the FIR has the advantages of linear phase, low design difficulty and the like, so that the FIR is widely applied.

The equation for an FIR filter is:

therefore, the basic operation is multiply-accumulate processing, and N times of multiplication and N-1 times of addition are needed for obtaining a filtering value. In the hardware-implemented FIR filter, the multiplier is usually used to implement the filtering operation, which consumes hardware resources, especially when the precision of the filter coefficient is high (i.e. the number of bits is large), a multiplier with a large bit width is needed, and the consumed hardware resources are considerable. Furthermore, if the shift register is used to store data samples, a large amount of hardware resources are also occupied.

Disclosure of Invention

It is an object of the present invention to provide a FIR filter that solves the problems of the background art.

In order to solve the above technical problem, the present invention provides an FIR filter, including:

a memory module to store input data samples;

the FIR computing module is used for performing FIR filtering operation on the read data samples;

the amplitude scaling module is used for carrying out amplitude scaling on the result of the FIR filtering operation to obtain the final filter output;

and the control logic module is used for generating a read-write control signal for the memory module, an operation control signal for the FIR operation module and a scaling coefficient selection signal for the amplitude scaling module.

In one embodiment, the memory module comprises n rows and m columns of bit units, each bit unit has the same structure and comprises a data input port, an A-way data output port, a B-way data output port, a write enable, an A-way read enable and a B-way read enable; the data input ports of all bit positions of the same bit are short-circuited, the A-path data output ports are short-circuited, and the B-path data output ports are short-circuited; the read and write enable signals of the memory module are generated by the control logic module, only one address is selected to be written in at the same time, and only one address is selected to be read out in the path A and the path B at the same time.

In one embodiment, the FIR operation block sequentially performs a plurality of shift and accumulation operations on the sum of the a-path data and the B-path data read from the memory block for the duration of time during which each read enable signal is asserted; the A path data and the B path data samples read out from the memory module each time correspond to two data samples of symmetric coefficients in the FIR filter;

the FIR operation module comprises:

an adder for adding the A-path data and the B-path data read from the memory module, wherein the read address is generated by the control logic module;

the plurality of stages of shifters are used for performing shift operation on the output result of the adder;

and the accumulator accumulates or subtracts the intermediate result of the shift operation.

In one embodiment, each of the plurality of stages of shifters has n selectable shift bits, and the shift bits of each stage of shifter are selected by a control signal generated by the control logic module; the total number of shift bits is the sum of the number of shift bits of all the shifters.

In one embodiment, the several stages of shifters are a first stage right removal shifter and a second stage right removal shifter, and the first stage right removal shifter has 4 selectable right shift numbers: 1 bit/2 bit/3 bit/4 bit, and the second-stage right removal device has 4 optional right shift bits: 0 bit/4 bit/8 bit/12 bit; the right shift numbers of the first-stage right removal device and the second-stage right removal device are respectively selected through a right shift number selection signal generated by the control logic module; when moving to the right, the high bits are symbol bit expanded.

In one embodiment, when the intermediate result of the shift operation is accumulated, the original data is added to 0 and then fed to the accumulator for addition; when the intermediate result of the shift operation is subtracted, the original data is inverted, added with 1 and then sent to the accumulator for addition.

In one embodiment, the memory module includes two memory regions: a data sample storage area and an operation intermediate result storage area; the data sample storage area is used for storing input data samples; the operation intermediate result storage area is used for storing operation intermediate results fed back from the FIR operation module; the selection of the two paths of input data by the memory module is controlled by the control logic module.

In one embodiment, the number of data samples read by the FIR operation module performing one main operation is the order of the FIR filter.

In one embodiment, a variable design is formed according to the address of the first read data sample of the next operation and the interval of the current time; if the interval is equal to one, then the filter is a common FIR filter; if the interval is greater than one, then the FIR filter is decimated.

In one embodiment, a variable design is formed according to the number of filtering rounds, and one round of filtering operation can be performed or multiple rounds of filtering can be performed to further improve the filtering precision.

In the FIR filter provided by the invention, the memory module is adopted to store the data sample, so that the hardware resource occupied by the data sample storage is greatly reduced; two data samples corresponding to the symmetric coefficients are added, and digit-controlled shift operation is performed on the addition result, so that a hardware multiplier is avoided, and hardware resources required by FIR operation are greatly reduced; meanwhile, as the plurality of stages of shifters and accumulators are adopted, relatively accurate filter coefficients can be realized, and multiple rounds of filtering operation can be adopted to further improve the filtering precision, so that the hardware cost of the FIR filter is greatly reduced on the premise of not influencing the performance of the FIR filter.

Drawings

Fig. 1 is a block diagram of an FIR filter according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a main structure of a memory module according to a first embodiment of the present invention;

FIG. 3 is a block diagram of an FIR calculation module according to a first embodiment of the present invention;

fig. 4 is a block diagram of a FIR filter according to a third embodiment of the present invention;

FIG. 5 is a flowchart of an FIR operation in the third embodiment of the present invention.

Detailed Description

An FIR filter according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a FIR filter, the structural block diagram of which is shown in FIG. 1, specifically comprising a memory module, a FIR operation module, an amplitude scaling module and a control logic module. The memory module is used for storing input data samples; the FIR operation module is the main body of the FIR filter and performs FIR filtering operation on the read data samples; the amplitude scaling module performs amplitude scaling on the FIR filtering operation result to obtain final filter output; the control logic module generates read-write signals to the memory module, operation control signals to the FIR operation module and scaling coefficient selection signals to the amplitude scaling module.

The schematic structural diagram of the memory module is shown in fig. 2, an array structure of n rows and m columns is formed by m × n bit units, the structure of each bit unit is the same, and each bit unit comprises a data input port, two data output ports of an a path and a B path, and write enable, a read enable of the a path and a read enable of the B path. And the data input short circuit, the A-path data output short circuit and the B-path data output short circuit of all bit units of the same bit are also short-circuited. The read-write enable signal of the memory module is generated by the control logic module, only one address is selected to be written in at the same time, and only one address in the path A and the path B is selected to be read out at the same time (read data collision is avoided).

The structural block diagram of the FIR operation module is shown in fig. 3, and includes an adder, a first-stage right removal adder, a second-stage right removal adder, and an accumulator. The A path data and the B path data are read out from the memory module, the read-out address is generated by the control logic module, and the two paths of data are added for subsequent operation. The principle is as follows: and adding two data samples corresponding to the symmetric coefficients in the memory module by utilizing the symmetric characteristic of the coefficients of the FIR filter, and multiplying the two data samples by the common coefficient.

The FIR operation module adopts two stages of right shift shifters (i.e. a first stage right removal shifter and a second stage right removal shifter). The first-stage right removal method has 4 optional right shift numbers: 1 bit/2 bit/3 bit/4 bit (i.e., divide by 2/4/8/16), the second level right removal method has 4 optional right shift numbers: 0 bits/4 bits/8 bits/12 bits (i.e., divided by 1/16/256/4096), and the right shift numbers of the first stage right removal operator and the second stage right removal operator are selected by a right shift number selection signal, respectively. When moving to the right, the high bits are symbol bit expanded. It should be noted that, only the exemplary technical solution adopted in the present embodiment is described here, in practical application, more than two stages of left shift or right shift shifters may be adopted according to needs, and the selectable shift bits of each stage of shifter may also be designed according to needs, which is not limited in the present embodiment.

Two stages of right removal adders cascade together with the overall divisor being the multiplication of the two. For example, if the first level right removal is selected to divide by 4 and the second level right removal is selected to divide by 8, the overall divisor is 32. The right shift number selection signal is generated by the control logic module and is dynamically changed in the working process, namely, the overall divisor is dynamically changed.

The data after two-stage division is fed into accumulator for accumulation, where there is addition/subtraction control. When the addition operation is selected, the original data is added with 0 and then is sent to an accumulator for addition; when the subtraction operation is selected, the original data is inverted and added to 1, and then fed into the accumulator for addition (i.e. actual subtraction). The output of the accumulator is provided to the amplitude scaling module as a result of the FIR operation module.

Taking a 30 th order FIR filter as an example, the overall work flow is as follows: the control logic module generates a write enable signal of the memory module, and continuously writes the input data samples of the FIR filter into corresponding addresses of the memory module, wherein the time sequence of the data samples and the written addresses are in a monotonic relation; in parallel, the control logic generates a read enable signal for the memory block, and for one FIR operation, the A-way and B-way read out 15 data samples, for example, the A-way read out address 20-6 data samples and the B-way read out address 21-35 data samples, totaling 30 samples of addresses 6-35. And respectively reading two data samples corresponding to the symmetric coefficients in the memory module by utilizing the symmetric characteristic of the coefficients of the FIR filter, and sending the two data samples to the adder. Two samples of address 20 and address 21 are added, two samples of address 19 and address 22 are added, and so on.

After one FIR operation is completed, the first read sample of the next operation is separated from the current time by 1. For example, the B-way operation reads the first sample corresponding to address 21, and the next operation reads the first sample corresponding to address 22.

In the effective duration of each read enable signal, the sum of the A path data and the B path data is sequentially subjected to a plurality of right removal methods and accumulation operations (controlled by a control logic module), and the divisors of the right removal methods and the accumulated iteration times of the right removal methods performed on different data samples are different, so that different filter coefficients are realized. For example, after adding two samples of address 20 and address 21, the respective right shift number, corresponding divisor, and add-subtract selections are as follows:

number of right shifts	Corresponding divisor	Add-subtract selection
			1	2	Adding
3	8	Adding
			5	32	Adding
6	64	Adding
			8	256	Adding
13	8192	Reducing

TABLE 1 Right Shift Numbers, corresponding divisor, and Add/subtract selection relationship

Therefore, the actual multiplied coefficient after adding the two sample values is: 1/2+1/8+1/32+1/64+1/256-1/8192=0.6756591797 (without considering right-shift truncation error), which is the coefficient of the 15 th and 16 th order of the filter. Based on the principle, the right shift number and addition and subtraction selection corresponding to the filter coefficients of other orders can be designed.

After FIR operations, the results may be too large or too small compared to the original data samples. And the amplitude scaling module is used for carrying out amplitude scaling (reduction or amplification) on the result of the FIR operation module, controlling the amplitude within a reasonable range and obtaining the final filter output. If the shifter is a right shifter (for division), the operation result may be too small, and the amplitude can be amplified; if the shifter used is a left shift shifter (for multiplication), the result may be too large, and amplitude reduction may be performed. The specific amplitude scaling factor is generated by the control logic module.

In the first embodiment, the memory module is used for storing the data samples, so that hardware resources occupied by the storage of the data samples are greatly reduced; two data samples corresponding to the symmetric coefficients are added, and digit-controlled shift operation is performed on the addition result, so that a hardware multiplier is avoided, and hardware resources required by FIR operation are greatly reduced; meanwhile, as a plurality of stages of shifters and accumulation/subtraction devices are adopted, relatively accurate filter coefficients can be realized, and the effect of greatly reducing the hardware cost of the FIR filter is achieved on the premise of basically not influencing the performance of the FIR filter.

Example two

The second embodiment realizes a decimation FIR filter, and the structural block diagram, the memory module structural diagram and the FIR operation module structural block diagram are the same as those of the first embodiment. The difference from the first embodiment is that: through different designs of the control logic module, after one FIR operation is completed, the distance between the address of the first read sample of the next operation and the address of the first read sample of the current operation is more than 1. For example, if the first read sample address of the next operation is 4 times away from the current time, 4 times of extraction of the FIR filter is realized; the first read sample address of the next operation is 5 times away from the current time, so that the FIR filter is extracted by 5 times.

EXAMPLE III

Fig. 4 is a block diagram of an FIR filter according to a third embodiment of the present invention, which includes the same main blocks as in the first embodiment. The difference from the first embodiment is that the present embodiment divides the storage area of the memory module into two blocks:

data sample storage area: the data storage device is used for storing input data samples;

operation intermediate result storage area: and the device is used for storing the operation intermediate result fed back from the FIR operation module.

Correspondingly, the input data of the memory module has two paths, which are respectively the intermediate result fed back by the data sample input and the FIR operation module, and the selection of the two paths of input data is controlled by the control logic module.

Taking a 27-order FIR filter as an example, assume that the total available address range of the memory module is 0-35, wherein addresses 0-10 are divided into operation intermediate result storage areas, and addresses 26-34 are divided into data sample storage areas. For one FIR operation, the working flow is shown in FIG. 5 and includes two rounds of operations. The first round is divided into 11 steps, in each step, the A path and the B path respectively read out 4 data samples (from addresses 26-34), carry out right shift division and accumulation operation after addition, and write the operation result (intermediate result) into the corresponding address in the addresses 0-10 of the memory module (at this moment, the input data of the memory module selects the intermediate result fed back by the FIR operation module); and a second round: the path A and the path B respectively read out 6 intermediate results (from addresses 0-10), and after addition, right shift division and accumulation operation are carried out to obtain the final result of one FIR operation. The principle of each 1-step operation in the first round and the second round is equivalent to one FIR operation in the first embodiment of the present invention.

For example, in step 1 of the first round, the a-way reads the data samples of addresses 32, 31, 30, 29, respectively, the B-way reads the data samples of addresses 32, 33, 34, 26, respectively (i.e., 7 data samples of addresses 29 to 34 and 26 are read, wherein the sample of address 32 is read in both the a-way and the B-way), and the operation result is written in address 4; in step 2 of the first round, the a-way reads data samples of addresses 34, 33, 32, 31, respectively, the B-way reads data samples of addresses 34, 26, 27, 28, respectively, the operation result is written to address 5, and so on. In the 11 th step of the first round, the a-way reads data samples at addresses 34, 33, 32, and 31, respectively, and the B-way reads data samples at addresses 34, 26, 27, and 28, respectively, and writes the operation result to address 3. In the second round, way a reads intermediate results for addresses 9, 8, 7, 6, 5, 4, respectively, and way B reads intermediate results for addresses 9, 10, 0, 1, 2, 3, respectively. In one FIR operation, the total read addresses 29 to 34, 26 to 34, and 26 to 28 total 27 data samples, i.e. the filter order is 27.

In the 1 st step of the first round of the next FIR operation, the interval between the first sample address read out from the a path and the B path and the first sample address in the 1 st step of the first round of the current FIR operation may be 1, or may be greater than 1, so as to implement a common FIR filter or an extraction FIR filter.

In this embodiment, the intermediate coefficients of each step of the first round are shown in table 2:

TAP number	Intermediate coefficient
		1,7	0.05493164062
2,6	0.3127441406
		3,5	0.7578125
4	1

Table 2 intermediate coefficients for each step operation of the first round table the coefficients for the second round of operation are shown in the following table:

TAP number	Coefficient of performance
		1,11	-0.02233886719
2,10	-0.09741210938
		3,9	-0.125
4,8	0.125
		5,7	0.6202392578
6	0.8906860352

Table 3 coefficient table of the second round of operation the resulting overall filter coefficients are shown in the following table:

TAP number	Final coefficient of performance
		1,27	-0.001227110624
2,26	-0.006986349821
		3,25	-0.02227967978
4,24	-0.05280393362
		5,23	-0.097615242
6,22	-0.1434914768
		7,21	-0.1629073322
8,20	-0.1163720489
		9,19	0.02871975303
10,18	0.2798831761
		11,17	0.6068120152
12,16	0.937889114
		13,15	1.185935289
14	1.278638422

Table 4 table of all filter coefficients finally obtained

The filter orders, address correspondence, calculation steps and coefficients listed here are only for illustrating the principle of the present embodiment, and in practical applications, various designs can be generated as needed under the condition that the principle is not changed, and the present embodiment does not limit this. The calculation turns listed here are two turns (accordingly, the storage area of the memory module is divided into two blocks), and in practical applications, more calculation turns can be adopted as needed to achieve higher coefficient accuracy (accordingly, the storage area of the memory module is divided into more blocks), which is not limited in this embodiment.

On the basis of the technical scheme of the embodiment, the design of multiple rounds of filtering operation is added, and the filtering precision is further improved, so that the effect of greatly expanding the application range of the hardware is achieved on the premise that the hardware cost is kept low.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A FIR filter, characterized in that it comprises:

a memory module to store input data samples;

2. The FIR filter of claim 1, wherein said memory block comprises n rows and m columns of bit cells, each bit cell having the same structure and comprising a data input port, an a-way data output port and a B-way data output port, a write enable, an a-way read enable and a B-way read enable; the data input ports of all bit positions of the same bit are short-circuited, the A-path data output ports are short-circuited, and the B-path data output ports are short-circuited; the read and write enable signals of the memory module are generated by the control logic module, only one address is selected to be written in at the same time, and only one address is selected to be read out in the path A and the path B at the same time.

3. The FIR filter as set forth in claim 2, wherein said FIR operation block sequentially performs a plurality of shift and accumulation operations on the sum of the a-way data and the B-way data read out from the memory block for a duration in which each read enable signal is asserted; the A path data and the B path data samples read out from the memory module each time correspond to two data samples of symmetric coefficients in the FIR filter;

the FIR operation module comprises:

4. The FIR filter according to claim 3, wherein each of said plurality of stages of shifters has n selectable numbers of shift bits, the number of shift bits of each stage of shifter being selected by a control signal generated by the control logic block; the total number of shift bits is the sum of the number of shift bits of all the shifters.

5. The FIR filter according to claim 4, characterized in that said several stages of shifters are a first stage right removal shifter and a second stage right removal shifter, said first stage right removal shifter having a total of 4 selectable right shift bits: 1 bit/2 bit/3 bit/4 bit, and the second-stage right removal device has 4 optional right shift bits: 0 bit/4 bit/8 bit/12 bit; the right shift numbers of the first-stage right removal device and the second-stage right removal device are respectively selected through a right shift number selection signal generated by the control logic module; when moving to the right, the high bits are symbol bit expanded.

6. A FIR filter as claimed in claim 5, characterized in that, when adding up the intermediate results of the shift operations, the original data are added to 0 and fed to the accumulator for addition; when the intermediate result of the shift operation is subtracted, the original data is inverted, added with 1 and then sent to the accumulator for addition.

7. The FIR filter according to claim 6, characterized in that said memory module comprises two memory areas: a data sample storage area and an operation intermediate result storage area; the data sample storage area is used for storing input data samples; the operation intermediate result storage area is used for storing operation intermediate results fed back from the FIR operation module; the selection of the two paths of input data by the memory module is controlled by the control logic module.

8. The FIR filter according to claim 7, wherein the number of data samples read by the FIR operation module in one main operation is the order of the FIR filter.

9. The FIR filter according to claim 8, wherein a variable design is formed according to an interval between an address of a first read data sample of a next operation and a present time; if the interval is equal to one, the filter is a common FIR filter; if the interval is greater than one, then the FIR filter is decimated.

10. The FIR filter according to claim 9, wherein a variable design is formed according to the number of filtering rounds, and one round of filtering operation can be performed, or multiple rounds of filtering can be performed to further improve the filtering accuracy.