CN1835587A - Method of realizing VLSI of brightness interpolator based on AVS movement compensation - Google Patents
Method of realizing VLSI of brightness interpolator based on AVS movement compensation Download PDFInfo
- Publication number
- CN1835587A CN1835587A CN 200610025670 CN200610025670A CN1835587A CN 1835587 A CN1835587 A CN 1835587A CN 200610025670 CN200610025670 CN 200610025670 CN 200610025670 A CN200610025670 A CN 200610025670A CN 1835587 A CN1835587 A CN 1835587A
- Authority
- CN
- China
- Prior art keywords
- input
- filter
- data
- output
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
- Image Processing (AREA)
Abstract
The invention adopts a stages-variable pipeline architecture that can automatically select stages from 4 stages to 8 stages based on the interpolation requirement in different target location. It comprises the flowing operations: data delay, filtering in row direction, filtering in column direction, filtering at J point, data reduction, 1/4 pixel filtering, output path selecting and amplitude limiting. The method can simultaneously execute operations of data inputting, processing and outputting, and avoid the system occupation on the idle waiting, data transposition and intermediate variables storage.
Description
Technical field
The present invention relates to a kind of method of digital video decoding technical field, specifically is a kind of VLSI (very lagre scale integrated circuit (VLSIC)) implementation method of the brightness interpolator based on AVS (digital audio/video encoding and decoding technique standard) motion compensation.
Background technology
The video section of the AVS audio/video encoding/decoding technical standard that digital audio/video encoding and decoding technique standard operation group (AVS working group) is formulated is the State Standard of the People's Republic of China on February 22nd, 2006 by promulgation, standard No. GB/T 20090.2-2006 was in enforcement on March 1 in 2006.Motion compensation is one of AVS decoding algorithm most important component as the inverse operation of estimation.Estimation and motion compensation are intended to eliminate the time redundancy between video data frame and the frame, thereby reach the purpose of video data compression.Because under actual conditions, the distance of picture motion can have infinite precision, so the motion vector of integer precision can't satisfy the growing requirement to video quality.In AVS, adopted the motion vector of fraction precision to improve picture quality.The AVS standard code, the motion vector of monochrome information has the precision of 1/4 pixel; Correspondingly, the precision of chrominance information motion vector reaches 1/8 pixel.For monochrome information, defined two kind of 4 tap filter and a kind of bi-linear filter among the AVS, the method for use filtering interpolation obtains the data of half-pix and 1/4 location of pixels.Detail can be with reference to the document and the reference software of AVS standard.Fractional pixel interpolation has also increased the complexity of calculating greatly when improving picture quality, this directly translates into the rising of cost and the increase of power consumption when VLSI realizes.For the application of high definition video, it is more outstanding that this problem just seems.For example at decoding per second 30 frames, during the high definition code stream of 1920 * 1080 pixels, in order to guarantee the real-time of video playback, the per second kind need be carried out interpolation operation to the luminance block of 1944000 8 * 8 pixels under the worst case.Huge amount of calculation realizes having brought a difficult problem for the VLSI of brightness interpolator, promptly how under the prerequisite that guarantees the video decode real-time, dwindles area of chip as far as possible and reduces the clock frequency of system.
According to retrieval to the prior art document, people such as discovery Deng Lei are at Pacific Rim Conferenceon Multimedia 2004:Tokyo, among " the An Efficient VLSI Implementation for MC Interpolation of AVSStandard " that is delivered on the Japan (international conference of a multimedia technology field) (the efficient VLSI of interpolation algorithm realizes in the AVS motion compensation), relate to a kind of implementation method of AVS brightness interpolator, this method has certain streamline thought, but its shortcoming is: 1,6 pixel registers of (n+1) * have been used in its input memory cell.Wherein n is the pixel number of parallel computation.Simultaneously, obtain synchronous input data in order to make 1/4 pixel filter, this framework has used 12 grades of delay time registers altogether.Here exist bigger resource redundancy.2, the filter quantity of using in its framework is more.For example, under the situation of n=1, need use 30 all kinds of filters.Therefore there is bigger calculating redundancy.3, the interpolation device that uses this method to realize, will reach 9 clock cycle its time of delay that is input to output at most, exist the regular hour redundancy here.
Summary of the invention
In order to address the above problem, the objective of the invention is to, a kind of VLSI implementation method of the brightness interpolator based on the AVS motion compensation is provided.The present invention adopts the variable pipeline organization of a kind of progression, make input, processing and the output of data to carry out simultaneously, avoid idle waiting, data transposition and deposited the expense of intermediate variable, when improving arithmetic speed, also effectively reduced taking of hardware resource.Use this method to realize brightness interpolator, under the prerequisite of guaranteeing the high definition video real-time decoding, also control chip area and system clock frequency effectively.
The present invention is achieved by the following technical solutions, the present invention has adopted the variable pipeline organization of a kind of progression, at the interpolation needs of different target position, selects 4 to 8 level production lines automatically, carry out input, processing and the output of data simultaneously, comprise the steps:
(a) the input data are done the delay operation;
(b) line direction filtering;
(c) column direction filtering;
(d) J point filtering;
(e) to (a) and (b), (c) and (d) dateout of step put in order;
(f) 1/4th pixel filters;
(g) output channel selection, amplitude limit output.
Below each step is further detailed:
(a) the input data are done the delay operation
If the pixel number of parallel computation is n, wherein between the n desirable 1 and 8, data are by the row input and output, and then the input data of every row need n+4 pixel at most, and each clock cycle input data line is expressed as { A with it
N+3, A
N+2... A
0, wherein being total to the n+4 item, each represents the pixel of one 8 bit, these data is carried out three grades postpone operation, obtains the triplex row dateout, and with respect to the input data, this three line data has the delay of 1,2 and 3 clock cycle respectively, is expressed as { B
N+3, B
N+2... B
0, { C
N+3, C
N+2... C
0And { D
N+3, D
N+2... D
0;
(b) line direction filtering
Use n+1 4 tap filters, tap coefficient is [1,5,5 ,-1], and filter is numbered n and is decremented to 0; Wherein the n filter is input as { C
N+3, C
N+2, C
N+1, C
n, the n-1 filter be input as { C
N+2, C
N+1, C
n, C
N-1, the rest may be inferred, and the output of this group filter is expressed as { b
n, b
N-1... b
0, output is than clock cycle of input delay;
(c) column direction filtering
Use n+4 4 tap filters, tap coefficient is [1,5,5 ,-1], and filter is numbered n+3 and is decremented to 0; Wherein the n+3 filter is input as { A
N+3, B
N+3, C
N+3, D
N+3, the n+2 filter be input as { A
N+2, B
N+2, C
N+2, D
N+2, the rest may be inferred; The output of this group filter is expressed as { h
N+3, h
N+2... h
0, output is than clock cycle of input delay;
(d) J point filtering
Use n+1 4 tap filters, tap coefficient is [1,5,5 ,-1], and filter is numbered n and is decremented to 0; Wherein the n filter is input as { h
N+3, h
N+2, h
N+1, h
n, the n-1 filter be input as { h
N+2, h
N+1, h
n, h
N-1, the rest may be inferred; The output of this group filter is expressed as { j
n, j
N-1... j
0; Output is than clock cycle of input delay;
(e) to (a) and (b), (c) and (d) dateout of step put in order
The purpose of this step is to provide the input data for (f) step; By to (a) and (b), (c) and (d) dateout in these four steps select and postpone operation, at the 1/4 pixel interpolation of diverse location, obtain n group dateout, 4 every group, be used for the input of 1/4th pixel filters;
(f) 1/4th pixel filters
Use n 4 tap filters, tap coefficient is [1,7,7,1], and filter is numbered n-1 and is decremented to 0; Its input data are from (e) output in step; The output of this group filter is expressed as { Q
N-1, Q
N-2... Q
0; Output is than clock cycle of input delay;
(g) output channel selection, amplitude limit output
At first select n data the outputs in five steps from (a) and (b), (c), (d) with (f); When the target location is the integer pixel point, promptly fractional coordinates Y and X are at 0 o'clock, select { A
N+3, A
N+2... A
4; When the target location is the b point, promptly when fractional coordinates Y=0, X=2, select { b
n, b
N-1... b
1; When the target location is the h point, promptly when fractional coordinates X=2, Y=0, select { h
N+3, h
N+2... h
4; When the target location is the j point, promptly when fractional coordinates Y=2, X=2, select { j
n, j
N-1... j
1; When the target location is other, select { Q
N-1, Q
N-2... Q
0; Use n amplitude limiter to handle this n data respectively subsequently, codomain is limited in 0 to 255, each length is 8 bits; Export the data of 8*n bit at last.
In said method, step (a) is worked simultaneously to this 7 step operation of step (g), from being input to output, forms a streamline; Thereby this brightness interpolator can both carry out secondary data input in each clock cycle, and after postponing through the some cycles number, each clock cycle can both be carried out secondary data output.
In said method, the I/O mode of brightness interpolator is not limited to be undertaken by row; Carry out input and output by row if desired, only need fractional coordinates Y and X are exchanged, and do not need the structure of interpolation device is done any change.
Said method is mainly decoded towards high definition video, but is not limited to the decoding high definition video; By changing the parameter n of definition in the step (a), the i.e. number of the pixel of parallel computation, employed hardware resource quantity in the time of just can adjusting specific implementation.
As from the foregoing, the VLSI implementation method of a kind of brightness interpolator based on the AVS motion compensation of the present invention, adopted the variable pipeline organization of a kind of progression, interpolation at the different target position needs, automatically select 5 to 8 level production lines, carry out the operation that comprises input data delay, line direction filtering, column direction filtering, the filtering of J point, data preparation, 1/4 pixel filter, output channel selection and these steps of amplitude limit.This method makes input, processing and the output of data to carry out simultaneously, has avoided idle waiting, data transposition and has deposited the expense of intermediate variable, has also effectively reduced taking of hardware resource when improving arithmetic speed.Use this method to realize brightness interpolator, under the prerequisite of guaranteeing the high definition video real-time decoding, also control chip area and system clock frequency effectively.
Especially, the method that people such as the Deng Lei that is mentioned in the present invention and the preamble propose compares, can obtain following comparing result: (1) from register quantitatively, under the n=1 situation, in people's such as Deng Lei the framework, the pixel register quantity that is used to import storage and data sync is 48 (6 * 6+12), and in the framework of the present invention, under the situation of n=1, the quantity of pixel register only is 18 (5 * 3+3); (2) quantitatively, under the n=1 situation, in people's such as Deng Lei the framework, 30 all kinds of filters have been used altogether from filter; And in framework of the present invention, only need to use 10 filters.And in two in the framework size of single filter be similar; (3) on computational speed, in people's such as Deng Lei the framework, the long delay between output and the input is 9 clock cycle, and in framework of the present invention, and long delay is 8 clock cycle, slightly improves.
In sum, the present invention has advantage in the saving of computational speed and hardware resource.
Description of drawings
Fig. 1 is the overall construction drawing of brightness interpolator;
Fig. 2 is the position distribution of brightness fraction pixel among the AVS;
Wherein contain the position at uppercase square expression integer pixel point place, the circle that contains lowercase is represented the position at half-pix and 1/4th pixel places.
Fig. 3 is the schematic diagram of pipeline work;
Fig. 4 is the form (situations during 2 parallel computations) of the input data of agreement;
Fig. 5 is the structure chart of delay time register pack module;
Fig. 6 is the structure chart of line filter group;
Fig. 7 is the structure chart of column filter group;
Fig. 8 is the structure chart of J point bank of filters;
Fig. 9 be 1/4 bank of filters module and with being connected of data preparation module;
Figure 10 is the cut-away view of data preparation module;
Figure 11 is outlet selector and amplitude limiter.
Specific implementation
Provide following examples in conjunction with technical solution of the present invention and accompanying drawing:
As shown in Figure 1, be convenient narration, in this example, the pixel number of regulation parallel computation is 2, even defined parameter n equals 2 in the step (a).Be not equal to 2 situation for n, only need simply expand (n was greater than 2 o'clock) or simplify (n equals at 1 o'clock) getting final product this routine structure.
As Fig. 1,7 steps of the present invention correspond respectively to 7 hardware modules among the figure.Its corresponding relation is as follows:
The corresponding delay time register group of step (a).
Step (b) corresponding row bank of filters.
Step (c) respective column bank of filters.
The corresponding J point of step (d) bank of filters.
Step (e) corresponding data sorting module.
Corresponding 1/4 bank of filters of step (f).
Corresponding outlet selector of step (g) and amplitude limiter.
Each hardware module is worked simultaneously, forms streamline, at the interpolation needs of different target position, selects 5 to 8 level production lines automatically, carries out the operation (as Fig. 3) of above steps.Below set forth each module respectively.
The delay time register pack module.As Fig. 5.Because n equals 2, the every row of input data should have the brightness data of n+4=6 pixel at most.When carrying out the interpolation of diverse location, the input data bulk that need use also is different.During for example to i position interpolation, need use the data of every capable n+4=6 pixel; And during to d position interpolation, only need use the data of every capable n=2 pixel.Therefore be necessary regulation, during the data input, useful data begins to arrange to low level from a high position, (consults Fig. 4) till having arranged.In AVS, the brightness data of each pixel is represented with 8 bit unsigned numbers.Therefore, for the operation that requires in the completing steps (a), need to use 3 grades of registers, every grade of bit wide should be 6 * 8=48 bit.More generally under the situation, every grade of bit wide should be (n+3) * 8 bit.
The line filter pack module.As Fig. 6.The function of this module is to calculate the half-pixel data (consulting Fig. 2) be in position b, and its result is as required as the input of dateout or 1/4 pixel filter.Because n equals 2, the line filter group should be made of n+1=3 filter.Wherein each filter has tap coefficient (1,5,5 ,-1).4 inputs of each filter are the bit wide of 8 bits.Wherein, filter R_FIR_2's is input as { C
5, C
4, C
3, C
2, R_FIR_1 is input as { C
4, C
3, C
2, C
1, R_FIR_0 is input as { C
3, C
2, C
1, C
0.In order to keep the precision of data after the filtering, filter is output as 13 bit signed numbers, is expressed as { b
2, b
1, b
0.More generally under the situation, the line filter pack module should be made of n+1 filter, and its output is expressed as { b
n, b
N-1... b
0.Owing to adopted output register, data output will be later than clock cycle of input.
The column filter pack module.As Fig. 7.The function of this module is to calculate the half-pixel data (consulting Fig. 2) be in position h, and its result is as required as the input of dateout or 1/4 pixel filter.Because n equals 2, the column filter group should be made of n+4=6 filter.Wherein each filter has tap coefficient (1,5,5 ,-1).4 inputs of each filter are the bit wide of 8 bits.Wherein, filter C_FIR_5's is input as { A
5, B
5, C
5, D
5, filter C_FIR 4 is input as { A
4, B
4, C
4, D
4... the rest may be inferred.In order to keep the precision of data after the filtering, filter is output as 13 bit signed numbers, is expressed as { b
5, b
4, b
3, b
2, b
1, b
0.More generally under the situation, the column filter pack module should be made of n+4 filter, and its output is expressed as { b
N+3, b
N+2B
0.Owing to adopted output register, data output will be later than clock cycle of input.
J point bank of filters module.As Fig. 8.The function of this module is to calculate the half-pixel data (as Fig. 2) be in position j, and its result is as required as the input of dateout or 1/4 pixel filter.Because n equals 2, J point bank of filters should be made of n+1=3 filter.Wherein each filter has tap coefficient (1,5,5 ,-1).4 inputs of each filter are the bit wide of 13 bits, this be because the input of J point bank of filters from the output of column filter group.Filter J_FIR_2 is input as { h
5, h
4, h
3, h
2, J_FIR_1 is input as { h
4, h
3, h
2, h
1, J_FIR_0 is input as { h
3, h
2, h
1, h
0.In order to keep the precision of data after the filtering, filter is output as 17 bit signed numbers, is expressed as { j
2, j
1, j
0.More generally under the situation, J point bank of filters module should be made of n+1 filter, and its output is expressed as { j
n, j
N-1... j
0.Owing to adopted output register, data output will be later than clock cycle of input.
1/4 bank of filters module.As Fig. 9.The function of this module is to calculate the data that are in 1/4 location of pixels, comprises position a, c, i, k, e, g, p, r, d, n, f and q (as Fig. 2).This module itself and what be indifferent to its output is the data of which 1/4 position, but decide by its input, promptly finish 1/4 regioselective function by the data preparation module.1/4 bank of filters should be made of n=2 filter.Wherein each filter has tap coefficient (1,7,7,1).It should be noted that this method not at e, g, these four positions of p and r are equipped with special bi-linear filter, and are to use 1/4 filter to finish this function, and implementation method is seen the form in " data preparation module ".In order to make filter be applicable to 1/4 all positions, each filter needs the input of 2 17 bits and the input of 2 13 bits.Owing to adopted skimble-scamble input width, the calculating that in fact each filter carries out is Y=X
3+ 7*8*x
2+ 7*X
1+ 8*x
0Y is the filtering result in the formula, X
3And X
1Be the inputs of 17 bits, x
2And x
0Be the inputs of 13 bits, * represents multiplication sign.Y is the signed number of one 21 bit, and filter moves to right Y and exports behind 9 bits.Output is expressed as { Q
1, Q
0, every 12 bit.More generally under the situation, 1/4 bank of filters module should be made of n filter, and its output is expressed as { Q
N-1, Q
N-2... Q
0.Owing to adopted output register, data output will be later than clock cycle of input.
The data preparation module.As Figure 10.The function of this module is the target location according to interpolation, selects from all outputs of delay time register group, line filter group, column filter group and these 4 modules of J point bank of filters and puts out needed data in order, is used for the input of 1/4 bank of filters module.To be example (as Fig. 2) to position a interpolation, the data that need use are ee, D, b, E.Correspond in this example, calculate Q
0Needed data are exactly { b
1, D
2, b
0, D
1.To be example to position d interpolation, the data that need use are ff, D, h, H again.Notice that in streamline ff is a h position data of carrying the previous clock cycle with respect to h.H then is the D position data that postpones a clock cycle with respect to D.And D and h are synchronous.Therefore, synchronous for the input that makes 1/4 filter in this example, calculate Q
0Needed data are exactly { h
4++, D
4+, h
4+, D
4.Wherein+represent clock cycle of data delay is exported again, ++ expression postpones two cycles.According to such thinking, obtain a table.When having represented the different target position, following table calculates Q
0Needed data.Obtain being used for Q
nTable, only the subscript in the table need be added that all n gets final product.
| The | Input | 1 | Input 2 | Input 3 | Input 4 |
| a | b 1 | D 2 | b 0 | D 1 | |
| c | b 0 | D 2 | b 1 | D 3 | |
| i | j 1 | h 2+ | j 0 | h 1+ | |
| k | j 0 | h 2+ | j 1 | h 3+ | |
| e | j 1 | D 3+ | j 1 | D 3+ | |
| g | j 1 | D 2+ | j 1 | D 2+ | |
| p | j 1 | D 3 | j 1 | D 3 | |
| r | j 1 | D 2 | j 1 | D 2 | |
| d | h 4++ | D 4+ | h 4+ | D 4 | |
| n | h 4 | D 4 | h 4+ | D 4+ | |
| f | j 1+ | b 1+ | j 1 | b 1 | |
| q | j 1 | b 1+ | j 1+ | b 1++ |
Take in order to reduce hardware resource, all data separating that need postpone in the table can be come out, after selecting with special selector, the unified delay.So obtain following two tables.
| The | Input | 1 | Input 2 | Input 3 | Input 4 |
| a | b 1 | D 2 | b 0 | D 1 | |
| c | b 0 | D 2 | b 1 | D 3 | |
| i | j 1 | V | j 0 | U | |
| k | j 0 | V | j 1 | U | |
| e | j 1 | U | j 1 | U | |
| g | j 1 | U | j 1 | U | |
| p | j 1 | D 3 | j 1 | D 3 | |
| r | j 1 | D 2 | j 1 | D 2 | |
| d | V+ | U | V | D 4 | |
| n | h 4 | D 4 | V | U | |
| f | U | V | j 1 | b 1 | |
| q | j 1 | V | U | V+ |
| The position | U | V |
| a | ||
| c | ||
| i | h 1+ | h 2+ |
| k | h 3+ | h 2+ |
| e | D 3+ | |
| g | D 2+ | |
| p | ||
| r | ||
| d | D 4+ | h 4+ |
| n | D 4+ | h 4+ |
| f | j 1+ | b 1+ |
| q | j 1+ | b 1+ |
As Figure 10, can realize these two the described functions of table with hardware approach.
Outlet selector and amplitude limiter module.As Figure 11.The function of this module is divided into two parts.First's function is to select dateout.When the target location is integer pixel point D, (consult Fig. 2), select { A
N+3, A
N+2... A
4.When the target location is the b point, select { b
n, b
N-1... b
1.When the target location is the h point, select { h
N+3, h
N+2... h
4.When the target location is 1/4 pixel, select { Q
N-1, Q
N-2... Q
0.N=2 especially, in this example.The second portion function is an amplitude limit, is about to dateout and is limited in 0 to 255 the scope: when amplitude limiter is input as when negative, be output as 0; When amplitude limiter input greater than 255 the time, output 255; Input is consistent with output under other situations.Especially, n=2 has then used two amplitude limiters in this example.
So far, realized a kind of brightness interpolator based on the AVS motion compensation.In this example, the pixel number of regulation parallel computation is n=2.Be not equal to 2 situation for n, only need simply expand (n was greater than 2 o'clock) or simplify (n equals at 1 o'clock) getting final product this routine structure.
Claims (10)
1. the VLSI implementation method based on the brightness interpolator of AVS motion compensation is characterized in that, has adopted the variable pipeline organization of a kind of progression, interpolation at the target location needs, automatically select 4 to 8 level production lines, carry out input, processing and the output of data simultaneously, comprise the steps:
(a) the input data are done the delay operation;
(b) line direction filtering;
(c) column direction filtering;
(d) J point filtering;
(e) to (a) and (b), (c) and (d) dateout of step put in order;
(f) 1/4th pixel filters;
(g) output channel selection, amplitude limit output.
2. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1, it is characterized in that, in step (a), if the pixel number of parallel computation is n, wherein between the n desirable 1 and 8, data are by the row input and output, and then the input data of every row need n+4 pixel at most, each clock cycle input data line is expressed as { A with it
N+3, A
N+2... A
0, wherein being total to the n+4 item, each represents the pixel of one 8 bit, these data is carried out three grades postpone operation, obtains the triplex row dateout, and with respect to the input data, this three line data has the delay of 1,2 and 3 clock cycle respectively, is expressed as { B
N+3, B
N+2... B
0, { C
N+3, C
N+2... C
0And { D
N+3, D
N+2... D
0.
3. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1 is characterized in that, in step (b), uses n+1 4 tap filters, and tap coefficient is [1,5,5 ,-1], and filter is numbered n and is decremented to 0; Wherein the n filter is input as { C
N+3, C
N+2, C
N+1, C
n, the n-1 filter be input as { C
N+2, C
N+1, C
n, C
N-1, the rest may be inferred, and the output of this group filter is expressed as { b
n, b
N-1... b
0, output is than clock cycle of input delay.
4. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1 is characterized in that, in step (c), uses n+4 4 tap filters, and tap coefficient is [1,5,5 ,-1], and filter is numbered n+3 and is decremented to 0; Wherein the n+3 filter is input as { A
N+3, B
N+3, C
N+3, D
N+3, the n+2 filter be input as { A
N+2, B
N+2, C
N+2, D
N+2, the rest may be inferred; The output of this group filter is expressed as { h
N+3, h
N+2... h
0, output is than clock cycle of input delay.
5. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1 is characterized in that, in step (d), uses n+1 4 tap filters, and tap coefficient is [1,5,5 ,-1], and filter is numbered n and is decremented to 0; Wherein the n filter is input as { h
N+3, h
N+2, h
N+1, h
n, the n-1 filter be input as { h
N+2, h
N+1, h
n, h
N-1, the rest may be inferred; The output of this group filter is expressed as { j
n, j
N-1... j
0; Output is than clock cycle of input delay.
6. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1 is characterized in that, in step (e), the purpose of this step is to provide the input data for (f) step; By to (a) and (b), (c) and (d) dateout in these four steps select and postpone operation, at the 1/4 pixel interpolation of diverse location, obtain n group dateout, 4 every group, be used for the input of 1/4th pixel filters.
7. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1 is characterized in that, in step (f), uses n 4 tap filters, and tap coefficient is [1,7,7,1], and filter is numbered n-1 and is decremented to 0; Its input data are from (e) output in step; The output of this group filter is expressed as { Q
N-1, Q
N-2... Q
0; Output is than clock cycle of input delay.
8. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1 is characterized in that, in step (g), at first selects n data from (a) and (b), (c), (d) with (f) the outputs in five steps; When the target location is the integer pixel point, promptly fractional coordinates Y and X are at 0 o'clock, select { A
N+3, A
N+2... A
4; When the target location is the b point, promptly when fractional coordinates Y=0, X=2, select { b
n, b
N-1... b
1; When the target location is the h point, promptly when fractional coordinates X=2, Y=0, select (h
N+3, h
N+2... h
4; When the target location is the j point, promptly when fractional coordinates Y=2, X=2, select { j
n, j
N-1... j
1; When the target location is point beyond the j point, select { Q
N-1, Q
N-2... Q
0; Use n amplitude limiter to handle this n data respectively subsequently, codomain is limited in 0 to 255, each length is 8 bits; Export the data of 8*n bit at last.
9. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1 is characterized in that, carries out input and output by row if desired, only needs fractional coordinates Y and X are exchanged.
10. the VLSI implementation method of the brightness interpolator based on the AVS motion compensation as claimed in claim 1, it is characterized in that, by changing the parameter n of definition in the step (a), i.e. the number of the pixel of parallel computation, thereby employed hardware resource quantity when adjusting specific implementation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100256704A CN100394797C (en) | 2006-04-13 | 2006-04-13 | Method of realizing VLSI of brightness interpolator based on AVS movement compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100256704A CN100394797C (en) | 2006-04-13 | 2006-04-13 | Method of realizing VLSI of brightness interpolator based on AVS movement compensation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1835587A true CN1835587A (en) | 2006-09-20 |
| CN100394797C CN100394797C (en) | 2008-06-11 |
Family
ID=37003166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100256704A Expired - Fee Related CN100394797C (en) | 2006-04-13 | 2006-04-13 | Method of realizing VLSI of brightness interpolator based on AVS movement compensation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100394797C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888554A (en) * | 2010-07-09 | 2010-11-17 | 西安交通大学 | VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter |
| CN103188487A (en) * | 2011-12-28 | 2013-07-03 | 联芯科技有限公司 | Convolution method in video image and video image processing system |
| CN104536555A (en) * | 2009-03-30 | 2015-04-22 | 高通股份有限公司 | Adaptive voltage scaling |
| WO2022116330A1 (en) * | 2020-12-02 | 2022-06-09 | Tcl华星光电技术有限公司 | Compensation method and compensation device for display panel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3590996B2 (en) * | 1993-09-30 | 2004-11-17 | ソニー株式会社 | Hierarchical encoding and decoding apparatus for digital image signal |
| US7110606B2 (en) * | 2003-06-12 | 2006-09-19 | Trieu-Kien Truong | System and method for a direct computation of cubic spline interpolation for real-time image codec |
| CN1186939C (en) * | 2003-08-01 | 2005-01-26 | 中国科学院计算技术研究所 | Real time 1/4 interpolation method based on multistage pipeline architecture |
| CN1306820C (en) * | 2004-07-29 | 2007-03-21 | 联合信源数字音视频技术（北京）有限公司 | Fractional pixel filter system and its filter method for video frequency decoding chip |
-
2006
- 2006-04-13 CN CNB2006100256704A patent/CN100394797C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104536555A (en) * | 2009-03-30 | 2015-04-22 | 高通股份有限公司 | Adaptive voltage scaling |
| CN104536555B (en) * | 2009-03-30 | 2017-05-24 | 高通股份有限公司 | Adaptive voltage scaling |
| CN101888554A (en) * | 2010-07-09 | 2010-11-17 | 西安交通大学 | VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter |
| CN101888554B (en) * | 2010-07-09 | 2013-05-22 | 西安交通大学 | VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter |
| CN103188487A (en) * | 2011-12-28 | 2013-07-03 | 联芯科技有限公司 | Convolution method in video image and video image processing system |
| CN103188487B (en) * | 2011-12-28 | 2016-11-23 | 联芯科技有限公司 | Convolution method in video image and video image processing system |
| WO2022116330A1 (en) * | 2020-12-02 | 2022-06-09 | Tcl华星光电技术有限公司 | Compensation method and compensation device for display panel |
| US11790863B2 (en) | 2020-12-02 | 2023-10-17 | Tcl China Star Optoelectronics Technology Co., Ltd. | Compensation method of display panel and compensation device thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100394797C (en) | 2008-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110533164B (en) | Winograd convolution splitting method for convolution neural network accelerator | |
| CN1009772B (en) | Devices for computing monodimentional cosine transforms and image coding device and decoding device ineluding such computation devices | |
| CN1102026A (en) | Reconfigurable programmable digital filter architecture | |
| CN101076008A (en) | Method and apparatus for processing clipped wave | |
| CN1246765A (en) | Method and system for digital signal interpolation | |
| CN1909529A (en) | 3780-point discrete fourier transformation processor | |
| CN1992517A (en) | Programmable interpolated filter device and realizing method therefor | |
| CN1668108A (en) | Resolution changing method and apparatus | |
| CN1835587A (en) | Method of realizing VLSI of brightness interpolator based on AVS movement compensation | |
| Sau et al. | Challenging the best HEVC fractional pixel FPGA interpolators with reconfigurable and multifrequency approximate computing | |
| CN1575587A (en) | Polyphase filter combining vertical peaking and scaling in pixel-processing arrangement | |
| CN1852442A (en) | Layering motion estimation method and super farge scale integrated circuit | |
| CN1592103A (en) | N step half-band interpolating filter | |
| CN1946178A (en) | VLSI device for movement evaluation and method for movement evaluation | |
| CN1703094A (en) | Image interpolation apparatus and methods that apply quarter pel interpolation to selected half pel interpolation results | |
| CN1297940C (en) | Image zooming method | |
| CN1448871A (en) | Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure | |
| CN1099071C (en) | Digital filter device having bit shifter unit | |
| Lin et al. | Low-power parallel tree architecture for full search block-matching motion estimation | |
| CN1640113A (en) | Noise filtering in images | |
| CN103092559A (en) | Multiplying unit structure for discrete cosine transformation (DCT)/inverse discrete cosine transformation (IDCT) circuit under high efficiency video coding (HEVC) standard | |
| CN110737869B (en) | DCT/IDCT multiplier circuit optimization method and application | |
| CN100345437C (en) | Multiplierless pyramid filter | |
| CN110555519B (en) | Low-complexity convolutional neural network architecture based on symbol random calculation | |
| CN1186939C (en) | Real time 1/4 interpolation method based on multistage pipeline architecture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080611 Termination date: 20110413 |