CN115473512B - Parallel timing synchronization method based on polyphase filter bank structure - Google Patents
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Abstract
The invention discloses a parallel timing synchronization method based on a polyphase filter bank structure, which develops a parallel timing error correction technology based on the polyphase filter bank, wherein the filtering calculation rate of each channel is equal to the symbol rate, and the requirement of high-speed data signals on a digital processing module is effectively reduced; meanwhile, the parallel timing error correction scheme provided by the invention can respectively carry out filtering correction on each judgment sampling point, is suitable for the situation that the sampling rate is not matched with the symbol rate, and is not an advantage of other parallel timing correction methods.
Description
Technical Field
The invention belongs to the technical field of digital signal processing, and particularly relates to a parallel timing synchronization method based on a polyphase filter bank structure, which is suitable for timing error correction of a receiving demodulation technology in high-speed data transmission.
Background
In a high-speed wireless communication system, a digital receiving demodulation module is required to have an extremely high operation rate, and in order to reduce the calculation load of a digital processing module, a parallel demodulation mode is adopted for signals, so that the current main research content is adopted. The broadband signal can be split into a group of sub-signals with different frequency bands by using a filter bank technology, and the signal extractor and the filter can be interchanged in position by the Noboolean identity transformation to realize parallel deceleration processing.
The polyphase filter bank based channelization technique is derived from a complex exponential filter bank, and fig. 1 is a block diagram of a typical complex exponential modulation filter bank. The signal is filtered by a band-pass filter in the mth path to obtain a narrow-band signal of a corresponding frequency band, then the narrow-band signal is extracted and reduced in speed, and then the signal is down-converted to a baseband, so that a plurality of paths of sub-band signals can be obtained, and the frequency band synthesis operation can be regarded as the inverse process of the decomposition operation. When the analysis and synthesis filter bank satisfies the complete reconstruction condition and no subband signal processing is performed, the reconstructed signal may be considered as a delayed result of the input signal.
The multi-phase implementation based on the framework can greatly reduce the processing speed of the sub-band, and foreign part scholars have deduced the sub-band matched filtering, timing error estimation and correction and carrier frequency error detection technology by utilizing the multi-phase filter bank technology, thus completing the complete demodulation process of the broadband digital signal under certain limiting conditions.
After the digital receiver down-converts the signal to the baseband and completes the matching and filtering, the decision is needed, and because the sampling rate and the time delay cannot be completely synchronous with the signal in the analog-digital conversion process, the deviation exists between the sampling decision point and the optimal decision point, and the deviation leads to the performance reduction of the demodulation error code, so the timing synchronization is needed, and the decision time is adjusted to the optimal position.
The digital timing synchronization key technology comprises two parts, namely timing error detection and timing error correction, the design of a feedback loop is adopted in common use at present, the timing error is estimated by utilizing the information of the current judgment point, the timing error is smoothed by a loop filter and then is used for correcting the judgment value of the next time, and the feedback loop is formed in such a way that the convergence can be realized after the data accumulation with less time. Such methods perform well under serial demodulation architecture for long-time communications, but are difficult to implement in parallel due to the presence of feedback loops. In high-speed wireless communication with increasing data volume, a parallel demodulation architecture must be adopted, so that developing a timing synchronization technology suitable for a parallel structure becomes a research hotspot.
Currently, foreign scholars design a parallel synchronous error correction method by adopting a polyphase filter bank architecture, but the method is only suitable for the condition that the sampling rate is an integral multiple of the symbol rate, and the method is immediately invalid when the sampling rate and the symbol rate cannot be tuned (namely, the ratio of the sampling rate to the symbol rate is irrational number). In environments where all-digital receivers have become the dominant trend, in order to increase the flexibility and universality of digital demodulation systems, developers struggle to move the analog-to-digital conversion module forward as much as possible, which tends to result in a more fixed sampling rate, requiring sample rate and symbol rate tuning to be difficult or even impossible in most cases.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a parallel timing synchronization method based on a polyphase filter bank structure, which can implement parallel timing correction in case of a mismatch between a sampling rate and a symbol rate.
A parallel timing synchronization method based on a polyphase filter bank structure, comprising:
the first step, after the signals are filtered by each synthesis filter in the parallel structure of the polyphase filter bank, each channel signal is sent to a buffer, and each channel stores the values of 3 sampling points;
second, a fractional delay filter is calculated according to the following formula:
representing a time domain variable of the filter, D being a filter order;
third step, according to the decision time m k At the location, a correction factor is allocated to each channel; let the channel number where the sampling decision point is located be q, specifically the following three cases:
(1) When q is smaller than D/2, the previous time values of the D/2+q+1-D channels are multiplied by l (-D/2+1) to l (1-q) respectively; the current time values of the 1 st to q+D/2 th channels are multiplied by l (2-q) to l (D/2+1) correspondingly respectively; the current time values of the 3D/2+q+1-2D channels are multiplied by l (-D/2+1) to l (1-q) respectively; the values of the 3D/2-q+1-2D channels at the next time are multiplied by l (2-q) to l (D/2+1) correspondingly;
(2) When q=D/2, the current time values of the 1 st to D channels are multiplied by l (-D/2+1) to l (0) respectively; the values of the D+1-2D channels at the next time are multiplied by l (1) -l (D/2) correspondingly;
(3) When q is greater than D/2, the current time values of the q-D/2+1-D channels are multiplied by l (-D/2+1) to l (D-q+1) respectively; the values of the 1 st to q-D/2 th channels at the next time are multiplied by l (D-q+2) to l (D/2) correspondingly; the values of the q+D/2+1-2D channels at the next time are multiplied by l (-D/2+1) to l (D-q+1) respectively; the lower time values of the D+1 to q+D/2 channels are multiplied by l (D-q+2) to l (D/2) respectively;
fourth, adding the corrected data of all channels to obtain a correction value of the judgment moment;
fifthly, when q is more than or equal to D/2, discarding the value at the last moment in the buffer memory, and storing the value at the next moment to wait for calculation;
and repeating the second step to the fifth step to realize timing synchronization.
Preferably, in the decomposition part, the signals are extracted and filtered, and then IFFT conversion is carried out, so as to obtain multi-path parallel data;
in the synthesis part, the sub-band signals are firstly subjected to IFFT transformation, then filtered and then interpolated, and finally delayed and accumulated, thus obtaining the recovered signals.
Preferably, C (z) employs a raised cosine filter,h (z) and F (z) are the analysis filter and the synthesis filter, respectively, in the polyphase filter bank.
Preferably, H (z) and F (z) are the same square root raised cosine filter.
The invention has the following beneficial effects:
the invention develops a parallel timing error correction technology based on a polyphase filter bank, and the filtering calculation rate of each channel is equal to the symbol rate, thereby effectively reducing the requirement of high-speed data signals on a digital processing module; meanwhile, the parallel timing error correction scheme provided by the invention can respectively carry out filtering correction on each judgment sampling point, is suitable for the situation that the sampling rate is not matched with the symbol rate, and is not an advantage of other parallel timing correction methods.
Drawings
FIG. 1 is a block diagram of a complex exponential modulated filter bank;
FIG. 2 is a parallel demodulation architecture based on a polyphase filter bank;
FIG. 3 is an M-channel, D-decimated complex exponential filter bank model;
FIG. 4 is a multi-phase implementation of an analysis filter bank;
FIG. 5 is an M-channel, D-decimated polyphase filter bank structure;
FIG. 6 is a block diagram of a subband implementation of matched filtering;
fig. 7 is a schematic diagram of a parallel timing correction calculation rule when m=8, d=4;
fig. 8 is a timing error correction comparison of the two methods.
Detailed Description
The invention will now be described in detail by way of example with reference to the accompanying drawings.
1.1 System composition and working principle
1.1.1 System composition
The simplified overall block diagram of the parallel demodulation architecture based on the polyphase filter bank is shown in fig. 2, and the part shown by the dotted line box in the figure is the main content of the present invention. After the received digital signal is matched and filtered, in order to obtain the optimal sampling point time, firstly, timing error estimation is carried out, and the estimated timing offset is obtainedA series of calculation is carried out to obtain correction factors, and parallel matched filtering signals andthe correction factors are multiplied, and after interpolation and delay addition, corrected decision point values can be obtained.
1.1.2 principle of operation
This section mainly introduces the basic principle of implementing parallel demodulation by the polyphase filter bank architecture, mainly including the design of polyphase analysis and synthesis filter bank structures, and satisfies the design of fully reconstructed prototype filters and the derivation of subband matched filtering.
1.1.2.1 Multi-phase analysis and Synthesis Filter Bank implementation Structure
The structure of the M-channel, D-times decimated cascaded complex exponential filter bank is shown in FIG. 3, where H m (z) and F m (z), m=0, …, M-1 is a band-pass filter, the wideband signal is extracted by D times after being filtered by band-pass filters with different gating frequencies, and in order to avoid aliasing, D is less than or equal to M, and then the wideband signal is down-converted to a baseband, so that an M subband signal can be obtained. The synthesis part is the inverse of the analysis part, taking into account the subband signal processing block at the moment, if the filter H m (z) and F m (z) the power complementary condition can be satisfied, and the out-of-band spectrum is completely filtered, the model realizes the complete reconstruction of the signal.
The frequency domain expression of each node signal is derived, and the band-pass filters for different frequency bandsThe low-pass prototype filter H (z) thereof can be expressed as:
wherein ,WM ＝e -j2π/M Therefore:
d times extraction is carried out on the signals after band-pass filtering, and then the obtained signals are obtained:
then down-conversion processing is performed:
substituting equation (3) into equation (4) yields a frequency domain representation of each subband signal:
irrespective of the subband signal processing block, there is
Further to
The polyphase implementation of the analysis filter bank is derived by first performing a polyphase decomposition of the prototype filter H (z)
wherein
Substituting formula (9) into formula (3) to obtain
When M is an integer multiple of D,the above can be further deformed into
wherein [·]|↓D Representing the D-fold extraction of the sequence, the accumulation in equation (11) can be implemented with IDFT operations, according to the definition of the discrete fourier transform, and therefore:
the block diagram of the implementation of equation (13) is shown in fig. 4, where IDFT operations are implemented with a more efficient IFFT, it can be found that by performing polyphase decomposition on the prototype filter, the decimation operation is adjusted before the filtering computation, thus greatly reducing the operation rate.
The derivation method of the polyphase synthesis filter bank is substantially the same as that of the polyphase analysis filter bank, and the polyphase form of the synthesis prototype filter is:
wherein
Substituting formula (14) into formula (7) yields:
the last line of equation (16) shows that subband signal Y may be processed k (z) after IDFT transformation, directly performing polyphase synthesis filtering, and then performing interpolation operation, thereby realizing a deceleration process, wherein the implementation process is an inverse process of the polyphase analysis filter bank structure.
Fig. 5 shows an overall implementation structure of the M-channel, D-time decimated polyphase filter bank, where M-channel parallel data can be obtained by performing IFFT transformation after signal decimation and filtering. The synthesis part firstly carries out IFFT conversion on the subband signals, then filters and interpolates, and finally delays and accumulates to obtain the recovered signals. The cascaded polyphase filter bank structure provides a better scheme for signal parallel deceleration processing, and the extraction multiple can be adjusted according to actual conditions, and only the condition of dividing M by D is required to be satisfied.
Complete reconstruction conditions for 1.1.2.2 polyphase Filter banks
From equation (8), we can get the relation of Y (z) to X (z), we describe equation (8) in matrix form below, defining:
so that
From the above, it can be seen that the polyphase filter bank must require F to meet the complete reconstruction conditions T H (M×1) =d, and aliased partI.e.
wherein The filter C (z) satisfies the power complementary condition. In the invention, C (z) adopts a raised cosine filter with good performance, H (z) and F (z) are the same square root raised cosine filter, the pass band is smooth, the transition band power is complementary, the requirement of the formula (24) can be met, the roll-off factor alpha of the raised cosine filter can be flexibly adjusted, and the aliasing can be avoided by designing the order of the filter and the roll-off factor.
Considering equation (25) below, taking d=1 when d=m, then claimSince the normalized passband bandwidth of the prototype filter is 1/M, the elimination of aliasing must result in a prototype filter designed with extremely narrow transition bandwidths and large stopband attenuation, which are severalIt is not possible to realize. Therefore, the invention relaxes the design requirement of the prototype filter by reducing the size of the decimation factor D. By letting d=m/2, a 2-fold oversampled polyphase filter bank parallel architecture was designed, with the relevant parameter sizes listed in table 1.
Table 1 polyphase filter bank related parameters
1.1.2.3 parallel filtering technique
Assuming that the signal X (z) has been down-converted to baseband, the matched filtering calculation of X (z) when the filter bank satisfies the complete reconstruction condition can be expressed as
Where Y' (z) is the frequency domain representation of the matched filtered signal and Q (z) is the frequency domain representation of the matched filter. To achieve parallel matched filter computation, equation (26) is rewritten as:
wherein Definition F' (z) satisfies
Then there is
As can be seen from equation (29), the matched filtering operation can be transferred to the subband by only designing the filter F' (z) satisfying equation (28), and the implementation block diagram is shown in fig. 6. The convolution-extraction and interpolation-convolution operations in the figure can utilize the multirate filter bank theory to carry out the speed reduction processing, and the part in the dotted line frame can be obtained by pre-calculating according to the prior information of demodulation, thereby reducing the difficulty of demodulating the data transmission signal in real time.
1.2 parallel timing correction principle based on fractional delay Filter
When the digital signal meets the Nyquist sampling rate, the original signal can be completely recovered, and the receiving end clock and the transmitting end are not completely synchronous in wireless transmission, so that the symbol sampling judgment deviates from the optimal sampling point, the sampling moment with deviation is corrected, and a fractional delay filter is needed to be used. The invention adopts a truncated sinc function as a fractional delay filter and derives the parallel implementation form based on a polyphase filter bank structure.
In the synthesis filter bank section of fig. 5, the parallel signal after IFFT is set to be P m (z), m=0, … M-1, there are:
performing timing error correction on the synthesized signal Y (z), and setting the fractional delay filter to L (z), then:
in order to implement L (z) in parallel, it is subjected to multiphase decomposition:
substituting formula (32) into (31) to obtain:
equation (33) reduces the rate of operation by moving the fractional delay filter by polyphase decomposition before interpolation. Note that the final sampling decision process only needs to obtain the result of a certain sample point correcting the specific fractional delay, so that the multiphase filtering calculation for L (z) is not required to be completed completely, and only the sampling point at the decision time is required to be filtered, and the filtering rate is consistent with the symbol rate.
Definition of the definitionWhere (n) represents the output value at the nth time. Fig. 7 shows a schematic calculation rule of the parallel timing correction method according to the present invention when m=8, d=4, and the fractional delay filter order is D, wherein t is i I=0, 1, … represents the output time of the serial signal after synthesis, the rate of which is equal to the data sampling rate, it can be seen that each convolution calculation is obtained by multiplying the data of a certain time of 8 channels by the corresponding filter factor and adding, and each time the correction of one decision time is completed, the time of the data of different channels differs by 2 or 3, which is the delay caused by the filter and the non-maximum extraction structure.
The fractional delay filter is obtained by adopting a truncated sine function, the order of the filter is D, and when the estimated timing error value isThe filter l (n) can be calculated by the following equation:
wherein ,fp For the symbol rate of the signal, the decision time m is determined when the correction calculation of the sampling point is performed k Should be multiplied correspondingly with l (0), m k The update rate of (2) is the same as the symbol rate. Thus, we can divide the calculation process of the parallel timing correction technique into the following 5 steps:
the first step, after the signals are filtered by the synthesis filter in M channels, the signals are sent into a buffer, and each channel stores the values of 3 sampling points;
second, the result of the front end timing error detection module is utilized according to equation (34)Calculating a fractional delay filter;
third step, according to the decision time m k At the site, a correction factor is assigned to each channel. Let the channel number where the sampling decision point is located be q, this time division is divided into three cases:
1. when q is smaller than D/2, the previous time values of the D/2+q+1-D channels are multiplied by l (-D/2+1) to l (1-q) respectively; the current time values of the 1 st to q+D/2 th channels are multiplied by l (2-q) to l (D/2+1) correspondingly respectively; the current time values of the 3D/2+q+1-2D channels are multiplied by l (-D/2+1) to l (1-q) respectively; the values of the 3D/2-q+1-2D channels at the next time are multiplied by l (2-q) to l (D/2+1) respectively.
2. When q=D/2, the current time values of the 1 st to D channels are multiplied by l (-D/2+1) to l (0) respectively; the values of the D+1th to 2D channels at the next time are multiplied by l (1) to l (D/2) respectively.
3. When q is greater than D/2, the current time values of the q-D/2+1-D channels are multiplied by l (-D/2+1) to l (D-q+1) respectively; the values of the 1 st to q-D/2 th channels at the next time are multiplied by l (D-q+2) to l (D/2) correspondingly; the values of the q+D/2+1-2D channels at the next time are multiplied by l (-D/2+1) to l (D-q+1) respectively; the lower time values of the D+1 to q+D/2 th channels are multiplied by l (D-q+2) to l (D/2), respectively.
And fourthly, adding M data after correction of all channels to obtain a correction value of the judgment moment.
And fifthly, the sequence number q of the channel where the sampling decision point is located is circularly changed according to the sequence of 1-D, when q is more than or equal to D/2, the value at the last moment is discarded in the buffer, and the value at the next moment is stored for waiting calculation, so that 3 signal data are always stored in the buffer.
The steps are repeated, and real-time processing of parallel timing error correction can be realized.
5.3 experimental verification
And verifying the performance of the parallel timing error correction technology by utilizing a MATLAB simulation means, wherein relevant parameters required by simulation are shown in a table 2, and the order of the fractional delay filter is the same as the extraction multiple.
Table 2 parameters required for simulation
| Sampling rate | Symbol rate | Number of channels | Extraction multiple | Timing error |
| 128MHz | 32MHz | 16 | 8 | 0.125 |
In fig. 8, the correction error of the method is about 0.45 times of that of the piecewise square interpolation algorithm when the parallel correction method provided by the invention is compared with the correction error of the traditional piecewise square interpolation algorithm under the zero noise condition, because the parallel correction algorithm uses 8-point data information and the piecewise square interpolation algorithm uses only 4-point data information when the number of channels is 16, and the correction performance of the method is obviously better than that of the traditional method. Meanwhile, as the number of channels increases, the order of the fractional delay filter also increases, so that the performance is further improved, and the traditional interpolation algorithm requires fixed data information quantity and has low flexibility.
The calculation amount of the algorithm is analyzed and compared, only the multiplication condition is considered, and the piecewise square interpolation algorithm needs to calculate 4 information data and 4 information data and />Thus requiring a total of 8 multiplication operations, which require a calculated multiplication rate of 8 xf for conventional serial timing correction p . The correction method adopted by the invention has the operation times related to the order of the fractional delay filter, and when the order of the filter is equal to the extraction multiple D, 2D multiplication operations are needed, but because the method is operated based on a parallel architecture, the number of parallel branches is M=2D, and when one judgment sampling point is corrected, the calculation multiplication times of each channel are only 1, so the calculation multiplication rate needed in each independent channel is only f by the algorithm provided by the invention p Has better application prospect in a high-speed data transmission system.
In summary, the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A parallel timing synchronization method based on a polyphase filter bank structure, comprising:
the first step, after the signals are filtered by each synthesis filter in the parallel structure of the polyphase filter bank, each channel signal is sent to a buffer, and each channel stores the values of 3 sampling points;
second, a fractional delay filter is calculated according to the following formula:
wherein ,representing the estimated timing error value; />Is the symbol rate of the signal; />Time domain variable representing a filter,/>Is the filter order;
third step, according to the decision timeAt the location, a correction factor is allocated to each channel; let the channel number where the sampling decision point is located be q, specifically the following three cases:
(1) When (when)At the time->The last time value of the channel is respectively equal to +.>Corresponding multiplication; first->The current time value of the channel is respectively equal to +.>Corresponding multiplication; first, theThe current time value of the channel is respectively equal to +.>Corresponding multiplication; first, theThe value of the next time of the channel is respectively equal to +.>Corresponding multiplication;
(2) When (when)At the time->The current time value of the channel is respectively equal to +.>Corresponding multiplication; first, theThe value of the next time of the channel is respectively equal to +.>Corresponding multiplication;
(3) When (when)At the time->The current time value of the channel is respectively equal toCorresponding multiplication; first->The value of the next time of the channel is respectively andcorresponding multiplication; first->The value of the next time of the channel is respectively andcorresponding multiplication; first->The lower time values of the channels are respectively equal toCorresponding multiplication;
fourth, adding the corrected data of all channels to obtain a correction value of the judgment moment;
fifth step, whenWhen the value of the last moment is discarded in the buffer, the value of the next moment is stored for waiting to be calculated;
and repeating the second step to the fifth step to realize timing synchronization.
2. The parallel timing synchronization method based on a polyphase filter bank structure as claimed in claim 1, wherein in the decomposition part of the polyphase filter bank structure, the signals are extracted and filtered, and then IFFT is performed, so as to obtain multiple paths of parallel data;
in the synthesis part of the polyphase filter bank structure, the subband signals are firstly subjected to IFFT transformation, then filtered and then interpolated, and finally delayed and accumulated to obtain the recovered signals.
3. A parallel timing synchronization method based on a polyphase filter bank structure as claimed in claim 1,by means of raised cosine filters->，/> and />Respectively an analysis filter and a synthesis filter in a polyphase filter bank.
4. A parallel timing synchronization method based on a polyphase filter bank structure as claimed in claim 3,and->Is the same square root raised cosine filter.
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