CN114024553B - Multi-channel baseband-to-radio frequency up-conversion method and system and electronic equipment - Google Patents
Multi-channel baseband-to-radio frequency up-conversion method and system and electronic equipment Download PDFInfo
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Abstract
The method adopts multi-channel branches to process signals to be processed in parallel, the signals to be processed are subjected to multi-level up-conversion and interpolation filtering, and a multi-phase combining structure is designed in the up-conversion process, so that target signals are obtained and output. The signals to be processed are subjected to multi-channel parallel processing, and the traditional complex up-conversion algorithm is structurally optimized through the algorithm and the structural design of multi-level up-conversion, multi-phase interpolation filtering and multi-phase combination, so that the resource usage of the system occupied by the up-conversion algorithm is reduced, the running speed of the system can be improved, and the requirement of the system on hardware can be reduced.
Description
Technical Field
The present application relates to the field of signal processing, and in particular, to a method, a system, and an electronic device for up-conversion from a multi-channel baseband to a radio frequency.
Background
The digital frequency conversion technology is a technical method for moving the frequency spectrum of an input signal by using a digital signal processing method, and relates to the field of digital signal processing. In the field of digital television modulation technology, baseband signals need to be shifted from zero frequency to a modulation frequency band special for broadcasting and television, so that RF signals are transmitted to the home.
In the current up-conversion mode of signal spectrum, the sampling rate of the radio frequency digital-to-analog conversion DAC cannot be less than 2 times of the highest frequency of the sampled signal by the Nyquist sampling theorem, so that the target sampling frequency f exists dac ≥2*f max . Since in direct digital RF up-conversion systems f dac Internal operating clock f of larger, general FPGA/ASIC chip clk The target sampling frequency f is difficult to be reached dac It needs to be realized by a complex up-conversion algorithm.
However, the complex algorithm occupies a large amount of system resources, which not only increases the hardware requirement of the product and increases the product cost, but also affects the system operation speed due to excessive system resources occupation and generates a large system delay.
Disclosure of Invention
The application provides an up-conversion method, system and electronic equipment from a multi-channel baseband to a radio frequency, and the up-conversion processing method with less resource occupation can be used for reducing the system resource occupation of the equipment in the up-conversion processing process.
The application discloses an up-conversion method from a multi-channel baseband to a radio frequency, which is applied to an up-conversion system and comprises the following steps:
performing parallel processing on signals to be processed by adopting multi-channel branches;
up-sampling a multi-channel baseband sampling rate to an initial sampling frequency through resampling filtering, wherein the initial sampling frequency is the clock frequency f of a main processing module clk ；
Carrying out two-stage up-conversion and first-stage multi-phase interpolation filtering on a signal to be processed so as to change the sampling frequency of the signal to be processed into an intermediate sampling frequency, and moving a central frequency point to an intermediate signal frequency f'; wherein the intermediate sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac Half of (1);
combining the multi-channel signals to be processed after two-stage up-conversion to obtain combined signals;
performing multi-phase interpolation filtering on the combined signal to change the intermediate sampling frequency into a target sampling frequency, wherein the target sampling frequency is an interface data sampling rate f of a digital-to-analog converter dac ；
Shifting the central frequency point of the signal to be processed to the target signal frequency through third-level up-conversion based on the target sampling frequency to obtain a target signal;
and outputting the target signal through a digital-to-analog converter.
In an embodiment, the performing two-stage up-conversion and first-stage polyphase interpolation filtering on the signal to be processed to change the sampling frequency of the signal to be processed to an intermediate sampling frequency, and shifting the central frequency point to the intermediate signal frequency includes:
moving the central frequency point of the signal to be processed to a first signal frequency f' through a first-stage up-conversion based on the initial sampling frequency;
performing polyphase interpolation filtering on the signal to be processed after the first-stage up-conversion is completed so as to change the initial sampling frequency into an intermediate sampling frequency;
and moving the central frequency point of the signal to be processed to the intermediate signal frequency f' through the second-stage up-conversion based on the intermediate sampling frequency.
In one embodiment, the first signal frequency f "has a value range of
In one embodiment, the step frequency of the second up-conversion stage is
The ratio of the intermediate sampling frequency to the stepping frequency is R =2 × n.
In one embodiment, the polyphase interpolation filtering employs a FIR interpolation filter.
In one embodiment, the step of polyphase interpolation filtering includes:
and if the N-phase interpolation filtering is adopted, obtaining the sampling frequency through N parallel sub-filtering operations after the N-phase interpolation.
In one embodiment, the multiple channels are 2 × n channels, and the clock frequency of the main processing module
In one embodiment, the outputting the target signal through a digital-to-analog converter includes:
and converting the multiphase parallel data into single-phase serial data through a high-speed parallel-serial conversion interface and sending the single-phase serial data to a radio frequency digital-to-analog converter.
In one embodiment, the upsampling the baseband sampling rate of the multiple channels to the initial sampling frequency by resampling filtering includes:
and (5) up-sampling the signal to be processed by adopting a Farrow resampling filter.
The application also provides a multichannel baseband to radio frequency up-conversion system, including:
the signal input module is used for carrying out parallel processing on the signals to be processed by adopting multi-channel branches;
a resampling filter module for up-sampling the multi-channel baseband sampling rate to an initial sampling frequency, wherein the initial sampling frequency is the clock frequency f of the main processing module clk ；
The first up-conversion module is used for performing two-stage up-conversion and first-stage multiphase interpolation filtering on a signal to be processed so as to change the sampling frequency of the signal to be processed into an intermediate sampling frequency, and the central frequency point is moved to an intermediate signal frequency f'; wherein the intermediate sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac Half of (1);
the multi-phase combiner module is used for combining the multi-channel signals to be processed after two-stage up-conversion to obtain combined signals;
a multiphase interpolation filtering module for performing multiphase interpolation filtering on the combined signal to change the intermediate sampling frequency into a target sampling frequency, wherein the target sampling frequency is an interface data sampling rate f of a digital-to-analog converter dac ；
The second up-conversion module is used for moving the central frequency point of the signal to be processed to the target signal frequency through the third-level up-conversion based on the target sampling frequency to obtain a target signal;
and the output module is used for outputting the target signal through the digital-to-analog converter.
The present application further provides an electronic device, which includes:
a processor; and
a memory, in which a computer program is stored, and the processor is configured to execute the multi-channel baseband-to-radio frequency up-conversion method according to any one of the above items by calling the computer program stored in the memory.
From the above, according to the multichannel baseband-to-radio frequency up-conversion method, system and electronic device, the signals to be processed are subjected to multichannel parallel processing, and the traditional complex up-conversion algorithm is structurally optimized through the algorithm and structural design of multi-stage up-conversion, multi-phase interpolation filtering and multi-phase combination, so that the resource usage of the system occupied by the up-conversion algorithm is reduced.
Drawings
Fig. 1 is a flowchart illustrating an implementation of a multi-channel baseband-to-radio frequency up-conversion method according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a multi-channel baseband-to-radio frequency up-conversion method according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a spectrum shifting process according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a principle of polyphase interpolation filtering provided in the embodiment of the present application.
Fig. 5 is a schematic diagram of a multi-phase combining circuit provided in an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a multi-channel baseband-to-radio frequency up-conversion system according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will make the advantages and features of the present application more readily appreciated by those skilled in the art, and thus will more clearly define the scope of the invention.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; may be mechanically, electrically or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Referring to fig. 1, a flow chart of an implementation of the multi-channel baseband-to-radio frequency up-conversion method according to the embodiment of the present application is shown.
The up-conversion method from the multi-channel baseband to the radio frequency is applied to an up-conversion system, the up-conversion system can be applied to signal processing of a digital television, or the field of digital signal processing for moving a lower frequency band to a higher frequency band based on baseband signals, and the specific field type can be determined according to actual conditions.
As shown in fig. 1, the multi-channel baseband-to-radio frequency up-conversion method includes:
101. and performing parallel processing on the signals to be processed by adopting multi-channel branches.
Wherein, the frequency range of all frequency points supported by the system is set as f min ，f max ]The intermediate frequency point is f mid The interface data sampling rate of the DAC is f dac Internal master module processing clock frequency of f clk 。
Internal operation clock f of general FPGA/ASIC chip clk Is difficult to reach f dac The signals to be processed can be processed in parallel through the multi-channel branches. In an embodiment, this time may be set
When part of the modules need to work at the sampling rate f dac And 2 × N parallel branches are adopted for simultaneous processing, which is a multiphase representation structure of sampling rate conversion, wherein N can be determined according to design requirements, and N =2 or N =4 can be adopted from the viewpoints of processing convenience and optimization.
Setting the frequency point position of the final up-conversion of a certain channel as f e [ f min ,f max ]If so, let f' = f-f mid In this case, f' may be a positive or negative value in the range of f min -f mid ,f max -f mid ]。
Of course, the number of the channels and the value of N may be determined according to design requirements, and the present application does not limit the above values.
102. Up-sampling a multi-channel baseband sampling rate to an initial sampling frequency through resampling filtering, wherein the initial sampling frequency is the clock frequency f of a main processing module clk 。
Symbol rate of baseband signal relative to working clock frequency f in chip clk Is generally small, the symbol rate may be fixed or variable according to different standards, and f clk The integer division does not always exist, and the sampling rate is converted into the sum of f by a mode of firstly resampling clk The sampling rate with integer division relation is then up-sampled to f clk . Wherein the initial sampling frequency is the clock frequency f clk 。
In one embodiment, the resampling filtering may use a Farrow resampling filter to upsample the signal to be processed. The Farrow resampling filter is a module integrating resampling and upsampling functions, and the Farrow resampling filter can reduce the length of a link and reduce the use of resources. The specific type of resampling filter may be determined according to different design requirements.
103. Two-stage up-conversion and first-stage multiphase interpolation filtering are carried out on the signal to be processed, so that the sampling frequency of the signal to be processed is changed into an intermediate sampling frequency, and the central frequency point is shifted to an intermediate signal frequency f'.
Up-conversion refers to shifting the signal spectrum from the lower frequency band to the higher frequency band.
Wherein, the intermediate sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac One half, i.e.
Referring to fig. 2, a structure of a multi-channel baseband-to-radio frequency up-conversion method according to an embodiment of the present disclosure is shown.
With reference to fig. 2, performing two-stage up-conversion and first-stage polyphase interpolation filtering on a signal to be processed to change the sampling frequency of the signal to be processed to an intermediate sampling frequency, and shifting the central frequency point to an intermediate signal frequency f' includes:
1031. and moving the central frequency point of the signal to be processed to a first signal frequency f' through the first-stage up-conversion based on the initial sampling frequency.
Referring to fig. 3, a principle of a spectrum shifting process provided in an embodiment of the present application is shown.
Wherein the signal sampling rate is raised to f clk After f is clk And the sampling rate is shifted to f' from the 0Hz position through the first-stage up-conversion module. Specifically, the first signal frequency f "has a value range of
The first stage of frequency shifting may be referred to as an accurate frequency shift. The principle of spectrum shifting can be expressed by the following formula:
(I + jQ) represents a center frequency f after spectral shaping 0 Baseband signal, =0Hz>0 represents the final frequency point position of the frequency shift after the up-conversion, and the frequency spectrum shifting operation is essentially complex multiplication operation as seen by a formula.
Specifically, order
Wherein M is an integer and f "is limited to the range
The original range is defined as f min ，f max ]F is converted to the range of
F "of (1).
1032. And performing multi-phase interpolation filtering on the signal to be processed after the first-stage up-conversion is completed so as to change the initial sampling frequency into an intermediate sampling frequency.
The signal output by the first-stage up-conversion module needs to be up-sampled again to increase the sampling rate, and the sampling rate is increased to the value obtained by N-phase interpolation filtering
The device is
I.e. the intermediate sampling frequency. Polyphase interpolation filtering is still interpolation filtering in nature.
In one embodiment, a general FIR interpolation filter can be used, and polyphase is a representation of its implementation, and an 8-step FIR filter is taken for better illustration of its principle. Filter coefficient is set to [ c ] 0 ，c 1 ，c 2 ，c 3 ,c 4 ,c 5 ,c 6 ,c 7 ]The filtering operation is essentially a convolution operation, i.e.:
specifically, if the filtering is the N-phase interpolation filtering, the sampling frequency is obtained through N parallel sub-filtering operations after the N-phase interpolation.
Referring to fig. 4, the principle of polyphase interpolation filtering is shown.
In one embodiment, let N =4, i.e. the input sequence x is interpolated by a factor of 4, assuming the original input sequence is [ x ] 0 ,x 1 ,x 2 ,x 3 ,……]The input sequence after 4 times zero value interpolation is [0, x ] 0 ，0，0,0,x 1 ,0,0,0，x 2 ，0，0，0，x 3 ，……]Then, there is an output filtering sequence that can be expressed as:
y 0 ＝c 0 *0+c 1 *0+c 2 *0+c 3 *x 0 ++c 4 *0+c 5 *0+c 6 *0+c 7 *x 1
＝c 3 *x 0 +c 7 *x 1
y 1 ＝c 0 *0+c 1 *0+c 2 *x 0 +c 3 *0++c 4 *0+c 5 *0+c 6 *x 1 +c 7 *0
＝c 2 *x 0 +c 3 *x 1
y 2 ＝c 0 *0+c 1 *x 0 +c 2 *0+c 3 *0++c 4 *0+c 5 *x 1 +c 6 *0+c 7 *0
＝c 1 *x 0 +c 5 *x 1
y 3 ＝c 0 *x 0 +c 1 *0+c 2 *0+c 3 *0++c 4 *x 1 +c 5 *0+c 6 *0+c 7 *0
＝c 0 *x 0 +c 4 *x 1
it can be seen that the output filter sequence subjected to zero-valued interpolation can be divided into 4 subsequences with different coefficient operations, and the filter coefficient of each subsequence is a part of the original filter coefficient extracted at intervals of N, that is, a sub-filtering operation. The whole filter can work at a sampling rate which is 4 times of the working clock frequency through 4 parallel sub-filtering operations.
Of course, the above is only one embodiment, and the specific type, term number and interpolation filtering mode of the polyphase interpolation filter can be set according to actual requirements.
1033. And moving the central frequency point of the signal to be processed to the intermediate signal frequency f' through the second-stage up-conversion based on the intermediate sampling frequency.
After N-phase interpolation filtering, the signal sampling rate is
At this sampling rate, a second stage of up-conversion is performed to shift the frequency from f "to f', which is the intermediate signal frequency. The step frequency of the second stage frequency shift is
The frequency of the stepping is large, so that the stepping frequency shift can be called as stepping frequency shift. In this step the sampling rate is
The ratio of the sampling rate to the stepping frequency is R =2 × N, if N =2, R =4, the sine and cosine angle value of the up-conversion complex multiplication is exactly four phase points (0 °,90 °,180 °,270 °) in a unit circle, and the frequency shifting operation does not need a multiplier and only needs I and Q replacement. The complex multiplication taking four phase points in the unit circle is sequentially:
if N =4 then R =8, taking 8 phase points (0 °,45 °,90 °,135 °,180 °,225 °,270 °,315 °) within the unit circle, the frequency shifting operation requires only a real multiplication operation and no complex multiplication operation. The complex multiplication taking eight phase points in the unit circle is sequentially:
therefore, when N =2 or N =4, the up-conversion complex multiplication operation can be simplified, the logic resource of the FPGA/ASIC chip can be saved, and the occupation of the system computing resource is effectively reduced.
104. And combining the multi-channel signals to be processed after the two-stage up-conversion is completed to obtain combined signals.
Referring to fig. 5, a diagram illustrates a multi-phase combining principle provided by an embodiment of the present application.
After the signals are subjected to the second-stage frequency spectrum moving operation, the multi-channel signals can be combined, and the multi-phase combiner adds the signals of the corresponding phases of the multiple channels to obtain the combined multi-phase signals.
Fig. 5 illustrates a structure of a 4-phase combining. As shown in fig. 5, in the up-conversion system with n channels, each channel has 4 phases, and the signals of the channels and the phases are summed to obtain a unique 4-phase signal to be processed.
105. Performing multi-phase interpolation filtering on the combined signal to change the intermediate sampling frequency to a target sampling frequency, wherein the target sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac 。
The multi-channel signals after the multi-phase combination are combined into a multi-phase signal of a path combination, and the sampling rate is
The frequency spectrum range of the combined signal is [ f ] with 0Hz as the center min -f mid ,f max -f mid ]In place, the sampling rate can still be raised to f using a 2-fold interpolation filter by low-pass filtering dac . With the increase of the sampling rate of the output signal, the multiphase structure of the second-stage multiphase interpolation filtering is 2 × n phases.
106. And shifting the central frequency point of the signal to be processed to the target signal frequency through the third-level up-conversion based on the target sampling frequency to obtain the target signal.
At a sampling rate of f dac Then, carrying out third-stage up-conversion operation, uniformly carrying out overall frequency shift operation on the combined signals, and fixedly moving the combined signals upwards mid And finally, the center frequency point of the corresponding channel is moved to f, namely the position of the target frequency point, through the third frequency moving operation.
107. And outputting the target signal through a digital-to-analog converter.
In one embodiment, outputting the target signal through a digital-to-analog converter comprises: and converting the multiphase parallel data into single-phase serial data through a high-speed parallel-serial conversion interface and sending the single-phase serial data to a radio frequency digital-to-analog converter.
Through the conversion, multiphase parallel data can be converted into single-phase serial data, so that multichannel multiphase data can be converted into signals which can be converted and transmitted through a video digital-to-analog converter again, the complexity of an up-conversion algorithm is reduced, and the occupation of resources is reduced.
In combination with the above steps 101-107, in the specific case, f dac ＝2304MHz，f min ＝0MHz，f max If =1000MHz, then there aref mid =500MHz, and satisfies f dac >2*f max . Working master clock with N =4 modules
Is provided with three channels with frequency points of f in sequence 1 ＝100MHz，f 2 ＝400MHz，f 3 ＝700MHz。
Carrying out first-step decomposition on three frequency points:
f′ 1 ＝f 1 -f mid ＝-400(MHz)
f′ 2 ＝f 2 -f mid ＝-100(MHz)
f′ 3 ＝f 3 -f mid ＝200(MHz)
and then carrying out second-step decomposition:
the Farrow resampling filter up-samples the signal sampling rate to 288MHz, then carries on the first up-conversion, the frequency conversion position of three channels is f ″ 1 ＝32(MHz)，f″ 2 ＝44(MHz)，f″ 3 ＝56(MHz)。
The first stage polyphase interpolation filters up-samples the signal sample rate to
That is, the first-stage polyphase interpolation filtering adopts N =4, and the second-stage polyphase up-conversion is carried out to eight phase points in a unit circleComplex multiplication with increasing phase M per sample 1 ＝-3，M 2 ＝-1，M 3 ＝1。
Through the second-stage multiphase up-conversion, the frequency point positions of the three channels are moved to f' 1 ＝-400MHz，f′ 2 ＝-100MHz，f′ 3 =200MHz. The frequency spectrum positions of the three channels are not overlapped after being combined, and are all within the range of [ -500MHz,500MHz]In range, so as to design the pass band f of the second stage polyphase interpolation filter pass =500MHz, stop band
Sampling rate of f s ＝f dac =2304MHz. The number of parallel phases is 2 × n =8, i.e. an eight-phase structure.
The third-level up-conversion shifts the integral frequency spectrum of the signal after being combined and subjected to interpolation filtering upwards mid =500MHz, three channel frequency point positions after frequency shift are set as f 1 ＝-400MHz+500MHz＝100MHz，f 2 ＝-100MHz+500MHz＝400MHz，f 3 And =200MHz +500MHz =700MHz, which is the same as the preset target frequency point.
The sampling rate of the signal subjected to third upper side frequency is 2304MHz, and is consistent with the data rate of the input interface of the radio frequency digital-to-analog conversion DAC, and the main clock of the internal processing module is 288MHz, so that the signal needs to be output through the 8-to-1 high-speed parallel-serial conversion module.
It should be understood that the above cases are only examples, and specific parameters need to be determined according to practical applications, which are not further limited in the present application.
From the above, the resampling filtering and the first-stage frequency shifting operation which use the most resources only need to work at the position with a single phase and a low sampling rate, the second-stage frequency shifting is simplified by adopting a proper N value, the third-stage frequency shifting only needs to process one path of data after combination, and the whole up-conversion algorithm and structure can be greatly optimized through the comprehensive operation of the third-stage frequency shifting, so that the purpose of reducing the resource usage amount is achieved.
Referring to fig. 6, the present application further provides a structure of a multi-channel baseband-to-radio frequency up-conversion system.
As shown in fig. 6, a multi-channel baseband-to-radio frequency up-conversion system includes a signal input module 1, a resampling filtering module 2, a first up-conversion module 3, a multi-phase combiner module 4, a multi-phase interpolation filtering module 5, a second up-conversion module 6, and an output module 7:
the signal input module 1 is used for parallel processing of signals to be processed by adopting multi-channel branches.
Wherein, the frequency range of all frequency points supported by the system is set as f min ，f max ]The intermediate frequency point is f mid The interface data sampling rate of the DAC is f dac Internal master module processing clock frequency of f clk 。
Internal working clock f of general FPGA/ASIC chip clk F is difficult to reach dac The signals to be processed can be processed in parallel through the multi-channel branches. In an embodiment, this time may be set
When part of the modules need to work at the sampling rate f dac And 2 × N parallel branches are adopted for simultaneous processing, which is a multiphase representation structure of sampling rate conversion, wherein N can be determined according to design requirements, and N =2 or N =4 can be adopted from the viewpoints of processing convenience and optimization.
A resampling filter module 2, configured to perform up-sampling on the multi-channel baseband sampling rate to an initial sampling frequency through resampling filtering, where the initial sampling frequency is a clock frequency f of the main processing module clk 。
Symbol rate of baseband signal relative to working clock frequency f in chip clk Is generally small, the symbol rate may be fixed or variable according to different standards, and f clk The integer division does not always exist, and the sampling rate is converted into the sum of f by a mode of firstly resampling clk Sample rate with integer divisionThen up-sampling is carried out to f clk . Wherein the initial sampling frequency is also the clock frequency f clk 。
The first up-conversion module 3 is used for performing two-stage up-conversion and first-stage multiphase interpolation filtering on a signal to be processed so as to change the sampling frequency of the signal to be processed into an intermediate sampling frequency, and the central frequency point is moved to an intermediate signal frequency f'; wherein the intermediate sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac Half of the total.
Wherein, the intermediate sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac One half, i.e.
The first up-conversion module 3 may be configured to perform the following steps:
moving the central frequency point of the signal to be processed to a first signal frequency f' through a first-stage up-conversion based on the initial sampling frequency;
performing multi-phase interpolation filtering on the signal to be processed after the first-stage up-conversion is completed so as to change the initial sampling frequency into an intermediate sampling frequency;
and moving the central frequency point of the signal to be processed to the intermediate signal frequency f' through the second-stage up-conversion based on the intermediate sampling frequency.
And the multi-phase combiner module 4 is used for combining the multi-channel signals to be processed after the two-stage up-conversion is completed to obtain combined signals.
After the signals are subjected to the second-stage frequency spectrum moving operation, the multi-channel signals can be combined, and the multi-phase combiner adds the signals of the corresponding phases of the multiple channels to obtain the combined multi-phase signals.
A polyphase interpolation filtering module 5, configured to perform polyphase interpolation filtering on the combined signal to change the intermediate sampling frequency to a target sampling frequency, where the target sampling frequency is an interface data sampling rate f of a digital-to-analog converter dac 。
The multi-channel signals after the multi-phase combination are combinedIs a multi-phase signal combined all the way, and has a sampling rate of
The frequency spectrum range of the combined signal is [ f ] with 0Hz as the center min -f mid ,f max -f mid ]In place, the sampling rate can still be raised to f using a 2-fold interpolation filter by low-pass filtering dac . The multiphase structure of the second-stage multiphase interpolation filtering is 2 x N phases along with the increase of the sampling rate of the output signal.
And the second up-conversion module 6 is used for shifting the central frequency point of the signal to be processed to the target signal frequency through the third-level up-conversion based on the target sampling frequency to obtain the target signal.
At a sampling rate of f dac Then, carrying out third-stage up-conversion operation, uniformly carrying out overall frequency shifting operation on the combined signals, and fixedly moving the combined signals upwards mid And finally, the center frequency point of the corresponding channel is moved to f, namely the position of the target frequency point, through the third frequency moving operation.
And the output module 7 is used for outputting the target signal through a digital-to-analog converter.
In one embodiment, outputting the target signal through a digital-to-analog converter comprises: and converting the multiphase parallel data into single-phase serial data through a high-speed parallel-serial conversion interface and sending the single-phase serial data to a radio frequency digital-to-analog converter.
Through the conversion, multiphase parallel data can be converted into unidirectional serial data, so that multichannel multiphase data can be converted into signals which can be converted and transmitted through a video digital-to-analog converter again, the complexity of an up-conversion algorithm is reduced, and the occupation of resources is reduced.
It can be understood that, the up-conversion system reduces the consumption of FPGA/ASIC hardware resources under the condition of realizing the integral function of the up-conversion system by optimizing the algorithm structure of the up-conversion, thereby effectively reducing the requirement of the system on the hardware resources.
Referring to fig. 7, a structure of an electronic device provided in an embodiment of the present application is shown.
The electronic device may be a video signal processing device, and may be a device for shifting a baseband signal of a lower frequency band to a digital signal of a higher frequency band. Such as signal transmission processing means for digital television signals. It is to be understood that the present application is not limited to the particular type of electronic device.
As shown in fig. 7, the electronic device 2 includes a processor 21 and a memory 22, and the processor 21 is electrically connected to the memory 22;
the memory 22 stores a computer program, and the processor 21 calls the computer program stored in the memory 22 to execute the following steps:
performing parallel processing on signals to be processed by adopting multi-channel branches; the method comprises the steps that the multi-channel baseband sampling rate is up-sampled to an initial sampling frequency through resampling filtering, wherein the initial sampling frequency is the clock frequency fclk of a main processing module; carrying out two-stage up-conversion and first-stage multi-phase interpolation filtering on a signal to be processed so as to change the sampling frequency of the signal to be processed into an intermediate sampling frequency and move a central frequency point to an intermediate signal frequency f ^ a'; wherein the intermediate sampling frequency is half of an interface data sampling rate fdac of the digital-to-analog converter; combining the multi-channel signals to be processed after two-stage up-conversion to obtain combined signals; performing multi-phase interpolation filtering on the combined signal to change the intermediate sampling frequency into a target sampling frequency, wherein the target sampling frequency is an interface data sampling rate fdac of a digital-to-analog converter; shifting the central frequency point of the signal to be processed to the target signal frequency through third-level up-conversion based on the target sampling frequency to obtain a target signal; and outputting the target signal through a digital-to-analog converter.
It is understood that the type of the components of the processor 21 and the memory 22 may be any type according to the requirement, for example, an operation processing unit such as an FPGA or an ASIC is used as the processor 21, and the present application is not limited thereto.
In an embodiment, the processor 21 is further configured to:
moving the central frequency point of the signal to be processed to a first signal frequency f' through a first-stage up-conversion based on the initial sampling frequency; performing polyphase interpolation filtering on the signal to be processed after the first-stage up-conversion is completed so as to change the initial sampling frequency into an intermediate sampling frequency; and moving the central frequency point of the signal to be processed to the intermediate signal frequency f' through the second-stage up-conversion based on the intermediate sampling frequency.
For implementation of the above steps, reference may be made to multiple embodiments of the multi-channel baseband-to-radio frequency up-conversion method shown in fig. 1 to 5, which are not described herein again.
From the above, according to the electronic device, the signals to be processed are subjected to multi-channel parallel processing, and the traditional complex up-conversion algorithm is structurally optimized through the algorithm and the structural design of multi-level up-conversion, multi-phase interpolation filtering and multi-phase combining, so that the resource usage amount of a system occupied by the up-conversion algorithm is reduced, the running speed of the electronic device is increased, the hardware requirement is reduced, and the cost of the electronic device is further reduced.
In this embodiment, the electronic device and the multichannel baseband-to-radio frequency up-conversion system belong to the same concept as the multichannel baseband-to-radio frequency up-conversion method in the above embodiment, and any method step provided in the multichannel baseband-to-radio frequency up-conversion method embodiment may be run on the electronic device and the multichannel baseband-to-radio frequency up-conversion system.
The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present application within the knowledge of those skilled in the art.
Claims (11)
1. A multi-channel baseband-to-radio frequency up-conversion method is applied to an up-conversion system and is characterized by comprising the following steps:
adopting multi-channel branches to perform parallel processing on signals to be processed;
up-sampling the multi-channel baseband sampling rate to an initial sampling frequency through resampling filtering, wherein the initial sampling frequency is the clock frequency f of the main processing module clk ；
Carrying out two-stage up-conversion and first-stage multiphase interpolation filtering on a signal to be processed so as to change the sampling frequency of the signal to be processed into an intermediate sampling frequency, and moving a central frequency point to an intermediate signal frequency f'; wherein the intermediate sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac Half of (1);
combining the multi-channel signals to be processed after two-stage up-conversion to obtain combined signals;
performing multi-phase interpolation filtering on the combined signal to change the intermediate sampling frequency into a target sampling frequency, wherein the target sampling frequency is an interface data sampling rate f of a digital-to-analog converter dac ；
Shifting the central frequency point of the signal to be processed to the target signal frequency through third-level up-conversion based on the target sampling frequency to obtain a target signal;
and outputting the target signal through a digital-to-analog converter.
2. The method of claim 1, wherein the performing two-stage up-conversion and the first-stage polyphase interpolation filtering on the signal to be processed to change the sampling frequency of the signal to be processed to an intermediate sampling frequency and shift the center frequency point to the intermediate signal frequency comprises:
moving the central frequency point of the signal to be processed to a first signal frequency f' through a first-stage up-conversion based on the initial sampling frequency;
performing polyphase interpolation filtering on the signal to be processed after the first-stage up-conversion is completed so as to change the initial sampling frequency into an intermediate sampling frequency;
and moving the central frequency point of the signal to be processed to the intermediate signal frequency f' through the second-stage up-conversion based on the intermediate sampling frequency.
3. The method of claim 2, wherein the first signal frequency f "is in a range of values
4. The multi-channel baseband-to-radio frequency up-conversion method of claim 2,
the step frequency of the second-stage up-conversion is the clock frequency f of the main processing module clk And one half of
The ratio of the intermediate sampling frequency to the stepping frequency is R =2 × n, n being the number of phases of the interpolation filtering.
5. The multi-channel baseband-to-radio frequency up-conversion method according to claim 1 or 2, wherein said polyphase interpolation filtering employs a FIR interpolation filter.
6. The multi-channel baseband to radio frequency up-conversion method of claim 1 or 2,
the step of polyphase interpolation filtering comprises:
if the filtering is N-phase interpolation filtering, after N-phase interpolation, the sampling frequency is obtained through N parallel sub-filtering operations.
7. The method of multi-channel baseband to radio frequency up-conversion of claim 1, wherein:
the multiple channels are 2 × N channels, and the clock frequency of the main processing module
And N is the number of interpolation-filtered phases.
8. The multi-channel baseband-to-radio frequency up-conversion method according to claim 1, wherein said outputting the target signal through a digital-to-analog converter comprises:
and converting the multiphase parallel data into single-phase serial data through a high-speed parallel-serial conversion interface and sending the single-phase serial data to a radio frequency digital-to-analog converter.
9. The method of multi-channel baseband-to-radio frequency up-conversion according to claim 1, wherein the up-sampling the multi-channel baseband sampling rate to an initial sampling frequency by resampling filtering comprises:
and (5) up-sampling the signal to be processed by adopting a Farrow resampling filter.
10. A multi-channel baseband-to-radio frequency up-conversion system, comprising:
the signal input module is used for carrying out parallel processing on the signals to be processed by adopting multi-channel branches;
a resampling filter module for up-sampling the multi-channel baseband sampling rate to an initial sampling frequency, wherein the initial sampling frequency is the clock frequency f of the main processing module clk ；
The first up-conversion module is used for performing two-stage up-conversion and first-stage multiphase interpolation filtering on a signal to be processed so as to change the sampling frequency of the signal to be processed into an intermediate sampling frequency, and the central frequency point is moved to an intermediate signal frequency f'; wherein the intermediate sampling frequency is the interface data sampling rate f of the digital-to-analog converter dac Half of (1);
the multi-phase combiner module is used for combining the multi-channel signals to be processed after the two-stage up-conversion is completed to obtain combined signals;
a multiphase interpolation filtering module for performing multiphase interpolation filtering on the combined signal to change the intermediate sampling frequency into a target sampling frequency, wherein the target sampling frequency is an interface data sampling rate f of a digital-to-analog converter dac ；
The second up-conversion module is used for moving the central frequency point of the signal to be processed to the target signal frequency through third-level up-conversion based on the target sampling frequency to obtain a target signal;
and the output module is used for outputting the target signal through the digital-to-analog converter.
11. An electronic device, characterized in that the electronic device comprises:
a processor; and
memory in which a computer program is stored, the processor being adapted to perform a multi-channel baseband to radio frequency up-conversion method according to any of claims 1-9 by invoking the computer program stored in the memory.
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