CN112039495B - Floating-point number FIR digital filter and design method thereof - Google Patents

Floating-point number FIR digital filter and design method thereof Download PDF

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CN112039495B
CN112039495B CN202010899954.6A CN202010899954A CN112039495B CN 112039495 B CN112039495 B CN 112039495B CN 202010899954 A CN202010899954 A CN 202010899954A CN 112039495 B CN112039495 B CN 112039495B
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马春光
陈元
鄢然
周逸
吕洪光
罗勇
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University of Electronic Science and Technology of China
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Abstract

The invention discloses a floating-point number FIR digital filter and a design method thereof, belonging to the technical field of digital signal processing in a high-voltage pulse power supply system. The filter comprises a data storage module to be filtered, a filter coefficient storage module, a floating point number conversion module, a first-in first-out memory module, a memory control module, a first random access memory, a second random access memory and a floating point number multiplication and accumulation module. The FIR digital filter based on floating point number operation can be realized, the precision of the filtering result can reach the precision of the theoretical value calculated by MATLAB, the quantization error introduced by the FIR digital filter is greatly reduced compared with the traditional fixed point number filter, and meanwhile, the FIR digital filter can perform low-pass filtering on the signal which is collected in a high-voltage pulse power supply system and receives high-frequency interference, thereby laying a foundation for subsequent monitoring and analysis of the signal.

Description

Floating-point number FIR digital filter and design method thereof
Technical Field
The invention belongs to the technical field of digital signal processing in a high-voltage pulse power supply system, and particularly relates to a floating-point FIR digital filter and a design method thereof.
Background
For a high-voltage pulse power supply system, because the load of a high-power switching tube in a switching loop is the primary coil of a high-frequency transformer, which is an inductive load, when the high-power switching tube is switched on or off, peak noise appears at both primary ends of the high-frequency transformer. The high current change rate and the high voltage change rate generated in the working process form interference sources by surge current and peak voltage, and because analog quantity signals such as voltage, current and the like in a power supply system are easily subjected to high-frequency interference, signal waveforms are doped with a large number of high-frequency clutter, the acquired analog quantity data frequently bounce and even wrong data are acquired, the monitoring and analysis of the signals are difficult, so that the digital filtering design is carried out in the acquisition system, and the low-pass filtering of the acquired signals is very necessary.
The FPGA (field programmable gate array) has the advantages of high integration level, flexible compiling, high efficiency of parallel operation processing and the like, can simplify the circuit complexity from the design level of a hardware circuit, removes redundant logic control circuit elements in the circuit, can reduce the development difficulty of circuit design and shorten the development period, has great advantages on designing a digital filter by a digital signal processing IP core (intellectual property core) with strong functions and a memory IP core in the FPGA, can reconfigure parameters without changing the hardware environment by using the FPGA as a hardware platform for realizing the digital filter, and has the advantages of low price, flexibility, convenience and the like.
FIR (finite impulse response) digital filters have the advantages of stability and good amplitude-frequency characteristics, and can be designed to have strict linear phase so as to avoid phase distortion of the processed signal, and therefore, are widely used in digital signal processing systems. However, the conventional FIR filter implements data processing in the FPGA by using fixed points, for example, a FIR digital filter designed based on the FPGA designed by guo xiaoyu of the university of wuhan in the master thesis thereof [ guo xiaoyu, implementation of the FPGA-based FIR digital filter, wuhan university, 2004], is a filtering calculation using fixed points, because the precision range that the fixed points can represent is very limited, if digital filtering is performed by using fixed points, especially in a filter of a multiply-accumulate (MAC) structure, quantization errors introduced therein are easily amplified continuously along with the process of multiply-accumulate, and finally, a deviation between an actual filtering result and a theory is large, and because the fixed points need to scale processing data each time, development difficulty and a development period are increased.
Disclosure of Invention
In view of the defects of the fixed-point FIR digital filter in the prior art, the invention provides a floating-point FIR digital filter and a design method thereof, so that the error between the filtering result and the theoretical result is extremely small.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a floating-point number FIR digital filter comprises a data storage module to be filtered, a filter coefficient storage module, a floating-point number conversion module, a first-in first-out memory module, a memory control module, a first random access memory, a second random access memory and a floating-point number multiply-accumulate module.
The data storage module to be filtered is a read-only memory module or an AD data acquisition module and is used for storing the data to be filtered and sending the data to be filtered to the floating-point number conversion module.
And the filter coefficient storage module is used for storing the filter coefficient and sending the filter coefficient to the floating point number conversion module.
The floating point number conversion module is used for converting the data to be filtered into the data to be filtered in a floating point number format and then sending the data to be filtered to the first-in first-out memory module; the filter coefficients are converted to floating point format filter coefficients and then sent to a second random access memory.
And the first-in first-out memory module is used for enabling the phase of the data to be filtered in the floating point format to be consistent with the phase of the filter coefficient in the floating point format and sending the data to be filtered in the floating point format to the first random access memory.
The memory control module is used for controlling the address reading and writing of the first random access memory and the second random access memory.
The first random access memory is used for storing the data to be filtered in the floating point format and then sending the data to be filtered in the floating point format to the floating point multiply-accumulate module; and the second random access memory is used for storing the floating point format filter coefficients and then sending the floating point format filter coefficients to the floating point multiply-accumulate module.
And the floating-point number multiply-accumulate module is used for carrying out multiply-accumulate operation on the floating-point number format data to be filtered and the floating-point number format filter coefficient and outputting the filtered data.
Furthermore, the floating-point number conversion module comprises an absolute value taking module, a decimal to binary conversion module, an exponent extraction module and a bit splicing module. And the absolute value taking module receives the integer part of the decimal data to be filtered, then sends the absolute value of the integer part to the exponent extracting module, and sends the sign bit to the bit splicing module. The decimal to binary conversion module receives decimal data to be filtered, converts the decimal data to binary data and sends the binary data to the index extraction module and the bit splicing module; and the index extraction module is used for carrying out index extraction on the received absolute value and the binary decimal and then sending the extracted index to the bit splicing module. The bit splicing module splices the sign bit, the exponent bit and the decimal bit to obtain a floating point number which conforms to the IEEE-754 standard.
Furthermore, the floating-point number multiply-accumulate module comprises a floating-point number multiplier IP core, a floating-point number adder IP core, a register and a counter. The floating-point number multiplier IP core receives the data to be filtered in the floating-point number format and the filter coefficient in the floating-point number format, performs multiplication operation, inputs a product result into the floating-point number adder IP core, accumulates the product result by the floating-point number adder IP core, stores the accumulated result of each time into a register for participating in next accumulation calculation, and outputs a final accumulated result if the accumulated number reaches a set number.
The design method of the floating-point FIR digital filter comprises the following steps:
s1, collecting a section of data to be filtered containing a complete period, wherein the data is decimal; and carrying out spectrum analysis on the section of data to be filtered so as to obtain a filter coefficient represented by a decimal system.
And S2, storing the filter coefficient and the data to be filtered into a data to be filtered storage module.
And S3, the data to be filtered storage module sends the stored filter coefficient and the data to be filtered to the floating point number conversion module, and the floating point number conversion module converts the decimal filter coefficient and the data to be filtered into a 32-bit floating point number format which accords with the IEEE-754 standard.
And S4, the filter coefficients in the floating point format and the data to be filtered are matched with the input time sequence of the floating point multiply-accumulate module through the first-in first-out memory module, the memory control module, the first random access memory and the second random access memory.
And S5, inputting the two paths of data output from the output ports of the first random access memory and the second random access memory into a floating point number multiply-accumulate module, and performing floating point number multiply-accumulate operation to obtain the filtered discrete data.
Further, in step S1, the band filtered data is subjected to spectrum analysis using MATLAB.
The floating-point FIR digital filter and the design method thereof can realize the FIR digital filter based on floating-point arithmetic on FPGA, so that the precision of the filtering result can reach the theoretical value precision of MATLAB calculation, the quantization error introduced by the filter is greatly reduced compared with the traditional fixed-point filter, and meanwhile, the high-frequency interference signal collected in a high-voltage pulse power supply system can be subjected to low-pass filtering, thereby laying a foundation for the subsequent monitoring and analysis of the signal.
Drawings
FIG. 1 is a flow chart of a design method in an embodiment of the invention.
Fig. 2 is a block diagram of an FIR filter module in an FPGA in the embodiment of the present invention.
FIG. 3 is a flow chart of a decimal to binary decimal algorithm in an embodiment of the present invention.
FIG. 4 is a block diagram of a floating-point number conversion module in the FPGA according to an embodiment of the present invention.
FIG. 5 is a flow chart of RAM address control according to an embodiment of the present invention.
FIGS. 6(a) and 6(b) are timing diagrams of data read from the internal RAM of the FIR filter according to the embodiment of the present invention; fig. 6(a) shows a filter coefficient data read timing, and fig. 6(b) shows a data read timing to be filtered.
FIG. 7 is a block diagram of floating point number multiply accumulator structure in an FPGA embodiment of the present invention.
FIG. 8 is a floating point number multiply accumulator dataflow diagram in an embodiment of the present invention.
FIG. 9 is a timing diagram illustrating operation of a floating-point multiply-accumulator according to an embodiment of the present invention.
FIGS. 10(a), 10(b) and 10(c) are waveform diagrams of the results of FPGA and MATLAB filtering according to the embodiment of the present invention; in fig. 10(a), the left side shows the FPGA filtering result, the right side shows the MATLAB filtering result, fig. 10(b) shows a comparison graph of the FPGA and MATLAB filtering results, and fig. 10(c) shows a comparison graph of specific data of the FPGA and MATLAB filtering.
FIG. 11 is a graph comparing the filtering result with the original waveform according to the embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments.
The embodiment of the invention provides a floating-point FIR digital filter and a design method thereof, wherein the flow of the design method is shown in figure 1. The hardware platform is FPGA, the design method is MATLAB and FPGA combined simulation design, wherein the MATLAB is responsible for complex signal analysis, filter parameter design, coefficient calculation and other work, and the FPGA is responsible for building a filter structure on a hardware level, so that digital filtering on hardware is realized. The filter is designed into a direct structure of a window function method, and the Kaiser window is selected as the window function, so that the Kaiser window has steeper roll-off and larger stop-band attenuation compared with other windows; the output expression of this filter can be expressed as:
Figure BDA0002659467620000041
wherein m is the filter order, h (i) is the ith filter coefficient, i is 0,1,2, …, m-1, x (n-i) is the nth to-i data to be filtered, and y (n) is the nth filtered data; the system function of the filter of the embodiment is as follows:
Figure BDA0002659467620000042
wherein h is1(i) As a function of the ideal low-pass filter system, w (i) is a window function, Ω1Is the angular frequency, I0The first Bessel function is corrected for zero order, beta is a parameter of the Bessel function, and the value of beta determines the shape of the Kaiser window and can be calculated according to the stop band requirement of the filter.
The floating point number FIR filter structure designed in FPGA is as shown in figure 2, in the structure, firstly, two paths of data imported from MATLAB, namely data x to be filtered and filter coefficient h are Read by two pieces of FPGA built-in block ROM (Read-Only Memory), the Read data are decimal data and need to be converted into 32 bit floating point numbers conforming to IEEE-754 standard through a floating point number conversion module in FPGA, and the expression about the IEEE-754 standard 32 bit floating point numbers is as follows:
X＝(-1)S×1.c×2e-bias(formula 3)
Where S represents the value of the sign bit, c represents the unsigned mantissa, E represents the value of the exponent field, bias represents the offset, if the binary number of the exponent is represented by E, then the offset is:
bias＝2E-1-1 (formula 4)
For a 32-bit single precision floating point number, the exponent binary bit is 8 bits, so the offset bias has a value of 127.
The process of converting decimal number into floating point number is to convert decimal number into binary number, and the process is divided into two parts: the decimal part conversion process algorithm provided by the embodiment is shown in the attached figure 3.
Wherein D _ part is a decimal fractional part value, D _ bit is a decimal digit reserved for the decimal, D _ binary is a converted binary decimal, and D _ binary _ bit sets digits for the converted binary decimal. It should be noted that in order to preserve as high precision as possible, the number of binary digits set may exceed 23 bits, and if it exceeds 23 bits, redundant bits are automatically discarded when they are assigned to the unsigned mantissa c in a floating point number. In fact, the number of bits actually assigned to c is typically less than 23 bits, because the first few bits in c will be assigned the value of a binary integer if the original decimal number has an integer part other than 0.
Firstly, taking an absolute value of an integer part of a binary decimal and extracting a sign bit, wherein the decimal integers in the FPGA are all expressed in a binary complement mode, so that the operation of taking the absolute value of an N-bit binary number is shown as the following expression:
Figure BDA0002659467620000051
wherein X2CThat is, the complement of binary, the MSB (most significant bit) of the complement is a sign bit, the value of the sign bit is assigned to the sign bit S of the floating-point number, and when the value of the sign bit is 1, the original binary number is a negative number, and when the value of the sign bit is 0, the original binary number is a positive number.
Then, 1.c standardization is carried out on the binary decimal with the absolute value, namely, the original decimal point is shifted to the back of the MSB, and the shifted decimal point is added or subtracted with the offset bias according to the number of the shifted decimal point, namely: if the left shift is d, the exponent is-d, the left shift number is subtracted by the required offset, if the right shift is d, the exponent is + d, and the required offset is added by the right shift number; after 1.c normalization, the value is first assigned to the floating point number exponent field e, then the 1 before the decimal point in 1.c is truncated, and the c bits after the decimal point are assigned to the floating point number mantissa c, which for a 32-bit single precision floating point has 23 bits of unsigned mantissa.
And finally, sequentially splicing the obtained 1-bit sign bit S, 8-bit exponent e and 23-bit unsigned fractional part c from high to low in a bit splicing module to obtain a 32-bit floating point number X, wherein the floating point number conversion module designed according to the idea is shown in the attached figure 4.
Therefore, the floating-point number conversion of the method needs to input the integer part and the decimal part of the original decimal number, wherein the integer part keeps the sign, and the decimal part only keeps the number with the first digit not being 0 after the decimal point to the last digit.
After the read decimal data is converted into 32-bit single-precision floating point data by the floating point number conversion module, compared with the reading and writing of the filter coefficient H, one more FIFO (First-In-First-Out-Memory) module is needed for a data path of the signal data X to be filtered. The module has the function that when the filter system actually works in the data acquisition system, because the conversion time of the selected data acquisition AD chip is often inconsistent with the working time of the filter, the FIFO module is required to be used for clock domain crossing operation, so that X can be consistent with the reading time sequence of H, when MATLAB joint simulation operation is used, the FIFO module can be selected to be ignored, and if the frequency is called, the reading and writing clock frequency of the FIFO is required to be kept consistent.
No matter whether the FIFO is called or not, the last two paths of data are input into two RAM (Random-access Memory), and the timing sequence of the two paths of data is adjusted by controlling the read-write enable and the address of the RAM through the Memory control module, so that the timing sequence can meet the working timing sequence of a subsequent floating point number times accumulator module. Meanwhile, in order to save the internal storage space of the RAM, the range of the address addr _ h _ RAM of the filter coefficient h _ RAM and the address addr _ x _ RAM of the data x _ RAM to be filtered may be controlled, and a specific control flowchart is shown in fig. 5.
It can be seen from the figure that the range of variation for the address addr _ h _ RAM of the RAM holding the filter coefficient h is from 1 to m, m representing the order of the filter; for the RAM address addr _ x _ RAM storing the data x to be filtered, the variation range is more complicated, and when the address addr _ h _ RAM is m, the address addr _ x _ RAM changes as follows: if its value is 0, it becomes 1; if its value is 1, it becomes m, and if its value is a number other than 0 and 1, it remains unchanged; if the address of addr _ h _ ram is not m, addr _ x _ ram is automatically decremented until its value is reduced to 1. Since the statement for controlling the two addresses in the FPGA is executed according to the rising edge of the global clock clk, that is, the statement shown in the flowchart is executed once every rising edge of clk, so that the cyclic change of the two addresses can be realized, and the sequential reading of the data stored in the RAM can be realized, and the timing charts of the two paths of data reading in the filter module are shown in fig. 6(a) and 6 (b). It can be seen from the timing diagram that the working timing sequences of the two RAMs x _ RAM and h _ RAM for controlling data reading and writing are both when the en _ RAM is enabled to be high, the we _ RAM signal is high, the data at the current input port is written to the specified address, and when the we _ RAM signal is low, the data at the current address is read to the output port. The RAM in this embodiment is set to the write-first mode, that is, the data written this time is output at the output port while writing.
In addition, whenThe two times t1 and t2 can be seen in the sequence diagram, the former representing the data throughput period of the filter, i.e. how long filtered data can be output, and the latter representing the omission time. It should be noted that the filter designed with this structure has a throughput rate fTWith filter order m, global clock frequency fclkThe relationship of (a) is shown as follows:
Figure BDA0002659467620000071
therefore, the relational expression between t1 and t2 in the timing diagram is:
Figure BDA0002659467620000072
and outputting the two paths of data x and h from the RAM, and inputting the two paths of data x and h into a floating-point number multiply-accumulate module to perform multiply-accumulate operation so as to complete digital filtering, wherein the multiply-accumulate formula is shown as (formula 1). For the design of the multiply-accumulate module, a multiplier and an adder are needed to be combined for realization, a mature and reliable floating-point number operator IP core is integrated in an FPGA chip, and the IP core is called to conveniently perform operations such as addition, subtraction, multiplication, division, squaring and the like on two IEEE-754 single-precision or double-precision floating-point numbers, and hardware resources and device delay can be saved to the greatest extent, so that in the embodiment, a floating-point number adder IP core and a floating-point number multiplier IP core are directly called to perform multiply-accumulate operation, the structural block diagram is shown in figure 7, and the data flow diagram is shown in figure 8. In addition, in order to improve the operation efficiency of the multiply-accumulator, a first-stage flow register is arranged at the output port of the adder and used for registering the result after each accumulation so as to be called when the accumulation is calculated next time.
The operation timing diagram of the floating-point multiply accumulator is shown in fig. 9, in which the data of wrong indicates that the data calculated at this time is error data, the output result does not read the data from the pipeline register in this period, and accumulation [ q ] indicates the q-th multiply-accumulate result, and the expression is:
Figure BDA0002659467620000073
the data y output from the multiply-accumulate device is the signal data filtered by the FIR filter, and in order to visually represent the filtering effect of the filter, the filtered discrete data needs to be imported into MATLAB, the SPTool tool is used to restore the signal waveform, and the difference of the filtering results of the MATLAB is contrastingly observed. In this embodiment, the signal filtered by the floating-point FIR filter is compared with the signal subjected to the same filtering in MATLAB, and the result is shown in fig. 10(a) and 10(b), and it can be seen by comparing the two waveforms, that the filtering result of the FIR filter operated by the floating-point is basically consistent with the filtering result of the MATLAB with high precision, and that the partial difference comparison of the two waveform data can be seen in detail in fig. 10(c), and the data obtained by the FPGA filtering and the MATLAB filtering data are compared at 10-7Errors begin to appear right and left, and the quantization errors introduced by the FIR filter based on the floating point number are proved to be very small.
In order to visually compare the effect of the filtering result compared with the original waveform, the filtered data waveform and the original signal waveform are drawn on the same graph, as shown in fig. 11, which proves that most high-frequency clutter of the waveform after low-pass filtering is filtered. The floating-point FIR filter designed by the invention has good filtering effect, can introduce extremely small precision error, has almost the same difference with an approximate theoretical value calculated by MATLAB, effectively solves the problem that the traditional fixed-point FIR filter easily causes overlarge quantization error, and provides guarantee for further analysis of signal data acquired in a high-voltage pulse power supply system because the filtering result of the filter is more accurate.

Claims (4)

1. A floating-point FIR digital filter comprises a data storage module to be filtered, a filter coefficient storage module, a floating-point conversion module, a first-in first-out memory module, a memory control module, a first random access memory, a second random access memory and a floating-point multiply-accumulate module;
the data storage module to be filtered is a read-only memory module or an AD data acquisition module and is used for storing data to be filtered and sending the data to be filtered to the floating-point number conversion module;
the filter coefficient storage module is used for storing the filter coefficient and sending the filter coefficient to the floating point number conversion module;
the floating point number conversion module is used for converting the data to be filtered into the data to be filtered in a floating point number format and then sending the data to the first-in first-out memory module, and converting the filter coefficient into the filter coefficient in the floating point number format and then sending the filter coefficient to the second random access memory; specifically, the floating-point number conversion module comprises an absolute value taking module, a decimal to binary conversion module, an exponent extraction module and a bit splicing module; the absolute value taking module receives an integer part of the decimal data to be filtered, then sends the absolute value of the integer part to the exponent extracting module, and sends a sign bit to the bit splicing module; the decimal to binary conversion module receives decimal data to be filtered, converts the decimal data to binary data and sends the binary data to the index extraction module and the bit splicing module; the index extraction module is used for carrying out index extraction on the received absolute value and the binary decimal number and then sending the extracted exponent bits to the bit splicing module; the bit splicing module splices a sign bit, an exponent bit and a decimal bit to obtain a floating point number conforming to the IEEE-754 standard;
the FIFO memory module is used for enabling the phase of the data to be filtered in the floating point format to be consistent with the phase of the filter coefficient in the floating point format and sending the data to be filtered in the floating point format to the first random access memory;
the memory control module is used for controlling the address reading and writing of the first random access memory and the second random access memory;
the first random access memory is used for storing the data to be filtered in the floating point format and then sending the data to be filtered in the floating point format to the floating point multiply-accumulate module; the second random access memory is used for storing the floating point number format filter coefficients and then sending the floating point number format filter coefficients to the floating point number multiply-accumulate module;
the floating-point number multiply-accumulate module is used for carrying out multiply-accumulate operation on the floating-point number format data to be filtered and the floating-point number format filter coefficient and outputting filtered data; specifically, the floating-point number multiply-accumulate module comprises a floating-point number multiplier IP core, a floating-point number adder IP core, a register and a counter; the floating-point number multiplier IP core receives the data to be filtered in the floating-point number format and the filter coefficient in the floating-point number format, performs multiplication operation, inputs a product result into the floating-point number adder IP core, accumulates the product result by the floating-point number adder IP core, stores the accumulated result of each time into a register for participating in next accumulation calculation, and outputs a final accumulated result if the accumulated number reaches a set number.
2. A method of designing a floating point FIR digital filter as claimed in claim 1, comprising the steps of:
s1, collecting a section of data to be filtered containing a complete period, wherein the data is decimal; carrying out spectrum analysis on the section of data to be filtered so as to obtain a filter coefficient represented by a decimal system;
s2, storing the filter coefficient and the data to be filtered into a data to be filtered storage module;
s3, the data storage module to be filtered sends the stored filter coefficient and the data to be filtered to the floating point number conversion module, and the floating point number conversion module converts the decimal filter coefficient and the data to be filtered into a 32-bit floating point number format which accords with the IEEE-754 standard;
s4, enabling the filter coefficients in the floating point number format and the data to be filtered to be matched with the input time sequence of the floating point number multiplication accumulation module through the first-in first-out memory module, the memory control module, the first random access memory and the second random access memory;
and S5, inputting the two paths of data output from the output ports of the first random access memory and the second random access memory into a floating point number multiply-accumulate module, and performing floating point number multiply-accumulate operation to obtain the filtered discrete data.
3. The method of claim 2, wherein in step S1, the band filtered data is subjected to spectral analysis using MATLAB.
4. The method of claim 2, wherein the filter uses an FPGA as a hardware platform.
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