KR100335252B1 - Fast digital filter - Google Patents

Abstract

The present invention relates to a high-speed digital filter having a bit division structure, and more particularly, to a high-speed digital filter having a bit-division structure, comprising: a real data register (1) An imaginary data register (3) for storing imaginary input data; First and second multiplexers (5, 7) for selecting and outputting the real and imaginary numbers of the real data register (1) and the imaginary data register (3), respectively; A first coefficient register (13) for storing a real number filter coefficient; A second coefficient register (15) for storing imaginary filter coefficients; A third multiplexer (9) for selecting and outputting filter coefficients of the first coefficient register (13) corresponding to the real and imaginary numbers of the first and second multiplexers (5, 7); A fourth multiplexer 11 for selecting and outputting filter coefficients of the second coefficient register 15 corresponding to the real and imaginary numbers of the first and second multiplexers 5 and 7; First and second adder trees (17, 19) for respectively adding outputs of the third and fourth multiplexers (9, 11); First and second digit correction registers (R1-R4) for respectively correcting the digits of the outputs of the adder trees (17, 19) by shifting the outputs of the first and second adder trees (17, 19); And a high-speed accumulator 20 for calculating real output data and imaginary output data by calculating the outputs of the first and second digit correction registers R1-R4.

That is, according to the present invention, it is possible to design the system using fewer resources by using the data characteristics of the two's complement type rather than the hardware using the conventional filter structure.

Description

[0001] FAST DIGITAL FILTER [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter, and more particularly, to a high-speed digital filter having a bit separation structure in which a delay time of an operation circuit is eliminated.

The use of digital filters is essential in many areas, including imaging radar signal processing. Therefore, in order to realize real-time data processing, it is necessary to speed up the digital filter.

A typical digital filter consists of a section that multiplies filter coefficients and input data, and a section that adds the multiplication results of each tap. In this case, hardware implementation of the multiplication part first consumes a lot of resources, and the computation time is very long, which causes a bottleneck and slows down the entire processing speed.

Second, the accumulator part accumulates the operation results of each bit and processes the final result. The size of the data to be calculated is much larger than the number of input bits. Therefore, when the general accumulator structure is used, the data processing time increases in the accumulation process. Therefore, the bottleneck in this part increases the clock period of the system, thereby increasing the overall data processing time.

Third, when the number of taps of a digital filter is large, it consumes a lot of resources when implemented in hardware. For typical digital filters, use signed numbers as data and filter coefficients. Therefore, the digital filter requires the coefficient of the filter to be complemented with the coefficient according to the sign of each data when performing the operation. So you have to put a register to save the repair, or implement a logic circuit to make the repair. In this case, you should consume a lot of resources and reduce the number of taps in the filter due to the limited amount of resources.

Fourth, when processing data of a complex number, the filter largely requires four operation results as shown in Table 1 below. Therefore, there is a problem in that it requires four operation parts when implemented in hardware.

Print Required calculation result Real output A = (real part data) x (real part coefficient) A - B B = (imaginary part data) x (imaginary part coefficient) Imaginary output C = (real part data) x (imaginary part coefficient) C + D D = (imaginary part data) x (real part coefficient)

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed digital filter of a bit division structure in which a delay time of an operation circuit is eliminated.

According to an aspect of the present invention, there is provided a high-speed digital filter having a bit-

A real data register for storing real input data;

An imaginary data register for storing imaginary input data;

First and second multiplexers for selecting and outputting the real and imaginary numbers of the real data register and the imaginary data register, respectively;

A first coefficient register for storing a real number filter coefficient;

A second coefficient register for storing imaginary filter coefficients;

A third multiplexer for selecting and outputting a filter coefficient of a first coefficient register corresponding to a real number and an imaginary number of the first and second multiplexers;

A fourth multiplexer for selecting and outputting a filter coefficient of a second coefficient register corresponding to a real number and an imaginary number of the first and second multiplexers; First and second adder trees for respectively adding outputs of the third and fourth multiplexers; A first and a second digit correction register for respectively correcting the digits of the adder tree output by shifting outputs of the first and second adder trees; And a high-speed accumulator for calculating real output data and imaginary output data by calculating the outputs of the first and second digit correction registers.

As described below, in order to solve the first problem of the prior art, the present invention divides data into bits and performs operations on each bit. The part performing the operation is implemented using Carry Save Adder (CSA) to reduce the delay time. This eliminates the need to use a multiplier to solve bottlenecks.

Also, in order to solve the second problem of the prior art, the accumulator part is implemented using Carry Save Adder (CSA) and Carry Propagation Adder (CPA) in the present invention. By implementing this method, the data processing method of the accumulator part can be modified to shorten the clock period of the system, and the data processing speed can be shortened.

In order to compensate for the third drawback of the prior art, the present invention makes it unnecessary to use the filter coefficient repair using an algorithm using the property of 2's complement, thereby reducing the amount of resources required.

In order to solve the fourth problem of the prior art, in the present invention, by using a method of multiplexing real numbers and imaginary parts of input data, four operation results can be obtained by only two operation parts, thereby reducing resource consumption .

1 is a block diagram of a high-speed digital filter of a bit-

2 is a block diagram showing the structure of a general CPA adder,

3 is a block diagram showing the structure of a general CSA adder;

FIG. 4 is a block diagram illustrating a structure of a high-speed computer in a high-speed digital filter of a bit-

FIG. 5 is a block diagram illustrating a structure of a computing unit in a high-speed digital filter of a bit division structure according to the present invention;

FIG. 6 is a block diagram illustrating another embodiment of a high-speed computer in a high-speed digital filter of a bit division structure according to the present invention.

7 is a block diagram showing another embodiment of a computing unit in a high-speed digital filter of a bit-division structure according to the present invention;

Description of the Related Art

1: real number data register 3: imaginary data register

5, 7, 9 11: Multiplexer 13, 15: Coefficient register

17, 19: Adder tree R1-R4: Digit correction register

20: High-speed accumulator

First, the theoretical background of the configuration of the digital filter of the present invention will be described as follows.

A typical digital filter is designed to perform Equation (1) below.

In Equation (1), Y (n) denotes n-th output data, C (k) denotes a kth filter coefficient, and X (n-k) denotes n-kth input data. Since Equation 1 represents a complex number, the output data can be divided into real output data and imaginary output data as shown in Equations (2) and (3)

In equations (2) and (3), superscripts R and I represent real numbers and imaginary numbers, respectively.

In the above equation, real input data is a signed number of L bits. The signed number is used as the complement of 2. Equation (4) below represents the size of the signed number.

In the above equation Represents the l-th bit of the n-th real input data. therefore May only have a value of '1' or '0'.

In Equation (4), the data size of the complement of 2 has a negative sign in the most significant bit. Therefore, when the partial sum is accumulated, the partial sum obtained from the most significant bit should be subtracted and the partial sum of the remaining bits must be added.

In Equation (3) and The input data can be expressed by Equation (5) and Equation (6) as follows.

Now, by substituting the above equation into the equation (2), the following equation (7) is obtained.

Referring to Equation (7), it can be seen that it is possible to perform filtering by bit-splitting the input data. Is a bit Is to perform a multiplication, but the result of the multiplication is Is '1' , And if it is '0' . In other words The calculation of Depending on the bit value of or .

The last equation of Equation (7) is based on the data bit value for all the tabs or , The result of bitwise operation can be obtained. Depending on the number of digits of the bit, , It is possible to obtain the result of the bit-by-bit-corrected operation of the data. The filtered result can be obtained by adding the result of the bit-by-bit corrected bits obtained from the least significant bit to the most significant bit.

Equation 3 is summarized in the same manner as Equation 8 below.

FIG. 1 is a block diagram showing the structure of a high-speed digital filter according to the present invention using Equation (8). The input data of 'L' bit and the filter coefficient of 'B' This is a hypothetical picture.

As shown in the figure, input data 0 to P-1 of L bits (0 to L-1) are divided into a real number and an imaginary number and input to the real data register 1 and the imaginary data register 3, respectively. The data stored in each of the registers 1 and 3 is configured to be able to cycle from the least significant bit (0) to the most significant bit (L-1), as shown.

New real input data ( ) And imaginary input data ( ) Is input, an operation for obtaining a bit-wise partial sum with respect to the least significant bit is performed first. That is, ), ( Are sequentially provided to the multiplexers 3 and 5 starting from the least significant bit.

To obtain the real output data shown in Equation (7), the real input data ( ) Bits ) Is multiplied by the real coefficient, and the imaginary input data ( ) Bits ) Must be multiplied by the imaginary coefficient. For this purpose, when the real number output data is obtained, the multiplexer 3 outputs the real number input data ( ) Bits ) Is stored in the real coefficient register 13 ( To the multiplexer 9 so that the imaginary input data ( ) Bits ) Is an imaginary coefficient in the imaginary coefficient register 15 ( To the multiplexer 11 so as to be multiplied.

Conversely, to obtain the imaginary output data of Equation (8), the real input data ( ) Bits ) Must be multiplied by the imaginary coefficient, and the imaginary input data ( ) Bits ) Must be multiplied by the real coefficient. To this end, the multiplexer 7 receives the real input data ( ) Bits ) Is stored in the imaginary coefficient register 15 as an imaginary coefficient ( To the multiplexer 11 so that the imaginary input data ( ) Bits ) Is a real number coefficient in the real number count register 13 To the multiplexer 9 to be multiplied.

The multiplexer 9 for the real part counts the bits of the real number input data ( ) Is '1', the corresponding filter value And if it is '0' . The imaginary number multiplexer 11 also outputs the bits of the imaginary input data ( ) In the same way or As shown in FIG.

This process is performed concurrently on all taps when implemented in hardware.

The results obtained so far are the filter coefficients ( , ) And the least significant bit of the input data and to be.

The resultant values from the multiplexers 9 and 11 are provided to an adder tree 17 and 19 composed of CSA (carry saver adder). In the adder tree 17 of the real number counting part, the result values of all tabs ( ). ≪ / RTI > Therefore, the result obtained from the adder tree (17) . However, the CSA divides the carry part and the sum part and outputs them. That is, adding the carry portion and the sum portion of the result of the adder tree 17 .

In the imaginary-number portion adder tree 19, As a result.

The reason why the adder trees 17 and 19 are implemented by the CSA is as follows.

A general carry propagation adder (CPA) is an adder that receives two inputs x (n), y (n) and outputs an output s (n), as shown in FIG. This adder adds the adder (Adder) (A1-An) ) To the carry input terminal of the next adder ( ). Therefore, the computation time is delayed due to the delay caused by the chain of the carry.

The general CSA of FIG. 3 is an adder which receives three outputs (x (n)), (y (n)) and (a (n)) and outputs two outputs c (n) A11-A1n) carries the output directly, unlike the CPA, it does not form a carry chain, so there is no delay and it is possible to perform a fast addition process. Because CSA consumes more resources than CPA, but has fast computation time, we implemented adder tree using CSA.

The result thus obtained is used to correct the digits in the digit correction registers R1, R2, R3, and R4. The partial sum of the first input data bits is given by Equation 7 . That is, there is no change. However, if the partial sum of the second input data bits is digitally corrected . This shifts the fractional sum by one bit to the left in the digit correction register (R1-R4).

Through this process, Wow Can be obtained.

The process of obtaining the corrected partial sum of the i-th bit is the same as the process of obtaining the partial sum of the 0-th bit described above Wow Can be obtained.

This process is repeated in order from the 0th input data bit to the (L-1) th input data bit, and the carries obtained from the adder trees 17 and 19 must also perform the above-described procedure.

The sequence-corrected partial sums calculated in this order are all added through the high-speed accumulator 20 to obtain the final filter output.

The high-speed accumulator 20 Wow From the 0th to the (L-1) th and obtains the final result of Equation (7).

The high-speed accumulator 20 can be manufactured in two ways.

The structure of the first high-speed accumulator 20 is shown in FIG. The first high-speed accumulator 20 mainly includes a cumulative circuit 23, 25 for accumulating the fractional-corrected fractional part of the real-number coefficient and the fractional-corrected fractional part of the imaginary-integer part, And an accumulation circuit 27 for adding a partial sum.

The accumulation circuits 23 and 25 accumulating the partial sum of the real coefficient part and the imaginary coefficient part accumulate the digitally corrected partial sum using the arithmetic units of the two 231, 233, and 251 and 253, respectively .

As shown in FIG. 3, the CSA receives three input data x (n), y (n), and an (a) by using a full-adder A21- The carry (c (n)) and the sum Sum (s (n)) are added together to output three outputs The sum of the input data x (n), y (n), and an) is obtained. However, since the operator of the present invention must be able to perform addition and subtraction as described later, The adders 231, 233, 251 and 253 of FIG. 5, which are modified from the CSA, add control signals # Add / n (n) (N) is represented by a binary number, the last digit of the input value y (n) must be '0' That is, the input value y (n) must have one digit greater than the input values a (n) and (x (n)).

The arithmetic operators 231, 233, 251 and 253 of the present invention are arranged such that the input value a (n) and the inverted input value a (n), that is, the one's complement value of a And the multiplexer MUX1 supplies the input value a (n) when the control signal # Add / Sub is 0 and the input value a (n) when the control signal # Add / (a (n)).

The output value and input value x (n) of the multiplexer MUX1 are provided to the input terminals a and b of the adders A11 to A1n and the input value y -1) of the carry- _in terminal C _in . Here, the control signal (# Add / Sub) is provided to the carry input terminal (C _in ) of the adder (An). Therefore, the adder A0-an adds the input values x (n), y (n) and a (n) when the control signal # Add / Sub is 0, (N (n)) is subtracted from the sum of the input values (x (n)) and (y (n)). That is, when the value of the control signal (# Add / Sub) is '0', the operators 231, 233, 251 and 253 of the present invention , And if the value of the control signal (# Add / Sub) is '1', a (n) of the three input data is subtracted .

On the other hand, the sum s (n) of the second operator 233 is input to the first operator 231 of the accumulation circuit 23 of the present invention as the input value x (n) via the sum register 235 And the carry (c (n)) of the second calculator 233 is provided as an input value y (n) via the carry register 237. The first operator 231 is also provided with a digit A carry of the real number is provided as an input value a (n) from R1.

The sum s (n) of the first operator 231 is provided as the input value x (n) and the carry c (n) of the second operator 231 is supplied to the second operator 233 as input Is provided as a value y (n), and the sum of the digit correction register R2 is provided as an input value a (n).

Here, since the highest-order bit L-1 discrimination signal (a signal only when the highest-order bit is provided) is used as the above-described control signal # Add / Sub, Is 0, the accumulation circuit 23 , And if the highest-order bit (L-1) is '1', a (n) of the three input data is subtracted .

The following equation is a part for accumulating the partial sum corrected by the real part counting part of the equation (7).

In the process of accumulating the digit-corrected partial sum from the above equation, the digits-corrected partial sum from the least significant bit (0) to the (L-2) th bit is added and the partial sum corrected with the most significant bit (L-1) is subtracted Able to know. Therefore, in the accumulation circuit 23 of the present invention, the highest-order bits L-1 (L-1) and L-2 ) Is provided, the accumulation circuit 23 can accumulate the partial sum corrected by the real number count part-number correction in Equation (7).

The description of the accumulation circuit 23 and the accumulation circuit 25 are identical except that the input signal is not an actual coefficient but an imaginary coefficient.

Next, the accumulation circuit 27 for accumulating the results of the accumulation circuits 23 and 25 will be described.

When the real output data is obtained in Equation (7), the accumulated partial sum of the imaginary-number portion is to be subtracted from the accumulated partial sum of the real-number counting portion. When the imaginary output data of Equation (8) The sum of the sum and imaginary coefficients should be added to the cumulative partial sum. To this end, in the present invention, two arithmetic operators 271 and 273 in the accumulation circuit 27 and one adder 275 are constituted, and the value of the register R5 for storing the sum s (n) of the accumulation circuit 23 The value of the register R6 storing the carry c (n) of the accumulation circuit 23 is input to the input value y (n (n)) of the arithmetic unit 271, ) And the value of the register R7 for storing the total value s (n) of the accumulation circuit 25 is provided as the input value a (n) of the arithmetic unit 271. [

The carry value c (n) of the arithmetic operation unit 271 is inputted to the input (x (n)) of the arithmetic unit 273 by the input And the carry (c (n)) of the accumulation circuit 25 stored in the register R8 is provided as the input value a (n) of the arithmetic unit 273.

Here, the arithmetic operators 271 and 273 add all the three input values x (n), y (n), and a (n) when the addition / subtraction control signal is provided as logic 0, When the subtraction control signal is provided to the logic 1, an operation of subtracting the input value a (n) from the two input values x (n) and y (n) is performed. If the addition / subtraction control signal is logic 0 If the addition / subtraction control signal is logic 1 .

Therefore, when the real output data in Equation 7 is to be obtained, the addition / subtraction control signal of logic 1 is provided, and when the imaginary output data of Equation 8 is to be obtained, the addition / subtraction control signal of logic 0 must be provided .

To form the final operation result into one output, the adder 275 constructs one output by using a general CPA. However, the CPA can take a long time to calculate by the delay time due to the carry chain in the calculation process, and can cause a bottleneck. Thus, if the CPA is synchronized with the clock to obtain the partial sum, then the total computation time is increased by the adder 275.

In order to solve such a problem, in the present invention, the registers R5, R6, R7, and R8 are formed between the accumulation circuits 23 and 25 and the accumulation circuit 27, The arithmetic units 271 and 273 in the registers 25 and 27 are configured to sequentially calculate the partial sums in synchronization with the clock C and to store the calculated final values in the registers R5 and R6, Respectively. That is, the registers R5, R6, R7, and R8 store the values of the accumulation circuits 23 and 25 when all the L-1 partial sums are obtained. In other words, the registers R5, R6, R7 and R8 are connected to the accumulation circuit 23 in synchronization with the clock C _L having the same period as the (C 占 (L-1) , And (25), respectively.

A register (R5), (R6), (R7), (R8) a cumulative clock circuit 27. The clock also (C _L), such as (C _L) in synchronism with storing the calculated value of the accumulation circuit (23,25) to (R6), (R7), and (R8) in synchronism with the operation of the register R5. Therefore, it is possible to prevent the resultant value of the accumulation circuits 23 and 25 from becoming a bottleneck due to the delay time generated in the accumulation circuit 27. [

6 shows another embodiment of a high-speed accumulator 20 according to the present invention.

The high-speed accumulator 20 of FIG. 6 also includes an accumulation circuit 33, 35, which accumulates the partial sum of the real number portion and the imaginary number portion, respectively, and a cumulative partial sum of the real number portion and the imaginary number portion And is an accumulation circuit 37 part.

The high-speed accumulator 20 of FIG. 6 adopts a method of accumulating the carry and the sum, respectively, differently from the high-speed accumulator 20 of FIG. 6, the operator 331 in the accumulation circuit 33 inputs and accumulates only the carry of the partial sum of the real coefficients, and the operator 333 is configured to accumulate only the sum of the partial sums of the real coefficients have.

The accumulated values (carry and summation values) in the operators 331 and 333 are stored in the registers 341, 343, 345 and 347 as shown in the figure, Is designed to store data when the (L-1) th partial sum is accumulated, like the registers R5-R8 of FIG. That is, the operators 331 and 333 sequentially accumulate the partial sums by being synchronized by the clock C, and the accumulated values are synchronized with the clocks C x (L-1 ) and stored in the registers 341, 343, 345, and 347, respectively.

The cumulative values of the operators 331 and 333 stored in the registers 341, 343, 345 and 347 are added through the operators 335 and 337, respectively. That is, the operator 335 outputs the sum s (n) and carry (c (n)) of the operators 331 and 333 provided through the registers 341 and 343 of the operators 331 and 333 to the operator 333 (N) and the carry (c (n)) of the arithmetic operation unit 333 and the sum s (n) The adder 337 adds the accumulated values of the arithmetic units 331 and 333 to the final sum.

As in the embodiment of Fig. 3, the highest difference discrimination signal (a signal only when the highest-order bit is provided) is used in the accumulation circuit 33, and the arithmetic operators 331 and 333 compute the highest- Subtracts the input value from the accumulated value when the discrimination signal is provided, and adds the input value from the accumulated value when the highest-order bit discrimination signal of logic 0 is provided. Therefore, when the highest-order bit (L-1) discrimination signal is 0, the accumulation circuit 33 accumulates the digit-corrected partial sum from the least significant bit (0) to the (L-2) And the subtracted partial sum of the most significant bit (L-1) is subtracted. That is, it can be seen that the accumulation circuit 33 of the present invention can accumulate the fractional part-corrected partial sum shown in Equation (7) like the accumulation circuit 23.

The description of the accumulation circuit 33 and the accumulation circuit 35 also operate in the same manner as described above, except that the input signal is not an actual coefficient but an imaginary coefficient.

FIG. 7 shows a detailed block diagram of the operators 331, 333, 351, and 353 that perform the above-described functions.

As shown in the figure, the operator of Fig. 7 receives the input value a (n) and the inverted input value a (n), that is, the one's complement of a (n), via the inverter I2 to the multiplexer MUX2 And the multiplexer MUX2 outputs the input value a (n) when the control signal (# Add / Sub) is 0 and the input value a (n) ) ≪ / RTI >

The output value and the input value x (n) of the multiplexer MUX2 are provided to the input terminal a of the adders A11-A1n and the sum s (n) of the adders A11- (n) are provided to the input terminal b and the carry input terminal C _{in of the} adders A11-A1n via registers 71 and 73, respectively. That is, the operators 331, 333, 351, and 353 in FIG. 7 accumulate (or subtract) the summation and carry, which are partial summations of which the digits are corrected, respectively.

The results of the accumulation circuits 33 and 35 are provided to the accumulation circuit 37, and the accumulation circuit is configured the same as the accumulation circuit 27 of Fig. In the embodiment of FIG. 6, registers R5, R6, R7, and R8 are not configured differently from the embodiment of FIG. 4, but arithmetic operators 331, 333, and 351 And 353 are sequentially accumulated by the registers 341 to 367 and then finally computed by the operators 335 to 337 and provided to the accumulation circuit 37 so that the accumulation circuit 37 It is easily understood by those skilled in the art that the result of the accumulation circuits 33 and 35 can be calculated in synchronization with the clock (C 占 (L-1) ).

Hereinafter, the operation of the apparatus of the present invention constructed as described above will be described.

First, the filter coefficients are stored in the coefficient registers 13 and 15, respectively. Then, new input data is input to the real data register 1 and the imaginary data register 3, respectively, and first, the real output data is obtained. The least significant bit of the input data stored in the real data register 1 and the imaginary data register 3 is provided to the multiplexers 5 and 11 and the multiplexer 5 outputs the real input data To the multiplexer 5, and the multiplexer 7 provides the imaginary input data of the imaginary data register 3 to the multiplexer 11, respectively. In order to calculate the real output data, the multiplexer 9 selects the filter coefficient of the filter coefficient register 13 corresponding to the real input data and provides it to the adder tree 17, and the multiplexer 11 converts the The filter coefficient of the filter coefficient register 15 is selected and provided to the adder tree 17. [

The adder trees 17 and 19 add the selected filter coefficients and provide them to the digit correction registers R1 to R4. The high-order accumulator 20 sequentially adds the digit-corrected filter coefficient values, and the most significant bit (MSB) is added to the most significant bit (MSB) Is subjected to subtraction to carry out a formula for accumulating the partial sum corrected by the real number count part of the equation (7). Thereafter, the high-speed accumulator 20 calculates the real output data using the accumulated partial sum.

While the high-speed accumulator 20 calculates the real output data, the multiplexers 5, 7, 9, 11 perform the operation of obtaining the imaginary output data. That is, a set of the least significant bits of the input data stored in the real data register 1 and the imaginary data register 3 is provided to the multiplexers 5 and 11, and the multiplexer 5 outputs the imaginary data of the imaginary data register 1 And provides the data to the multiplexer 9, and the multiplexer 7 provides the real input data of the real data register 3 to the multiplexer 11, respectively. In order to calculate the imaginary output data, the multiplexer 9 selects and provides the filter coefficients of the filter coefficient register 13 corresponding to the imaginary input data to the adder tree 17, The filter coefficient of the filter coefficient register 15 is selected and provided to the adder tree 17. [

The adder trees 17 and 19 add the selected filter coefficients and provide them to the digit correction registers R1 to R4. The high-order accumulator 20 sequentially adds the digit-corrected filter coefficient values, and the most significant bit (MSB) is added to the most significant bit (MSB) Is subjected to subtraction to carry out a formula for accumulating the partial sum corrected by the real number count part of the equation (7). Thereafter, the high-speed accumulator 20 calculates the imaginary output data using the accumulated partial sum.

Similarly, while the high-speed accumulator 20 outputs the imaginary output data using the accumulated partial sum, new input data is received and stored in the input data registers 1 and 3, and a process for obtaining the real output data is performed.

The filtering operation is performed by repeating this process.

As described above, according to the present invention, it is possible to design the system using fewer resources by using the data characteristics of the two's complement type rather than the hardware using the conventional filter structure.

In the present invention, the delay time of the operation circuit is reduced by implementing the adder tree portion in the CSA, and the CPA for obtaining the final result is driven by the clock (Cx (L-1) ) So that the filtering can be performed at a very high speed by eliminating the bottleneck phenomenon.

Claims (17)

A high-speed digital filter having a bit- A real data register for storing real input data; An imaginary data register for storing imaginary input data; First and second multiplexers for selecting and outputting the real and imaginary numbers of the real data register and the imaginary data register, respectively; A first coefficient register for storing a real number filter coefficient; A second coefficient register for storing imaginary filter coefficients; A third multiplexer for selecting and outputting a filter coefficient of a first coefficient register corresponding to a real number and an imaginary number of the first and second multiplexers; A fourth multiplexer for selecting and outputting a filter coefficient of a second coefficient register corresponding to a real number and an imaginary number of the first and second multiplexers; First and second adder trees for respectively adding outputs of the third and fourth multiplexers; A first and a second digit correction register for respectively correcting the digits of the adder tree output by shifting outputs of the first and second adder trees; And a high-speed accumulator for calculating the output of the first and second digit correction registers to calculate real output data and imaginary output data. The method according to claim 1, Wherein said first and second multiplexers provide a real number of said real data register to said third multiplexer and an imaginary number of said imaginary data register to a fourth multiplexer to first calculate real output data, And provide an imaginary number of said real data register to said fourth multiplexer and an imaginary number of said imaginary data register to a third multiplexer to produce imaginary output data. The method according to claim 1, The high-speed accumulator A first accumulation circuit for accumulating the real number coefficients provided from the first digit correction register and for subtracting the most significant real number coefficient; A second accumulation circuit for accumulating the imaginary coefficients provided from the second digit correction register and subtracting the highest imaginary coefficient; And a third accumulation circuit for selectively adding and subtracting the cumulative partial sum of the first and second accumulation circuits according to an addition / subtraction signal. The method of claim 3, Further comprising first to fourth partial sum storing registers for respectively storing partial sums from the first and second accumulation circuits, Wherein the first to fourth partial sum storing registers are configured to cause the first and second accumulation circuits to finally calculate the partial sum and provide the stored value to the third accumulation circuit. 5. The method of claim 4, Wherein the first and second accumulation circuits are configured to output a sum and a carry of the partial sum, respectively, Wherein the first to fourth partial sum storing registers are configured to store summation and carry provided from the first and second accumulation circuits, respectively. 6. The method of claim 5, Wherein the first accumulation circuit comprises: Wherein the first arithmetic unit comprises: first and second arithmetic operators; a first sum storage register and a first carry storage register, wherein the first arithmetic operator comprises: a carry of the first adder tree provided from the first digit correction register; And the second arithmetic operation unit adds and subtracts the sum and carry of the first arithmetic operation unit from the first adder tree provided from the first digit correction register and the sum of the first arithmetic operation register and the carry of the first carry storage register, Of the input signal is controlled in accordance with a control signal. 7. The semiconductor memory device according to claim 6, And a third register for storing a second adder tree and a second register for storing the second adder tree, wherein the third and fourth operators, the second sum storage register and the second carry storage register, The sum of the registers for storing the sum and the carry of the register for storing the second carry are added or subtracted in accordance with the control signal and the fourth operator adds and subtracts the sum and carry of the third operator and the second adder tree provided from the second digit register A high-speed digital filter of a bit division structure configured to add and subtract a sum according to a control signal. 8. The method according to claim 6 or 7, Wherein said control signal indicates said subtraction when a value of the highest-order bit is provided and indicates said addition when a value of a bit other than the highest-order bit is provided. 9. The method of claim 8, The third accumulation circuit The sum of the real numbers of the first accumulation circuit provided from the first partial sum storage register and the carry of the first accumulation circuit provided from the second partial sum storage register is added to the sum of real numbers of the first accumulation circuit provided from the third partial sum storage register A fifth calculator for selectively adding and subtracting the sum of the provided second accumulation circuits according to an addition / subtraction signal; A sixth calculator for selectively adding and subtracting a carry of the second accumulation circuit provided from the register for storing the fourth partial sum to an addition value of the sum and carry from the fifth operator according to an addition / subtraction signal; And a first CPA adder for adding the carry and the sum of the sixth operator. 10. The method of claim 9, Wherein the addition / subtraction signal acts as a subtraction signal when obtaining the real output data and as an addition signal when the imaginary output data is obtained. 11. The method of claim 10, Wherein the first to sixth arithmetic operators comprise: A first inverter for inverting a first input value added / subtracted in accordance with a control signal; A fifth multiplexer for selecting the first input value or the output of the first inverter according to the control signal; Wherein the least significant bit adder of the plurality of first group adders inputs the output of the fifth multiplexer and the second input value to the input terminal and inputs the control signal to the carry input terminal In addition, The first group of adders excluding the least significant bit adder inputs the output of the fifth multiplexer and the second input value to the input terminal and the third input value to the carry input terminal, . The method of claim 3, Wherein the first accumulation circuit comprises: A seventh calculator for adding and subtracting the carry of the first adder tree provided from the first digit correction register according to a control signal to provide a sum value and a carry, An eighth calculator for adding and subtracting the sum of the first adder tree provided from the second digit correction register according to a control signal to provide a sum and a carry; A third and a fourth total storage register for respectively storing a sum of the seventh and eighth operators; Third and fourth carry storing registers for respectively storing the carry of the seventh and eighth operators; A ninth operator for adding the carry and sum of the seventh operator provided from the third and fourth total storage registers and the third carry storage register and the sum of the eighth operator; And a tenth operator for adding the carry value of the ninth operator and the carry of the eighth operator provided from the fourth carry storage register. The method of claim 3, The second accumulation circuit comprises: An 11th arithmetic operation unit for adding / subtracting the carry of the second adder tree provided from the third digit correction register according to a control signal to provide a sum value and a carry, A twelfth operator for adding and subtracting the sum of the second adder tree provided from the fourth digit correction register according to a control signal to provide a sum and a carry; A fifth and a sixth total storage register for storing the sum of the eleventh and twelfth operators; Fifth and sixth carry storing registers respectively storing the carry of the eleventh operator and the twelfth operator; A thirteenth operator for adding the carry and sum of the eleventh operator provided from the fifth and sixth total storage registers and the fifth carry storage register and the sum of the twelfth operator; And a fourteenth operator for adding the carry of the thirteenth operator and the carry of the thirteenth operator provided from the sixth carry storing register. The method according to claim 12 or 13, Wherein said control signal indicates said subtraction when a value of the highest-order bit is provided and indicates said addition when a value of a bit other than the highest-order bit is provided. 15. The method of claim 14, The third accumulation circuit A fifteenth calculator for selectively adding and subtracting the sum of the second accumulation circuits according to an addition / subtraction signal to a sum of real numbers and a carry of the first accumulation circuit; A 16th arithmetic operator for selectively adding and subtracting the carry of the second accumulation circuit from the 15th arithmetic unit to the sum of the carry and the adder of the carry according to the addition / subtraction signal; And a second CPA type adder for adding the carry and sum of the 16th arithmetic operator. 16. The method of claim 15, Wherein the addition / subtraction signal acts as a subtraction signal when obtaining the real output data and as an addition signal when the imaginary output data is obtained. 17. The method of claim 16, Wherein the seventh to fourteenth arithmetic operators comprise: A second inverter for inverting the control signal; A fifth multiplexer for selecting and outputting the fourth input value or the output of the second inverter according to the control signal; A plurality of adders constituting a second group, a seventh total storage register and a seventh carry storage register, The least significant bit adder of the second group of adders inputs the output of the fifth multiplexer and the output of the seventh total storage register to the input terminal and inputs the control signal to the carry input terminal, The adders excluding the adder of the least significant bit input the output of the fifth multiplexer and the output of the seventh total storage register to the input terminal and the bit which is configured to input the output of the seventh carry storage register to the carry input terminal High-speed digital filter with separate structure.