CN204316468U - A kind of multi-path digital filter - Google Patents

Abstract

The utility model relates to a multi-channel digital filter, comprising: parallel/serial converters connected in sequence, a filter module and a serial/parallel converter; multiple parallel data streams are input into the parallel/serial converter, and parallel/serial conversion The converter is used to convert the input multiple parallel data streams into a high-speed serial data stream; the filter module is a lattice filter module, which is used to filter the serial data stream; the serial/parallel converter is used to convert the filtered The serial data stream is converted into multiple parallel data streams; a control module is also included, the control module is connected with the parallel/serial converter, the filter module and the serial/parallel converter, and the control module is used for generating data selection signals and address selection signals. The multi-channel digital filter of the present invention is based on the design of the lattice structure, which improves the deterioration of the filtering performance caused by the rounding or truncation in the digital filter operation process; in the system where multiple data streams can use the same filter, multiple The input and output design saves hardware overhead.

Description

A kind of multi-channel digital filter

technical field

The utility model relates to a multi-channel digital filter.

Background technique

Digital filter is a commonly used device in digital signal processing. It can be divided into two types: FIR (finite impulse response) and IIR (infinite impulse response), and there are various network structures, such as direct type, cascade type, etc., among which A filter with a new lattice structure has the following characteristics: (1) the modular structure facilitates high-speed parallel processing; (2) an n-order lattice filter can generate n The output performance of the transversal filter; (3) insensitive to the rounding error of the limited word length. Because of these advantages, it has been widely used in digital filters.

At present, the problems existing in the digital filter based on the circuit can be attributed to two categories, one is the effective word length effect, because the relevant parameters of the digital filter and the results of the operation process must be stored in a finite storage unit, There is an error between the filter realized by the circuit and the ideal filter, which affects the filtering performance. Second, the realization of filters generally requires a large number of computing circuits, especially high-order and high-precision filters, and the resource consumption will be particularly large. Many effective methods have been proposed to reduce resource consumption, such as parallel/serial conversion , Ping-pong structure, circuit multiplexing, etc., it is necessary to choose an appropriate method for different design structures.

Utility model content

In view of the above-mentioned problems of current digital circuit filters, the purpose of this utility model is to provide a multi-channel digital filter, based on lattice structure design, to improve the deterioration of filter performance caused by rounding or truncation in the operation process of digital filters ; In a system where multiple data streams can use the same filter, the multi-input multi-output design fully multiplexes the circuit and saves hardware overhead.

The utility model relates to a multi-channel digital filter, comprising: a parallel/serial converter connected in sequence, a filtering module and a serial/parallel converter;

Multiple parallel data streams are input into the parallel/serial converter, and the parallel/serial converter is used to convert the input multiple low-speed parallel data streams into one serial data stream;

The filtering module is a lattice filtering module, which is used to filter the serial data stream;

The serial/parallel converter is used to convert the filtered serial data stream into multiple parallel data streams;

Also includes a control module, the control module is connected with the parallel/serial converter, the filter module and the serial/parallel converter, the control module is used to generate a data selection signal and an address selection signal, the The data selection signal is used to control the parallel/serial conversion and serial/parallel conversion of the data stream, and the generation of the address selection signal, and the address selection signal is used to select the access address of the intermediate data in the filtering module.

Specifically, the filter module includes:

A plurality of multipliers and adders, each of which is composed of a multiplier and an adder, is used to multiply one path of the parallel data stream and the coefficient of the filter module through the multiplier, and the result is compared with another One way of the parallel data streams is added by an adder;

A plurality of memories, the plurality of memories are respectively connected to the plurality of multiply-accumulators for accessing the operation results of the multiply-accumulators;

A filter coefficient memory, the filter coefficient memory is connected to the plurality of multiply-adders, used to store the coefficients of the filtering module, and output to each of the multiply-adders respectively.

Preferably, the number of multipliers and adders is (3*n+1), where n is the order of the filtering module.

Preferably, the memory is a circular access memory, the number of the memory is n, n is the order of the filtering module, and each of the memory has I units, and I is the input parallel data stream the number of ways.

Specifically, the control module includes:

Address generator, the address generator is connected with the parallel/serial converter and the serial/parallel converter, the address generator is used to generate a data selection signal, output to the parallel/serial converter, the The data address selector and the serial/parallel converter, the data selection signal is used to control the parallel/serial conversion and serial/parallel conversion of the data stream, and the generation of the address selection signal, the address generator includes A counter, the counter is used to implement internal loop counting according to the number of paths of the input parallel data stream;

A data address selector, the data address selector is connected with the address generator and the memory, generates an address selection signal according to the data selection signal, and is used to select the intermediate data in the filtering module in the Access address in memory.

Specifically, the counting bit width i of the counter of the address generator is an upward rounding of log2I, wherein I is the number of channels of the input parallel data stream, and the address range of the address generator is 0～(2 ⁱ -1).

Because the multi-channel digital filter of the utility model adopts a lattice structure, it is insensitive to the rounding and truncation of the intermediate calculation results, and is not limited by the order of the filter and the coefficient of the filter. By adding simple control logic and a small number of storage units, the filtering of multiple data streams is realized, the circuit is fully multiplexed, and the hardware cost is greatly saved, and the more channels of input parallel data streams, the more multiplexed The more circuits there are, the more resources can be saved; the filter of the utility model is not limited by the coefficient and order of the filter, can be flexibly set according to the needs of filtering performance, has good scalability and high practical value.

Description of drawings

Fig. 1 is the structural diagram of multi-channel digital filter of the present utility model;

Fig. 2 is the structural representation of multiplier adder;

Fig. 3 is the structural representation of memory;

Fig. 4 is a structural diagram of a second-order lattice IIR filter.

Detailed ways

The multi-channel digital filter of the present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 1 is the structural diagram of the multi-channel digital filter of the present utility model, comprises parallel/serial converter S1 connected in sequence, filtering module S3 and serial/parallel converter S4, and simultaneously with parallel/serial converter S1, filtering Module S3 and serial/parallel converter S4 are connected to control module S2.

In the parallel/serial converter S1, input multiple parallel data streams (the first road to the first road in the figure), and the parallel/serial converter S1 converts the parallel data streams into one high-speed serial data stream, and the input The data stream is data that can be sampled and filtered by the same filter, such as three (I _A , I _B , and V) signals in single-phase metering and six (I _A , _VA , I _B , V _{B )} signals in three-phase metering. , I _C and V _C ) need to pass through the same high-pass filter to filter out the DC component, each phase power ( _PA , P _B and P _C ) need to pass through the same low-pass filter to filter out the AC component, each current and voltage ( I _A , V _A , I _B , V _B , I _C and V _C ) need to pass through the same fundamental wave filter to filter out harmonic components, etc.; and the more channels of input parallel data streams, the more multiplexing circuits The more, the more resources can be saved.

In order to facilitate hardware processing, the parallel input data stream of the fastest path inputs a data, and the parallel/serial converter S1 outputs 2 ⁱ data, where i is the upward rounding of log ₂ I, and I is the parallel input data in the figure The number of streams, for example, the input parallel data stream is three (I _A , I _B and V), i.e. I=3, the rounded up i of log ₂ I is 2, and the output of parallel/serial converter S1 is every 4 That is, one invalid data needs to be inserted in the ²² data.

The parallel/serial converter S1 realizes conversion according to the input data selection signal, for example, when the data selection signal is 0, the parallel/serial converter S1 selects and outputs the first data, when the data selection signal is (I-1), and/or The serial converter S1 selects and outputs the I-th channel of data, and when the range of the data selection signal is (I˜(2 ⁱ −1)), the parallel/serial converter S1 outputs invalid data “0”.

The control module S2 includes an address generator S21 and a data address selector S22, and the address generator S21 is connected with the parallel/serial converter S1, the serial/parallel converter S4 and the data address selector S22; the data address selector S22 is connected with the filter module S3 is connected. The control module S2 generates a data selection signal through the address generator S21 according to the number of parallel data streams input by the parallel/serial converter S1, and outputs it to the parallel/serial converter S1 and the serial/parallel converter S4 for controlling the data flow Parallel/serial and serial/parallel conversion, the address selection signal is generated by the data address selector S22, and output to the filter module S3, which is used to control the access of the intermediate data of the operation in the memory.

Specifically, the address generator S21 is used to generate the data selection signal, which is realized by internal loop counting, and the counting bit width i of the internal loop counter is rounded up by log ₂ I, and I is the number of paths of the input parallel data stream , the address range of the address generator S21 is 0~(2 ⁱ -1).

The data address selector S22 generates an address selection signal for data access based on the data selection signal generated by the address generator S21, which is used to select the access address of the intermediate data in the filter module S3 described later in the first memory to the Mth memory .

The filter module S3, based on the logic control of the internal memory, uses the lattice filter module to realize the filtering function of multiple data streams; it includes multiple multipliers S31 and multiple memories S32 connected to each other, and also includes a filter coefficient memory S33. The filter coefficient memory S33 is connected to a plurality of multiply-adders S31, and the data address selector S22 is connected to a plurality of memories S32. The filtering module S3 will be described in detail below in conjunction with FIG. 1 , FIG. 2 , and FIG. 3 .

Figure 2 is a schematic diagram of the structure of the multiplier-adder S31. The multiplier-adder S31 is composed of a multiplier and an adder. After the input data X1 and the filter coefficient K are multiplied by the multiplier, the result is added to another input data X2. The result is Y; an n-order lattice filter requires (3*n+1) multipliers and adders, and the filter coefficient K is stored in the filter coefficient memory S33.

FIG. 3 is a schematic structural diagram of the memory S32. The memory S32 stores the intermediate calculation results of the filter according to the address selection signal of the data address selector S22. The memory S32 performs cyclic access, and the access operation address is determined by the address selection signal generated by the data address selector S22, and within the same sampling time, the data of the same address is first taken out to the next multiplier, and then stored in The data output by the last multiplier-adder; the number of memories is determined by the order of the lattice filter, and the n-order lattice filter needs n memories, each of which has I units, and I is the number of ways to input parallel data streams , such as a second-order filter, the parallel data flow is four, then a total of 2 memories are required, and each memory requires 4 units.

Next, the multi-channel digital filter of the present invention will be described in detail with reference to FIG. 4 . Fig. 4 is a structural diagram of a second-order lattice IIR filter. The filter coefficients [K1, K2, V1, V2, V3] are designed by MATLAB. If it is necessary to filter the three parallel data streams, the parallel/serial converter S1 outputs x1, x2, x3 and invalid data 0 in turn. Input Go to module S3, get m1, m2, m3 and invalid data 0 in sequence after passing through two multipliers and adders. Store the current value m1 into this unit, and the storage and retrieval should be completed within one sampling time. It should be noted that the invalid data 0 has no corresponding storage unit. The storage address corresponding to each data is controlled by the data address selector S2; a similar operation is adopted for the second memory, and finally the filtering results y1, y2, y3 and invalid data 0 are sequentially output. In the dotted line box in Figure 4, one input of the adder is 0, which together with the multiplier is equivalent to a multiply-adder.

The serial/parallel converter S4 is the opposite of the function of the parallel/serial converter S1, and is used to convert the filtered serial data stream into multiple parallel data streams, and the number of parallel data streams output is parallel to that of the input The number of paths of the data stream is the same, so the invalid data in the filtered serial data stream should be discarded.

In this way, the multi-channel digital filter of the present utility model is based on the design of the lattice structure, which improves the deterioration of the filtering performance caused by rounding or truncation in the digital filter operation process; in a system where multiple data streams can use the same filter, The multi-input and multi-output design fully multiplexes circuits and saves hardware overhead.

The above embodiments are only for the purpose of illustrating the utility model, rather than limiting the utility model. Those skilled in the relevant technical fields can also make various changes or modifications without departing from the spirit and scope of the utility model. Therefore, all Equivalent technical solutions should also belong to the category of the present utility model, and should be defined by each claim.

Claims (6)

1. A multi-channel digital filter is characterized in that, comprising: a parallel/serial converter connected in sequence, a filtering module and a serial/parallel converter; Multiple parallel data streams are input into the parallel/serial converter, and the parallel/serial converter is used to convert the input multiple low-speed parallel data streams into one serial data stream; The filtering module is a lattice filtering module, which is used to filter the serial data stream; The serial/parallel converter is used to convert the filtered serial data stream into multiple parallel data streams; Also includes a control module, the control module is connected with the parallel/serial converter, the filter module and the serial/parallel converter, the control module is used to generate a data selection signal and an address selection signal, the The data selection signal is used to control the parallel/serial conversion and serial/parallel conversion of the data stream, and the generation of the address selection signal, and the address selection signal is used to select the access address of the intermediate data in the filtering module. 2. multi-channel digital filter as claimed in claim 1, is characterized in that, described filtering module comprises: A plurality of multipliers and adders, each of which is composed of a multiplier and an adder, is used to multiply one path of the parallel data stream and the coefficient of the filter module through the multiplier, and the result is compared with another One way of the parallel data streams is added by an adder; A plurality of memories, the plurality of memories are respectively connected to the plurality of multiply-accumulators for accessing the operation results of the multiply-accumulators; A filter coefficient memory, the filter coefficient memory is connected to the plurality of multiply-adders, used to store the coefficients of the filtering module, and output to each of the multiply-adders respectively. 3. The multi-channel digital filter according to claim 2, wherein the number of said multiply-adders is (3*n+1), wherein n is the order of said filtering module. 4. multi-channel digital filter as claimed in claim 2, is characterized in that, described memory is circular access memory, and the number of described memory is n, and n is the order number of described filtering module, and every Each memory has I units, and I is the number of ways of input parallel data streams. 5. multi-channel digital filter as claimed in claim 2, is characterized in that, described control module comprises: Address generator, the address generator is connected with the parallel/serial converter and the serial/parallel converter, the address generator is used to generate a data selection signal, output to the parallel/serial converter, the The data address selector and the serial/parallel converter, the data selection signal is used to control the parallel/serial conversion and serial/parallel conversion of the data stream, and the generation of the address selection signal, the address generator includes A counter, the counter is used to implement internal loop counting according to the number of paths of the input parallel data stream; A data address selector, the data address selector is connected with the address generator and the memory, generates an address selection signal according to the data selection signal, and is used to select the intermediate data in the filtering module in the Access address in memory. 6. multi-channel digital filter as claimed in claim 5, is characterized in that, the counting bit width i of the described counter of described address generator is the rounding up of log ₂ I, and wherein I is the parallel data flow of input The number of channels, the address range of the address generator is 0~(2 ⁱ -1).