CN114185014A - Parallel convolution method and device applied to radar signal processing - Google Patents
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Abstract
The invention discloses a parallel convolution method and a parallel convolution device applied to radar signal processing. The method comprises the following steps: carrying out segmented storage on the input signals with any length and the system function; the input signal is a radar excitation signal, and the system function is a target response function of the radar excitation signal; respectively carrying out fast Fourier transform on the input signals and the system functions after the segmented storage; performing complex multiplication and inverse fast Fourier transform on the input signal after fast Fourier transform and a system function to obtain a multi-section convolution result; and sequentially superposing the multiple sections of convolution structures according to a set rule and a time sequence to obtain a final convolution result. The invention adopts a mode of parallel processing of a plurality of pipelines to carry out a series of operations such as segmentation, storage, FFT, complex multiplication, IFFT, overlap addition and the like on input signals and system functions, realizes convolution operation, shortens the processing time and improves the running speed.
Description
Technical Field
The invention relates to the technical field of radar signal processing, in particular to a parallel convolution method and a parallel convolution device applied to radar signal processing.
Background
In signal processing applications, convolution is a very common and important operation, such as various signal filtering in communication, echo operation in radar simulators, and the like. In high-speed signal processing application, the convolution operation speed directly influences the response time of a signal processing system and restricts the improvement of the system performance.
Taking the application of the real-time closed-loop echo simulator of the synthetic aperture radar as an example, in the process of generating a scene echo signal in real time, convolution needs to be performed once each time an echo calculation parameter data packet is received. The number of points for convolution of the radar excitation signal and the system function is large, the calculation amount is large, and challenges are provided for the design of the system. The design requirement is to realize the fast convolution between an input signal with any length and a system function with a fixed length (such as 8192 points) on the FPGA (such as ensuring that the convolution between 4096 points and 8192 points can be completed in every 30us under a pipeline state). In the conventional convolution, when convolution is performed, an input signal x (n) and a system function h (n) must be of a certain length, and any long convolution cannot be completed. In addition, the traditional convolution processing has long time delay (for example, when the convolution operation of 4096 points and 8192 points is carried out, the clock period required by FFT conversion is 32918 clock periods, the required time under a 200MHZ clock is 164.59us), and the design requirement cannot be met.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a parallel convolution method and apparatus for radar signal processing, which can perform convolution operation on any radar excitation signal, shorten processing time, and increase system operation speed.
In order to achieve the purpose, the invention provides the following scheme:
a parallel convolution method applied to radar signal processing, comprising:
carrying out segmented storage on the input signals with any length and the system function; the input signal is a radar excitation signal, and the system function is a target response function of the radar excitation signal;
respectively carrying out fast Fourier transform on the input signals and the system functions after the segmented storage;
performing complex multiplication and inverse fast Fourier transform on the input signal after fast Fourier transform and a system function to obtain a multi-section convolution result;
and sequentially superposing the multiple sections of convolution structures according to a set rule and a time sequence to obtain a final convolution result.
Optionally, the input signal is divided into 4 segments and the system function is divided into 8 segments.
Alternatively, the fast fourier transform uses 12 pipelines in parallel, wherein 4 pipelines are input, and 8 pipelines are input to the system function.
Optionally, the complex multiplication and inverse fast fourier transform are in 32 pipeline parallel.
The invention also provides a parallel convolution device applied to radar signal processing, which comprises:
the first segmented storage module is used for carrying out segmented storage on the input signal; the input signal is a radar excitation signal;
the second segment storage module is used for carrying out segment storage on the system function; the system function is a target response function of the radar excitation signal;
the first FFT calculation module is connected with the first segmentation storage module and used for carrying out fast Fourier transform on the segmented input signals;
the second FFT calculation module is connected with the second segmented storage module and is used for carrying out fast Fourier transform on the segmented system function;
the complex multiplication and IFFT calculation module is connected with the first FFT calculation module and the second FFT calculation module and is used for carrying out complex multiplication and inverse fast Fourier transform on the input signal after fast Fourier transform and a system function to obtain a multi-section convolution result;
and the overlap-add module is connected with the complex multiplication and IFFT calculation module and is used for sequentially overlapping the multi-section convolution structures according to a set rule and a time sequence to obtain a final convolution result.
Optionally, the first segment storage module includes:
a first segmentation unit for segmenting the input signal;
a first storage unit for storing the segmented input signal;
the second segmented storage module comprises:
the second segmentation unit is used for segmenting the system function;
and the second storage unit is used for storing the segmented system function.
Optionally, the first FFT computation module employs 4 parallel pipelines; the second FFT computation module adopts 8 parallel pipelines.
Optionally, the complex multiplication and IFFT computation module employs 32 parallel pipelines.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention adopts a mode of parallel processing of a plurality of pipelines to carry out a series of operations such as segmentation, storage, FFT, complex multiplication, IFFT, overlap addition and the like on input signals and system functions, realizes convolution operation, shortens the processing time and improves the running speed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a flow chart of a parallel convolution method applied to radar signal processing according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating the stacking of segments in a segmented convolution process;
FIG. 3 is an arbitrarily long convolution of an input signal;
FIG. 4 is a paragraph transformation diagram;
FIG. 5 is a view showing an internal structure of a first segmentation unit;
FIG. 6 is a view showing an internal structure of a second memory cell;
FIG. 7 is a diagram of the structure of div _ store _ s1_ ctrl of a memory cell
FIG. 8 is one pipeline of the FFT transform portion;
FIG. 9 shows one of the pipelines of the complex multiplication and IFFT transform sections;
FIG. 10 is a view showing a structure of an overlap-add portion;
FIG. 11 is a resource usage scenario;
FIG. 12 is the result after convolution;
fig. 13 is a frequency domain waveform of the output result.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a parallel convolution method and a parallel convolution device applied to radar signal processing, which are used for realizing convolution operation on radar excitation signals of any length, shortening the processing time and improving the running speed of a system.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, the parallel convolution method applied to radar signal processing provided by the present invention includes:
And 2, respectively carrying out fast Fourier transform on the input signals and the system functions after the segmented storage. The fast Fourier transform adopts a 12-pipeline parallel mode, wherein 4 pipelines are input, and 8 pipelines are input in a system function.
And 3, performing complex multiplication and inverse fast Fourier transform on the input signal subjected to fast Fourier transform and the system function to obtain a multi-section convolution result. The complex multiplication and the inverse fast Fourier transform adopt a 32-pipeline parallel mode.
And 4, sequentially superposing the multiple sections of convolution structures according to a set rule and a time sequence to obtain a final convolution result.
The convolution result of the input signal x (n) and the system function h (n) can be expressed as y (n) ═ x (n) × h (n), and the length of the output sequence is the sum of the length of the input sequence and the length of the system function minus 1. The linear convolution method has high resource consumption and cannot realize the real-time signal processing. The design idea of the segmented convolution is to divide the long sequence into a plurality of short segments, and superpose the convolution results between the segments of the input signal and the segments of the system function according to a corresponding rule, so as to obtain a convolution result y (n).
Assuming that the input signal x (N) can be divided into M segments of length L, the system function h (N) can be divided into N segments of length L. By xi(n) and hj(N) represents the segmentation signals of x (N) and h (N), respectively (1. ltoreq. i.ltoreq.M, 1. ltoreq. j.ltoreq.N):
using x to convert y (n)i(n) and hj(n) may be expressed as:
xi(n) and hjThe values of (n) are not all concentrated in the first L points, for which a new variable X is introducedi(n) and Hj(N) (1. ltoreq. i.ltoreq.M, 1. ltoreq. j.ltoreq.N) which have a value only at the first L points.
To better formulate the final convolution result, the variable X is evaluatedi(n) and Hj(n) expanding. When M is<i≤M+N-1，N<When j is less than or equal to M + N-1:
the final convolution result can be expressed as (where k is an integer from 0 to M + N-1 and p is an integer from 0 to L):
equation (6) already shows the convolution result of the input signal x (n) and the system function h (n) at fixed length, which can be further expressed as:
when the input signal is arbitrarily long, as shown in fig. 2, the system function is 8192 points, the convolution can be viewed as a number of 4096 points of signal convolved with the system function. By using
Representing the first segment of 4096 point input signals convolved with the system function,
the second segment is represented by a second segment,
represents a third stage, reuse
Indicating a fourth segment, and so on. Taking one of the segments as an example, the analysis is performed as shown in FIG. 3. Fig. 4 shows a conversion relationship of a paragraph in the convolution process, which can be expressed as formula (8), where T is 4, q is a natural number, and z is q \ 3.
The invention also provides a parallel convolution device applied to radar signal processing, which comprises:
the first segmented storage module is used for carrying out segmented storage on the input signal; the input signal is a radar excitation signal;
the second segment storage module is used for carrying out segment storage on the system function; the system function is a target response function of the radar excitation signal;
the first FFT calculation module is connected with the first segmentation storage module and used for carrying out fast Fourier transform on the segmented input signals;
the second FFT calculation module is connected with the second segmented storage module and is used for carrying out fast Fourier transform on the segmented system function;
the complex multiplication and IFFT calculation module is connected with the first FFT calculation module and the second FFT calculation module and is used for carrying out complex multiplication and inverse fast Fourier transform on the input signal after fast Fourier transform and a system function to obtain a multi-section convolution result;
and the overlap-add module is connected with the complex multiplication and IFFT calculation module and is used for sequentially overlapping the multi-section convolution structures according to a set rule and a time sequence to obtain a final convolution result.
Wherein the first segmented storage module comprises:
a first segmentation unit for segmenting the input signal;
a first storage unit for storing the segmented input signal;
the second segmented storage module comprises:
the second segmentation unit is used for segmenting the system function;
and the second storage unit is used for storing the segmented system function.
The specific embodiment is as follows:
the implementation principle of the method is described below by taking an example of convolution of 4 segments (4 1024-point signals) and 8 segments (8 1024-point functions) of any long input signal (radar signal) at each stage.
Input signal x (n) is a sine wave of 50MHz frequency and amplitude 2^15, sending 4096 points of input signal every 30 us. The system function h (n) (target response function) is 8192 points of data.
The method comprises the following steps: segmented storage section
The first operation to be performed after the data is received is segment storage, and the function and detailed design of the segment storage are described below.
The function realized by the part is the segmented storage of the input signal and the system function. The input signal is divided into 4 segments and stored, and the system function is divided into 8 segments and stored. The two parts have the same integral structure, and only the difference of the number of the segmentation sections exists. The input signal is taken as an example for analysis, and the input signal can be further refined into the first segmentation unit and the first storage unit.
The main function of the first segmentation unit is to segment the input signal and divide the input signal into 4 segments of 1024-point signals. As shown in fig. 5, the first segmentation unit has 3 inputs and 5 outputs. The 3 inputs are respectively a reset signal, a data valid signal and a data signal. Wherein 4 outputs correspond to 4 channels of signals after segmentation processing respectively, and the other 1 output is a judgment signal for storing the output signal. The Start _ div _ flag block generates a control signal for controlling the section to count segments. The Div _ len _ counter block performs the function of counting, giving the next stage block an enable signal after every 1024 counts. The Div _ num _ counter module implements counting of the number of segments of a segment, and outputs a Div _ N _ F signal to the Start _ Div _ flag module when the count reaches the number of segments of the segment.
The first memory cell implements the storage and reading operations of signals, and the division of x (n) into 4 segments of 1024 dots data has been mentioned above. As shown in fig. 6, the first storage unit includes 4 modules, each corresponding to 4 segments of 1024 dots of data. As shown in fig. 7, the analysis is performed by one module div _ store _ s1_ ctrl, which implements the function of storing 1024 points of data, and stores the data in 4 RAMs, respectively, each RAM having 256 points. Then, data in 4 RAMs are sequentially read out at the time of reading, 1024 0 s are added to the rear of the read data, and then the first memory cell is output. The function of RAM _ wr _ ctrl block and truncation block (IQ0, IQ1, IQ2, IQ3) is to store one data at a time into RAM, and store cyclically from Dual Port RAM _1 to Dual Port RAM _4 until each RAM is full of 256 data. The main functions realized by the Start _ div _ flag module and the div _ len _ counter module are to generate a read address signal of the RAM and read data in the RAM. The function of the data selector in front of the Output _ ctrl module is to sequentially select data in 4 RAMs for reading, and the function of the Output _ ctrl module is to complement 1024-point 0 after 1024-point data Output, and Output the result to the next stage.
Step two: FFT transform section
The input signal x (n) is divided into 4 segments, the system function h (n) is divided into 8 segments, and after zero padding, 2048 points of data are obtained. They flow out of the segment storage section and then enter the FFT conversion section.
The FFT processing part adopts a 12-pipeline parallel mode, wherein 4 pipelines are input, and 8 pipelines are input for system functions. The Fast Fourier transform 9.0 module is called in the part, and FFT conversion of the segmented signals is realized.
The RE _ ROUND _ GAIN module and the IM _ ROUND _ GAIN module realize that the real part and the imaginary part of the signal after FFT are truncated, and then the real part and the imaginary part are spliced and output. Fig. 8 shows one pipeline of the FFT conversion part.
Step three: complex multiplication and IFFT transform section
After the 4 segments of the input signal x (n) and the 4 segments of the system function h (n) are output from the FFT transformation portion, they enter the complex multiplication and IFFT transformation portion.
The complex multiplication and IFFT transformation part adopts a parallel 32-pipeline manner, so that the input signal segment and any segment of the system function can realize complex multiplication (4 × 8 ═ 32), and analysis is performed by taking one pipeline as an example, as shown in fig. 9. The complete _ MUL module calls a complete Multiplier 6.0 module inside to realize COMPLEX multiplication operation. The Fast Fourier Transform 9.0 module is called inside the IFFT module, so that IFFT transformation is realized.
Step four: overlap-add section
The result after IFFT conversion is superposed after coming out of the IFFT module, the result is divided into 11 paths and superposed by 32 small segments of convolution results according to corresponding rules, and the superposed result flows into an overlap-add part.
The internal structure of the overlap-add portion is shown in fig. 10. The Fifo _ group module is used for storing convolution results, each Fifo group can store the result of 4096-point and 8192-point convolution once, and the internal part of the Fifo group comprises 22 FIFOs, wherein 11 FIFOs are used for storing the first 1024 points corresponding to 11 pipeline convolution results, and the other 11 FIFOs are used for storing the last 1024 points corresponding to 11 pipeline convolution results. The Fifo _ write module controls the convolution results to be stored in 3 sets of FIFOs in a sequential cycle at each time. After the data is stored in the FIFO, the FIFO _ write module controls the reading of 3 sets of 66 FIFOs, and the data read out inside each FIFO set is superimposed and output to the last superimposing module via dout. And finally superposing the results output by the 3 FIFO groups to obtain a final convolution result.
The technical effects are as follows:
the invention uses a high-performance FPGA processing board based on V7-690T of xilinx. The verilog code is generated by using a module built by a system generator, and the resource use condition obtained after the wiring is comprehensively laid out on the vivado is shown in fig. 11, so that the processing board meets the design requirement.
The baseband data input for the test is a sine wave with a frequency of 50MHZ and an amplitude of 2^15, and the system function is a single pulse. The system clock period is 200MHz, and two-way sampling is performed. The results of the convolution of the input signal with the system function through the system are shown in fig. 12, where the solid and dashed lines represent the results of the L and Q paths, respectively, after convolution. By observing that the output results of the IQ two paths are consistent with the expected results, the design successfully realizes the convolution between any long input signal and the 8192 point system function.
By observing the frequency domain oscillogram of the output result, as shown in fig. 13, the result is good, and the performance of the system is proved to meet the requirement.
The conventional convolution performs the convolution of 4096-point input signal and 8192-point system function, and performs zero padding operation when performing FFT transformation. A 4096 point input signal is followed by an 8192 point 0, and an 8192 point input signal is followed by a 4096 point 0. And because the FFT module must be an exponential power of 2 to set the Transform Length, the input signal of 4096 points and the system function of 8192 points are both zeroed to 16384 points. 32918 cycles are required from the time the signal enters the FFT module to the time the first data comes out. The system clock is 200MHZ and the time required for this part is 164.59 us. With pipelined processing, the minimum time required for this portion is 16384 clock cycles, and the time required for this portion is 81.92 us.
And by adopting a segmented convolution method, the input signal and the system function are divided into 1024-point segments, and FFT conversion is performed between the segments in parallel. 4221 cycles are required from the signal entering the FFT module to the first data coming out. At a system clock of 200MHZ, the required time is 21.105 us. With the pipeline processing method, the minimum time required to execute this portion is 2048 clock cycles, which is 10.24 us.
The segmented convolution adopts pipeline processing, and other parts can complete respective functions within 30 us. The system can realize convolution between any long input signal and 8192 point system function (namely ensuring that the convolution between 4096 points and 8192 points can be completed within every 30us under a running state).
TABLE 1FFT transform required time comparison
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. A parallel convolution method for radar signal processing, comprising:
carrying out segmented storage on the input signals with any length and the system function; the input signal is a radar excitation signal, and the system function is a target response function of the radar excitation signal;
respectively carrying out fast Fourier transform on the input signals and the system functions after the segmented storage;
performing complex multiplication and inverse fast Fourier transform on the input signal after fast Fourier transform and a system function to obtain a multi-section convolution result;
and sequentially superposing the multiple sections of convolution structures according to a set rule and a time sequence to obtain a final convolution result.
2. The parallel convolution method for radar signal processing according to claim 1, wherein the input signal is divided into 4 segments and the system function is divided into 8 segments.
3. The parallel convolution method for radar signal processing according to claim 1, wherein the fast fourier transform is performed in a 12-pipeline parallel manner, wherein 4 pipelines are input, and 8 pipelines are input in the system function.
4. The parallel convolution method for radar signal processing according to claim 1, wherein the complex multiplication and inverse fast fourier transform are performed in 32 pipeline parallel.
5. A parallel convolution device for radar signal processing, comprising:
the first segmented storage module is used for carrying out segmented storage on the input signal; the input signal is a radar excitation signal;
the second segment storage module is used for carrying out segment storage on the system function; the system function is a target response function of the radar excitation signal;
the first FFT calculation module is connected with the first segmentation storage module and used for carrying out fast Fourier transform on the segmented input signals;
the second FFT calculation module is connected with the second segmented storage module and is used for carrying out fast Fourier transform on the segmented system function;
the complex multiplication and IFFT calculation module is connected with the first FFT calculation module and the second FFT calculation module and is used for carrying out complex multiplication and inverse fast Fourier transform on the input signal after fast Fourier transform and a system function to obtain a multi-section convolution result;
and the overlap-add module is connected with the complex multiplication and IFFT calculation module and is used for sequentially overlapping the multi-section convolution structures according to a set rule and a time sequence to obtain a final convolution result.
6. The parallel convolution device applied to radar signal processing of claim 5, wherein the first segment storage module comprises:
a first segmentation unit for segmenting the input signal;
a first storage unit for storing the segmented input signal;
the second segmented storage module comprises:
the second segmentation unit is used for segmenting the system function;
and the second storage unit is used for storing the segmented system function.
7. The parallel convolution device for radar signal processing according to claim 5, wherein the first FFT calculation module adopts 4 parallel pipelines; the second FFT computation module adopts 8 parallel pipelines.
8. The parallel convolution device applied to radar signal processing according to claim 5, wherein the complex multiplication and IFFT calculation module adopts 32 parallel pipelines.
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