CN201886472U - Variable-length fast Fourier transform circuit - Google Patents
Variable-length fast Fourier transform circuit Download PDFInfo
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- CN201886472U CN201886472U CN2010205977782U CN201020597778U CN201886472U CN 201886472 U CN201886472 U CN 201886472U CN 2010205977782 U CN2010205977782 U CN 2010205977782U CN 201020597778 U CN201020597778 U CN 201020597778U CN 201886472 U CN201886472 U CN 201886472U
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Abstract
The utility model discloses a variable-length fast Fourier transform circuit, which is used for fast Fourier transform of a variable-length sequence point. The circuit comprises a mixed base operation module, a base combination selection module and a control module, wherein the mixed base operation module comprises a plurality of base operation units with different base numbers; the base combination selection module selects the combination of the base operation units according to the points of the sequence to be calculated; and the control module carries out fast Fourier transform for the sequence point by the selected base operation unit. The base operation units adopted in the fast Fourier transform circuit is variable and optional, i.e. the mixed base is adopted for the fast Fourier transform of 2n points, and a fast Fourier transform circuit with high speed and low time delay is realized by relatively lower hardware cost. The fast Fourier transform circuit has extremely high flexibility, and fast Fourier transform (FFT) operation with variable length can be carried out.
Description
[technical field]
The utility model relates to digital processing field, particularly a kind of variable length fast Fourier transform circuit.
[background technology]
Fourier transform is a kind of with the variation of signal from the time domain to the frequency domain, is a kind of important analysis tool in the fields such as acoustics, image, telecommunications and signal Processing.Wherein, discrete Fourier transform (DFT) (discreteFourier transform, DFT) especially one of indispensable instrument of digital processing field, particularly fast fourier transform (fast Fourier transform, appearance FFT) makes that DFT has obtained widely using.Adopt fft algorithm that the required multiplication number of times of COMPUTER CALCULATION DFT is greatly reduced, counting of the sequence of points that particularly is transformed is many more, and the saving of fft algorithm calculated amount is just remarkable more.
More detailed, be the sequence X (n) that N is ordered for length, wherein n gets 0 to N-1 integer, and its discrete Fourier transformation formula is:
Wherein
Obviously, employing formula 1 is carried out the DFT computing and is obtained X (k), needs N
2Subsequence point x (n) and corresponding twiddle factor
Complex multiplication calculate, and the inferior complex addition of N (N-1) calculates, when points N is big, this directly calculate the needed operand of DFT can be very big, and Fast Fourier Transform (FFT) is by utilizing twiddle factor
Periodicity and the symmetry method that adopts " dividing and rule " effect that reached effective minimizing operand.
For length is the sequence X (n) that N is ordered, if N wherein can be broken down into the product of two integers, promptly
N=LM, formula 2
Here suppose that N is not that prime number is too strict, because can satisfy formula 2 by any sequence being added zero, Fast Fourier Transform (FFT) this moment can recursively be decomposed into N point DFT the DFT that L point DFT and M order and calculate.Can be with reference to figure 1, the synoptic diagram when it shows the DFT employing FFT calculating of in the prior art N=15 being ordered.Because N=5*3=15, i.e. L=5 and M=3.This fft algorithm step is as follows:
N=r
1r
2…r
v
Thereby the DFT of a N point sequence will be broken down into many littler DFT, thereby produces the algorithm of more effective calculating DFT.In the application of reality, all be to utilize a fft circuit or fft processor to carry out the calculating that Fast Fourier Transform (FFT) realizes described discrete Fourier transformation separately usually.Since 2 DFT be the most basic also be to be realized the easiliest by hardware, be so-called basic 2 butterfly processing elements, so a lot of fft circuits or fft processor all are to adopt basic 2 butterfly processing elements to finish Fast Fourier Transform (FFT) as the core of Base computing unit, promptly this class fft circuit or fft processor adopt the DFT that is decomposed into to calculate at a lot of 2 to the DFT of a N point sequence.Similarly, also have basic 4FFT circuit or fft processor, basic 8FFT circuit or fft processor even adopt the fft circuit or the fft processor of basic 16 butterfly processing elements, basic 32 butterfly processing elements.
Obviously, when the radix of the Base computing unit that fft circuit or fft processor adopt is high more, help improving arithmetic speed more and operand is more little, but high more to requirement soft, hardware simultaneously.On the other hand, though fft circuit or processor can adopt base-2FFT computing, base-4FFT computing, base-8FFT computing or even base-16FFT computing or the like, but a common fft circuit or processor only use a kind of Base computing unit of fixed basic number, are that 2 Base computing unit or radix are 4 Base computing unit as radix.Sort circuit can only carry out the FFT conversion for the sequence of points of the integral number power of fixed basic number to counting, and has very big limitation.That is to say that adopting radix is that the base-4FFT circuit or the fft processor of 4 Base computing unit can only be 4 to counting
LSequence of points calculate, and can not be 2 to counting
LThe all sequences point calculate; Adopting radix is that the base-8FFT of 8 Base computing unit can only be 8 to counting
LSequence of points calculate, and can not be 2 to counting
LPerhaps 4
LThe all sequences point calculate.That is to say the restriction of having counted of these fft circuits or fft processor, can not satisfy the application under the certain situation the sequence of points that can handle.
Therefore, be necessary to propose a kind of new technical scheme and solve above-mentioned shortcoming.
[utility model content]
The purpose of this part is to summarize some aspects of embodiment of the present utility model and briefly introduces some preferred embodiments.In this part and the application's specification digest and utility model title, may do a little simplification or omit avoiding the making purpose of this part, specification digest and utility model title fuzzy, and this simplification or omit and can not be used to limit scope of the present utility model.
A purpose of the present utility model is to provide a kind of new fast Fourier transform circuit.
In order to reach the purpose of this utility model, the utility model provides a kind of fast Fourier transform circuit, is used for the fast fourier transform of variable length sequence of points, and described circuit comprises: the mixed base computing module comprises several not homoimerous Base computing unit; Base combination selection module is selected the combination of Base computing unit according to counting of sequence to be calculated; Control module utilizes the combination of the Base computing unit of selecting that sequence of points is carried out fast fourier transform.
Further, the radix of described Base computing unit is 2
n, wherein n is the integer greater than 0, the radix of each Base computing unit is all different.
Further, the radix of the Base computing unit in the combination of described Base computing unit is long-pending to equal counting of sequence to be calculated, and the number of the Base computing unit in the combination of described Base computing unit is minimum.
Further, the combination of described Base computing unit comprises the combination of different Base computings unit and the repetition of same Base computing unit.
Further, the Base computing unit of the high radix in the described mixed base computing module is realized by the Base computing unit iteration of low radix.
Further, described Base computing unit comprises butterfly processing element and twiddle factor unit.
Further, described mixed base computing module comprises that radix is that 2 Base computing unit, radix are that 4 Base computing unit and radix are 8 Base computing unit.
Further, described basic combination selection module comprises some grades of decision circuitry, each grade decision circuitry comprise first or the door and second or, wherein first or door receive the 3m-2 position and the 3m-1 position of described binary representation of counting, wherein second or door receive the 3m-1 position and the 3m position of described binary representation of counting, wherein m is the progression of this grade decision circuitry, and m is the integer greater than 0.
Further, when first or door be output as 1, the second or door be output as at 0 o'clock, it is 2 Base computing unit that this grade decision circuitry is selected radix; When first or door be output as 1 and second or the output of door when also being 1, it is 4 Base computing unit that this grade decision circuitry is selected radix; When first or the door be output as 0, second or the door be output as at 1 o'clock, this grade decision circuitry selection radix is 8 Base computing unit, when first or door be output as 0 and second or the output of door when also being 0, this grade decision circuitry is selected radix to be 8 Base computing unit and to enter the next stage decision circuitry and continue to select.
Compared with prior art, the Base computing unit that is adopted in the utility model is variable with selectable, promptly utilizes mixed base to carry out 2
nThe fast fourier transform of point utilizes relatively low hardware cost to realize the fast Fourier transform circuit of high speed low delay.This fast Fourier transform circuit has great dirigibility, can carry out the FFT computing of variable-length.
[description of drawings]
In conjunction with reaching ensuing detailed description with reference to the accompanying drawings, the utility model will be more readily understood, the structure member that wherein same Reference numeral is corresponding same, wherein:
Synoptic diagram when Fig. 1 is the DFT employing FFT calculating of in the prior art N=15 being ordered;
Fig. 2 is the block diagram of the variable length fast Fourier transform circuit among the embodiment of the present utility model;
Fig. 3 is the structural representation of the variable length fast Fourier transform circuit among the embodiment in the utility model;
Fig. 4 is the structural representation of the decision circuitry among the embodiment in the utility model; With
Fig. 5 selects the result schematic diagram of basic combined information for decision circuitry among the embodiment in the utility model.
[embodiment]
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, the utility model is described in further detail below in conjunction with the drawings and specific embodiments.
Fast Fourier transform circuit in the utility model has comprised alternative not homoimerous Base computing unit, with corresponding basic combination selection module, thereby changed the traditional pattern that can only carry out fast fourier transform to the sequence of points of fixedly counting, can select the best or preferable Base computing unit combination to carry out Fast Fourier Transform (FFT) fast and efficiently to the sequence of points of different length and calculate.
Please refer to Fig. 2, it shows the block diagram of the variable length fast Fourier transform circuit 200 among the embodiment of the present utility model.Described variable length fast Fourier transform circuit 200 can calculate arbitrary N=2 of counting quickly and efficiently
nThe DFT of sequence, wherein n is the integer greater than 0.Described variable length fast Fourier transform circuit 200 comprises mixed base computing module 202, basic combination selection module 204 and control module 206.
Mixed base computing module 202 comprises several not homoimerous Base computing unit, such as the first Base computing unit, the second Base computing unit ..., the 5th Base computing unit or the like.The radix of described Base computing unit is 2
n, wherein n is the integer greater than 0, the radix of each Base computing unit is all different.For example in one embodiment, described mixed base computing module 202 comprises that radix is that 2 Base computing unit, radix are that 4 Base computing unit and radix are 8 Base computing unit.In another embodiment, described mixed base computing module 202 comprises that radix is that 2 Base computing unit, radix are that 4 Base computing unit and radix are 16 Base computing unit.In another embodiment, described mixed base computing module 202 comprises that radix is that 2 Base computing unit and radix are 4 Base computing unit.In a word, there is not homoimerous Base computing unit available in the described mixed base computing module 202.
The combination that base combination selection module 204 is selected best or preferable Base computing unit according to counting of sequence to be calculated comes sequence to be calculated is calculated DFT.Described sequence number to be calculated can be any one number among the 2n, and wherein n is the integer greater than 0.Because counting of sequence to be calculated is indefinite, calculate so need in actual computation, select quick, the most rational Base computing unit combination to come that sequence to be calculated is carried out DFT as far as possible.Specifically, be the sequence of N, select best or preferable base combination to make for to be calculated counting:
N=a
1a
2…a
v
A wherein
1, a
2... a
vValue equal the radix of the Base computing unit that comprises in the described mixed base computing module 202, especially, a
1, a
2... a
vThe higher radix of preferential selection.That is to say that the radix of the Base computing unit in the described Base computing unit combination is long-pending to equal counting of sequence to be calculated, and the number of the Base computing unit in the combination of described Base computing unit is minimum.If for example mixed base computing module 202 comprises that radix is that 2 Base computing unit and radix are 4 Base computing unit, and counting of sequence to be calculated is 16, though N=16=2*2*2*2=4*2*2=4*4, but for the high efficiency of calculating, it is that 16 DFT recursively is decomposed into 4 DFT and 4 DFT calculate that the mode of preferentially selecting N=16=4*4 is counted sequence.Also such as mixed base computing module 202 comprises radix is that 2 Base computing unit, radix are that 4 Base computing unit and radix are 8 Base computing unit, and sequence number to be calculated is 256, though N=256=8*8*4=8*4*4*2=4*4*4*4=2*2*2*2*2*2*2*2, but for the high efficiency of calculating, it is that the DFT that 256 DFT recursively is decomposed into 8 DFT, 8 DFT and at 4 calculates that the mode of preferentially selecting N=256=8*8*4 is counted sequence.
In sum, described variable length fast Fourier transform circuit 200 is by adopting not homoimerous Base computing unit, and select the combination of best or preferable Base computing unit to carry out Fast Fourier Transform (FFT) in conjunction with basic combination selection module and calculate, because the combination of concrete base is according to the real-time calculation and analysis of counting of sequence to be calculated, so characteristics of the present utility model are to calculate the DFT of the sequence of variable length point, and the DFT that is not limited to the sequence of fixedly counting calculates; Another characteristics are to utilize relatively low hardware cost to realize the fast Fourier transform circuit of high speed low delay.
Please refer to Fig. 3, it shows the block diagram of the variable length fast Fourier transform circuit 300 among the embodiment of the present utility model.Described variable length fast Fourier transform circuit 300 can realize 2
nThe fast fourier transform of point, wherein n is greater than 0 and less than all integers of 13.Described variable length fast Fourier transform circuit 300 comprises mixed base computing module 320, basic combination selection module 340 and control module 360.
Described mixed base computing module 320 comprises basic 2 Base computing unit 322, basic 4 Base computing unit 324 and basic 8 Base computing unit 326.Described basic 2 Base computing unit 322 comprise that the radix of series connection is 2 butterfly processing element and twiddle factor unit; Described basic 4 Base computing unit 324 comprise that the radix of series connection is 4 butterfly processing element and twiddle factor unit; Described basic 8 Base computing unit 326 comprise that the radix of series connection is 8 butterfly processing element and twiddle factor unit.
Described basic combination selection module 340 comprises decision circuitry, and this decision circuitry receives counting of sequence to be calculated, selects the basic combined information that is applicable to this sequence in other words according to this judgement of counting then.At first should be noted that characteristics, because described counting is 2
n, after it is converted to a binary number, have only one be 1 remaining be 0 entirely.In the present embodiment because n is greater than 0 and less than all integers of 13, so described binary representation of counting comprises 13, promptly the 0th, the 1st, the 2nd ..., the 12nd.Because the 0th is 1 o'clock, described binary number is that odd number is not 2
nSo, temporarily do not consider the 0th situation.Described decision circuitry can be with reference to figure 4, and it shows the structure principle chart of the decision circuitry 400 among the embodiment of the present utility model.Described decision circuitry 400 comprises first order decision circuitry 410, second level decision circuitry 420, third level decision circuitry 430 and fourth stage decision circuitry 440, described first order decision circuitry 410 according to described count the 1st, select the Base computing unit for 2 and 3, described second level decision circuitry 420 according to described count the 4th, select the Base computing unit for 5 and 6, described third level decision circuitry 430 according to described count the 7th, select the Base computing unit for 8 and 9, described fourth stage decision circuitry 440 according to described count the 10th, select the Base computing unit for 11 and 12
Described first order decision circuitry 410 comprise first or the door 412 and second or the door 414, described first or door two input ends of 412 receive described the 1st of counting and the 2nd respectively, two input ends of described second or 414 receive described the 2nd of counting and the 3rd respectively.When described first or door 412 be output as 1, described second or door 414 be output as at 0 o'clock, can judge described the 1st of counting is 1, also is that described counting is 2, then selecting radix this moment is that 2 Base computing unit calculates; When described first or door 412 be output as 1, described second or the output of door 414 also be 1 o'clock, can judge described the 2nd of counting is 1, also is that described counting is 4, then selecting radix this moment is that 4 Base computing unit calculates; When described first or door 412 be output as 0, described second or door 414 be output as at 1 o'clock, can judge described the 3rd of counting is 1, also is that described counting is 8, then selecting radix this moment is that 8 Base computing unit calculates; When described first or door 412 be output as 0, described second or door 414 output also be 0 o'clock, can judge described front three of counting all is 0, also is described counting greater than 8, and then selecting radix this moment is that 8 Base computing unit calculates and enters the next stage decision circuitry simultaneously.
Described second level decision circuitry 420 comprise the 3rd or the door 422 and the 4th or the door 424, the described the 3rd or door two input ends of 422 receive described the 4th of counting and the 5th respectively, two input ends of the described the 4th or 424 receive described the 5th of counting and the 6th respectively.When the described the 3rd or door 422 be output as 1, the described the 4th or door 424 be output as at 0 o'clock, can judge described the 4th of counting is 1, also be that described counting is 16, then selecting radix this moment is that 2 Base computing unit calculates, because it is 8 Base computing unit that first order decision circuitry 410 has been selected radix, so count when being 16 when described, the base combination that decision circuitry is selected meets N=16=8*2; When the described the 3rd or door 422 be output as 1, the described the 4th or door 424 output also be 1 o'clock, can judge described the 5th of counting is 1, also be that described counting is 32, then selecting radix this moment is that 4 Base computing unit calculates, because it is 8 Base computing unit that first order decision circuitry 410 has been selected radix, so count when being 32 when described, the base combination that decision circuitry is selected meets N=32=8*4; When the described the 3rd or door 422 be output as 0, the described the 4th or door 424 be output as at 1 o'clock, can judge described the 6th of counting is 1, also be that described counting is 64, then selecting radix this moment is 8 Base computing unit, because it is 8 Base computing unit that first order decision circuitry 410 has been selected radix, so count when being 64 when described, the base combination that decision circuitry is selected meets N=64=8*8; When the described the 3rd or door 422 be output as 0, the described the 4th or the output of door 424 also be 0 o'clock, can judge described counting greater than 64, then selecting radix this moment is 8 Base computing unit, and enters the next stage decision circuitry.
Described third level decision circuitry 430 comprise the 5th or door 432 and the 6th or two input ends of door the 434, the described the 5th or door 432 receive described the 7th of counting and the 8th, the described the 6th or two input ends described the 8th of counting of reception of door 434 and the 9th.When the described the 5th or door 432 be output as 1, the described the 6th or door 434 be output as at 0 o'clock, can judge described the 7th of counting is 1, also be that described counting is 128, then selecting radix this moment is 2 Base computing unit, because it is 8 Base computing unit that first order decision circuitry 410 and second level decision circuitry 420 have all been selected radix, so count when being 128 when described, the base combination that decision circuitry is selected meets N=128=8*8*2; When the described the 5th or door 432 be output as 1, the described the 6th or door 434 output also be 1 o'clock, can judge described the 8th of counting is 1, also be that described counting is 256, then selecting radix this moment is 4 Base computing unit, because it is 8 Base computing unit that first order decision circuitry 410 and second level decision circuitry 420 have all been selected radix, so count when being 256 when described, the base combination that decision circuitry is selected meets N=256=8*8*4; When the described the 5th or door 432 be output as 0, the described the 6th or door 434 output also be 1 o'clock, can judge described the 9th of counting is 1, also be that described counting is 512, then selecting radix this moment is 8 Base computing unit, because it is 8 Base computing unit that first order decision circuitry 410 and second level decision circuitry 420 have all been selected radix, so count when being 512 when described, the base combination that decision circuitry is selected meets N=512=8*8*8; When the described the 5th or door 432 be output as 0, the described the 4th or the output of door 434 also be 0 o'clock, can judge described counting greater than 512, then selecting radix this moment is 8 Base computing unit, and enters the next stage decision circuitry.
Described fourth stage decision circuitry 440 comprise the 7th or door 442 and the 8th or door the 444, the described the 7th or door 442 inputs count the 10th and the 11st, the described the 8th or door 444 import the 11st and the 12nd that counts.When the described the 7th or door 442 be output as 1, the described the 8th or door 444 be output as at 0 o'clock, can judge described the 10th of counting is 1, also be that described counting is 1024, then selecting radix this moment is 2 Base computing unit, because it is 8 Base computing unit that first order decision circuitry 410, second level decision circuitry 420 and third level decision circuitry 430 have all been selected radix, so count when being 1024 when described, the base combination that decision circuitry is selected meets N=1024=8*8*8*2; When the described the 7th or door 442 be output as 1, the described the 8th or door 444 output also be 1 o'clock, can judge described the 11st of counting is 1, also be that described counting is 2048, then selecting radix this moment is 4 Base computing unit, because it is 8 Base computing unit that first order decision circuitry 410, second level decision circuitry 420 and third level decision circuitry 430 have all been selected radix, so count when being 2048 when described, the base combination that decision circuitry is selected meets N=2048=8*8*8*4; When the described the 7th or door 442 be output as 0, the described the 8th or door 444 be output as at 1 o'clock, can judge described the 12nd of counting is 1, also be that described counting is 4086, then selecting radix this moment is 8 Base computing unit, because it is 8 Base computing unit that first order decision circuitry 410, second level decision circuitry 420 and third level decision circuitry 430 have all been selected radix, so count when being 4086 when described, the base combination that decision circuitry is selected meets N=4086=8*8*8*8.
Will be appreciated that described decision circuitry can also continue to increase level V decision circuitry, the 6th grade of decision circuitry or the like, so that can calculate the more DFT of the sequence of multiple spot number.Also can increase described the 0th the detection of counting, when being 1 for the 0th, be considered as error handling processing.For different embodiment, the Base computing unit that described mixed base computing module comprises is not necessarily identical, and corresponding decision circuitry is also inequality.In certain embodiments, the Base computing unit further of the high radix in the described mixed base computing module realizes by the Base computing unit iteration of low radix, is that 16 Base computing unit can be that 2,4 and 8 Base computing unit is realized by radix as radix.Fig. 5 shows the basic combined information of the sequence selection that described decision circuitry 400 counts for difference simultaneously, so that understand the principle of work of described decision circuitry 400 more legibly.Wherein Y1, Y2, Y3, Y4, Y5, Y6, Y7 and Y8 respectively corresponding first or door 412, second or door 414, the 3rd or door 422, the 4th or door 424, the 5th or door 432, the 6th or door 434, the 7th or door 442 and the 8th or the output of door 444.
Above-mentioned explanation has fully disclosed embodiment of the present utility model.It is pointed out that and be familiar with the scope that any change that the person skilled in art does embodiment of the present utility model does not all break away from claims of the present utility model.Correspondingly, the scope of claim of the present utility model also is not limited only to described embodiment.
Claims (2)
1. fast Fourier transform circuit is used for the fast fourier transform of variable length sequence of points, it is characterized in that it comprises:
The mixed base computing module comprises several not homoimerous Base computing unit;
Base combination selection module is selected the combination of Base computing unit according to counting of sequence to be calculated;
Control module utilizes the combination of the Base computing unit of selecting that sequence of points is carried out fast fourier transform.
2. circuit according to claim 1, it is characterized in that, described basic combination selection module comprises some grades of decision circuitry, each grade decision circuitry comprise first or the door and second or, wherein first or door receive the 3m-2 position and the 3m-1 position of described binary representation of counting, wherein second or door receive the 3m-1 position and the 3m position of described binary representation of counting, wherein m is the progression of this grade decision circuitry, m is the integer greater than 0.
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