CN104967428A - Frequency domain implementation method of high-speed high-order FIR filter used for FPGA - Google Patents

Abstract

The invention discloses a frequency domain implementation method of a high-speed high-order FIR filter used for FPGA. When convolution operation is processed by utilization of a frequency domain, the problem that data cannot be processed in real time caused by zero filing time consumption is solved, an original conventional scheme of processing a sequence by utilization of one FFT IP is changed to a scheme of operating inputted data by utilization of two FFT IPs. Two FFTs output sectional convolution data respectively, and the difference of the later convolution and the previous convolution is just N clocks. Because the length of the sectional convolution is 2N, the previous N data and the previous sectional convolution are added, and the later N data and the later sectional convolution are added. Thus superfluous time-delay is not needed during overlap addition, a convolution result can be obtained, and therefore signal in-real processing is achieved. The provided frequency domain implementation method can lower FPGA resource consumption, can eliminate zero filling delay phenomena in the prior art, raises the processing speed, and can achieve real-time processing.

Description

For the frequency domain implementation method of the high-order and high-speed FIR filter of FPGA

Technical field

The present invention relates to discrete signal processing technical field, particularly a kind of frequency domain implementation method of the high-order and high-speed FIR filter for FPGA.

Background technology

In digital information processing system, FIR (Finite Impulse Response) filter is the most basic unit.The linear phase-frequency characteristic strict due to it and stable system, FIR becomes the Main Means of many fields deal with data.Along with the development of electronic technology, signal sampling frequency improves constantly, under high-speed sampling, the FIR filter based on multiplier architecture and the FIR filter based on distributed algorithm process in real time although can carry out streamline fast in FPGA, but the similar FIR filter of picture pulse compression technique, its exponent number is thousands of, too large to FPGA resource consumption.

Fast fourier transform (FFT) a kind ofly can realize this high order FIR filter and the relatively little method of consumption of natural resource.Fourier transform method design principle is as follows:

The essence of FIR filter is exactly the linear convolution of finite length sequence and Infinite Sequences, and linear convolution frequency-domain expression is:

y(n)＝x(n)*h(n)＝IFFT{FFT[x(n)]×FFT[h(n)]}

Wherein, * represents Discrete Linear convolution relation, and y (n) is output sequence, and x (n) is list entries, and h (n) is filter impulse response.FFT method realizes convolution flow chart as Fig. 1: for M-1 individual 0 and N-1 individual 0 is mended in the list entries of length N and the impulse response of length M respectively, length is all mended into L=M+N-1, thus isometric with convolution output sequence (length is the sequence length that the sequence convolution of M and N exports is M+N-1).Then be the list entries of L and impulse response to length after zero padding to do FFT computing respectively and forward frequency domain to, then list entries be multiplied with the frequency spectrum of impulse response, then do IFFT computing (inverse transformation) and just can obtain the long convolution results for L.In actual applications, sequence x (n) length is very long, and being FFT and IFFT needs very large counting, and hardware resource is limited, can not carry out FFT to long data.So generally data x (n) is segmented into the limited long sub-sequence collection x that multiple length is N ^m(k), so x (n) can be expressed as:

$x\left(n\right)=\underset{m=0}{\overset{\mathrm{\∞}}{\Σ}}{x}^m(n-mN)$

Wherein,

$x^m\left(k\right)=\left\{\begin{array}{c}x(k+mN),0\≤k\≤N-1\\ 0,N\≤k\≤M+N-2\end{array}\right.$

Be obtain sequences h after impulse response h (n) zero padding of M by length ₁(n)

$h_1\left(n\right)=\left\{\begin{array}{c}h\left(n\right),0\≤n\≤M-1\\ 0,M\≤n\≤M+N-2\end{array}\right.$

So the linear convolution of sequence x (n) and sequences h (n) is:

$y\left(n\right)=x\left(n\right)*h\left(n\right)=\underset{l=0}{\overset{M-1}{\Σ}}h\left(l\right)x(n-1)=\underset{m=0}{\overset{\mathrm{\∞}}{\Σ}}{y}_m(n-mN)$

Wherein, y _m(k)=h ₁(k) * x ^m(k).Required linear convolution divide into a unlimited length be the short length linear convolution of N+M-1 and, y _m(k) and y _m+1m-1 the sample overlap that a scope is mN≤n≤mN+M-2 is had between (k).

Obviously, the consumption of FPGA resource significantly can be reduced based on the FFT method of above-mentioned principle.But zero padding part expends time on the one hand, reduce processing speed, form time delay interval on the other hand, cause data to process in real time.This makes to reduce resource consumption and improve processing speed to be difficult to get both.

Summary of the invention

In order to solve the problem, the object of the present invention is to provide a kind of frequency domain implementation method of the high-order and high-speed FIR filter for FPGA, existing FFT method is improved, the problem that gets both is difficult to solve to reduce FPGA resource consumption and improve processing speed, that is: the consumption to FPGA resource under one side reduction high-order high-speed case, improves processing speed on the other hand to realize real-time process.

Above-mentioned purpose is achieved by the following technical solution:

For a frequency domain implementation method for the high-order and high-speed FIR filter of FPGA, described method comprises:

Steps A: impulse response h (n) length determining FIR filter is M, it is the fragment sequence of N that the data sequence x (n) of input FIR filter is segmented into multiple length, what setting impulse response h (n) and fragment sequence carried out FFT counts as 2N, wherein, and N=2 ⁱ, i is positive integer; Make M=N+1, as M curtailment spot patch foot;

Step B: impact response h (n) carries out the FFT computing of counting as 2N obtains impulse response spectrum H (k), fragment sequence is divided into odd number section and even number section, the FFT computing that after utilizing ping-pong operation odd number section fragment sequence and even number section fragment sequence to be mended respectively N number of zero, input two FFTIP core carries out counting as 2N, obtain sequential differs N number of clock, length is 2N odd number section fragment sequence frequency spectrum and even number section fragment sequence frequency spectrum, then respectively odd number section fragment sequence frequency spectrum is multiplied with impulse response spectrum H (k) with even number section fragment sequence frequency spectrum;

Step C: the product of odd number section fragment sequence frequency spectrum and even number section fragment sequence frequency spectrum and impulse response spectrum H (k) is input to two IFFT IP kernels respectively, obtains the odd number section Convolution sums even number section convolution that length is 2N respectively;

Step D: odd number section convolution results and even number section convolution results are added, obtain the output signal of FIR filter.

Counting as the twice of each sequence segment length N of FFT and IFFT computing, exponent number is N+1; If exponent number does not meet, need exponent number zero-adding to N+1.

Further, in described step B, first by impulse response h (n) zero padding to 2N length, then carry out the FFT computing of counting as 2N.

Further, in described step B, count as the FFT operation result of 2N is deposited in RAM, RAM uses and writes mode of priority.Because impulse response is introduced into FFT module, so the data exported are introduced in two RAM, RAM uses WriteMode, and the data entered just can read without the need to having passed.

Further, in described step B, by the 1st, 3,5 ... individual fragment sequence enters the FFT computing that first FFT IP kernel carries out counting as 2N successively, by the 2nd, 4,6 ... individual fragment sequence enters the FFT computing that second FFT IP kernel carries out counting as 2N successively; 1st (length is N's) fragment sequence inputs and mend N number of 0 after first FFT IP, zero padding simultaneously, 2nd (length is N's) fragment sequence starts to input into second FFT IP, N number of 0 is mended after input, zero padding simultaneously, 3rd length is that the fragment sequence of N inputs into first FFT IP again and mends N number of 0, and so successively by odd number section fragment sequence and the input of even number section fragment sequence, the clock cycle of adjacent two fragment sequence differences is always N.

Beneficial effect of the present invention:

(1) the frequency domain implementation method of the high-order and high-speed FIR filter for FPGA provided by the invention can not only reduce FPGA resource consumption, can also eliminate zero padding delay phenomenon of the prior art, improve processing speed, can realize process in real time.

(2) the frequency domain implementation of FIR filter provided by the invention solves the problem of the resource consumption of high speed processing under high-order case, structure of optimizing hardware, and the coefficient of FIR filter is configurable.

Accompanying drawing explanation

Fig. 1: prior art frequency domain realizes the linear convolution flow chart of two sequences;

Fig. 2: the structure chart designing FIR filter in FPGA provided by the invention;

Fig. 3: the concrete sequential chart that the present invention is to provide input signal;

Fig. 4: the sequential chart of the output signal after sectional convolution provided by the invention;

Fig. 5: FFTIP core module schematic diagram used in the present invention.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with embodiment and accompanying drawing, real-time proposals of the present invention is further described in detail.

The invention provides a kind of frequency domain implementation method of the high-order and high-speed FIR filter for FPGA, the method is to when utilizing frequency domain process convolution algorithm, the data caused because zero padding is consuming time cannot process this problem in real time and improve, utilized the data of two FFTIP to input to carry out computing by originally utilizing the conventional scheme of a FFTIP process sequence to change into, sequence sequential as shown in Figure 3.The method is applicable to the system that coefficient is real integer or complex integers, is applicable to Ultra-High Order system, is applicable to pulse compression system, is applicable to the configurable system of coefficient.

Technical solutions according to the invention are set forth as platform below using XILINX company FPGA.

The essence of FIR filter is exactly the linear convolution of finite length sequence and Infinite Sequences, that is:

y(n)＝x(n)*h(n)＝IFFT{FFT[x(n)]×FFT[h(n)]}

To the convolution of Infinite Sequences, x (n) is segmented into the limited long sub-sequence collection x that multiple length is N ^mn () be convolution on frequency domain, wherein, impulse response h (n) length is M=N+1; x ^mn () and h (n) mend N and N-1 individual zero respectively to become two length are the sequence of 2N, carry out the FFT computing of 2N point, the value of computing is multiplied and carries out IFFT computing, obtains convolution results.Counting as the twice of each sequence segment length N of FFT and IFFT computing, exponent number is N+1; If exponent number does not meet, need exponent number zero-adding to N+1.The convolution results utilizing overlap-add method multiple length to be 2N is added.Integer N, N+1 and 2N are the parameters according to the design of FIR filter implementation method, and N is 2 ⁱ, i is positive integer.The present invention needs to use XILINXFFTIP core, and its pinouts as shown in Figure 5, first selects Pipelined, StreamingI/O pattern, and process is counted as 2N, makes the data that IP kernel can be long to 2N continuously carry out FFT operation.The port used mainly contains following:

Clk: clock port; XN_RE, XN_IM: the real part of input signal and imaginary part, when input signal is that XN_IM is input as 0 by real signal; START:FFT commencing signal, can carry out continuous print FFT to signal by control port.FWD_INV_WE, FWD_INV:FWD_INV_WE put 1, FWD_INV when being 1, and being FFT computing, when FWD_INV is 0, is IFFT computing; XK_RE, XK_IM: the complex result of output; XK_INDEX: output signal mark, represent that the FFT carried out at this exports the number of data, coefficient FFT module is using this signal as the address storing FFT value, and data FFT is as the address of reading RAM intermediate value.XN_INDEX: the mark of input data, represents that the FFT carried out at this inputs the number of data, for controlling the beginning of next FFT.

The frequency domain implementation method concrete grammar of the high-order and high-speed FIR filter for FPGA provided by the invention comprises the following steps, see Fig. 2 thus:

Step 1: the impulse response of high order FIR filter and the signal of data sequence, judges it is impulse response or data sequence by CoefOrSignal signal.During beginning, first CoefOrSignal signal is set high, coefficient start sets high a clock, the FFT module that input impulse response enters coefficient by clock carries out computing, when inputting number and arriving N+1, by clock zero padding, when reaching 2N length, coefficient end of input, the result of output is respectively stored in two RAM, and RAM uses and writes mode of priority.

Step 2: set low by CoefOrSignal signal, list entries x (n) is N segmentation by length, obtains odd number section fragment sequence x ₁(n) and even number section fragment sequence x ₂n (), with ping-pong operation respectively by sequence x ₁(n), x ₂n () is input in two FFTIP, wherein during a list entries signal, another zero padding, makes FFT IP treated length be always 2N; Specifically:

$x_1\left(n\right)=\underset{i=0}{\Σ}{x}^{2i}(n-2iN)$

$x_2\left(n\right)=\underset{i=0}{\Σ}{x}^{2i+1}(n-2iN)$

Wherein,

$x^{2i}\left(k\right)=\left\{\begin{array}{c}x(k+2iN),0\≤k\≤N-1\\ 0,N\≤k\≤2N-1\end{array}\right.$

$x^{2i+1}\left(k\right)=\left\{\begin{array}{c}x(k+2iN+N),0\≤k\≤N-1\\ 0,N\≤k\≤2N-1\end{array}\right.$

Start signal is set high a clock at the previous clock starting list entries by each FFT IP all the time, can be judged, can process in real time like this to Infinite Sequences by XN_INDEX signal.Sequential chart as shown in Figure 3.

Step 3: the result that 2 fragment sequence signal FFT are dealt by XK_INDEX as address, find the coefficient spectrum (i.e. impulse response frequency spectrum) in respective RAM respectively, be multiplied, then respectively by IFFT IP kernel, obtain sectional convolution sequences y ^m(n); Output timing as shown in Figure 4.Specifically be expressed as:

$y_1\left(n\right)=IFFT\{FFT\left(h\right(n\left)\right)\×FFT\left(x_1\right(n\left)\right)\}=\underset{i-0}{\overset{\mathrm{\∞}}{\Σ}}{y}^{2i}(n-2iN)$

$y_2\left(n\right)=IFFT\{FFT\left(h\right(n\left)\right)\×FFT\left(x_2\right(n\left)\right)\}=\underset{i-0}{\overset{\mathrm{\∞}}{\Σ}}{y}^{2i+1}(n-2iN-N)$

Step 4: according to overlap-add method, y ^m(n) and y ^m+1a scope is had to be that M-1 sample of mN≤n≤mN+M-2 is overlapping between (n), because N=M-1, so overlapping range is mN≤n≤mN+N-1, overlap length just exports the half of length for convolution, and it is just convolution result out that rear N number of value of so previous sequence is added with the top n value of a rear sequence.Be embodied in:

$y_1\left(n\right)+y_2\left(n\right)=\underset{i-0}{\overset{\mathrm{\∞}}{\Σ}}{y}^{2i+1}(n-2iN-N)+\underset{i-0}{\overset{\mathrm{\∞}}{\Σ}}{y}^{2i}(n-2iN)=\underset{i=0}{\overset{\mathrm{\∞}}{\Σ}}{y}_i(n-iN)=y\left(n\right)$

As can be seen from the above, the result of output is consistent with principle.

In actual applications, as long as determine the size of FIR filter exponent number N, other are all determined as parameters such as sequence segment length and FFT count, so increasing exponent number hardware configuration can not change.First can design by larger counting during design, even if exponent number is very little, also can be reached the parameter of designing requirement by zero padding.Coefficient can not only be changed flexibly like this, coefficient length can also be changed flexibly.

The frequency domain implementation method of FIR filter provided by the invention, solves the speed issue realizing FIR filter on Ultra-High Order frequency domain, has accomplished minimizing resource, and energy high speed processing, and can flexible configuration to FIR filter coefficient.The effect of above-described embodiment is essentiality content of the present invention is described, but does not limit protection scope of the present invention with this.Those of ordinary skill in the art should be appreciated that and can modify to technical scheme of the present invention or equivalent replacement, and does not depart from essence and the protection range of technical solution of the present invention.

Claims (4)

1. for a frequency domain implementation method for the high-order and high-speed FIR filter of FPGA, it is characterized in that, described method comprises:

Steps A: impulse response h (n) length determining FIR filter is M, it is the fragment sequence of N that the data sequence x (n) of input FIR filter is segmented into multiple length, what setting impulse response h (n) and fragment sequence carried out FFT counts as 2N, wherein, and N=2 ⁱ, i is positive integer; Make M=N+1, as M curtailment spot patch foot;

Step B: impact response h (n) carries out the FFT computing of counting as 2N obtains impulse response spectrum H (k), fragment sequence is divided into odd number section and even number section, the FFT computing that after utilizing ping-pong operation odd number section fragment sequence and even number section fragment sequence to be mended respectively N number of zero, input two FFT IP kernels carry out counting as 2N, obtain sequential differs N number of clock, length is 2N odd number section fragment sequence frequency spectrum and even number section fragment sequence frequency spectrum, then respectively odd number section fragment sequence frequency spectrum is multiplied with impulse response spectrum H (k) with even number section fragment sequence frequency spectrum;

Step C: the product of odd number section fragment sequence frequency spectrum and even number section fragment sequence frequency spectrum and impulse response spectrum H (k) is input to two IFFT IP kernels respectively, obtains the odd number section Convolution sums even number section convolution that length is 2N respectively;

Step D: odd number section convolution results and even number section convolution results are added, obtain the output signal of FIR filter.

2. the frequency domain implementation method of the high-order and high-speed FIR filter for FPGA according to claim 1, is characterized in that: in described step B, first by impulse response h (n) zero padding to 2N length, then carry out the FFT computing of counting as 2N.

3. the frequency domain implementation method of the high-order and high-speed FIR filter for FPGA according to claim 2, is characterized in that: in described step B, counts as the FFT operation result of 2N is deposited in RAM, and RAM uses and writes mode of priority.

4. the frequency domain implementation method of the high-order and high-speed FIR filter for FPGA according to claim 3, it is characterized in that: in described step B, by the 1st, 3,5 ... individual fragment sequence enters the FFT computing that first FFT IP kernel carries out counting as 2N successively, by the 2nd, 4,6 ... individual fragment sequence enters the FFT computing that second FFT IP kernel carries out counting as 2N successively; 1st fragment sequence inputs mends N number of 0 after first FFT IP, zero padding simultaneously, 2nd fragment sequence starts to input into second FFT IP, N number of 0 is mended after input, zero padding simultaneously, 3rd length is that the fragment sequence of N inputs into first FFT IP again and mends N number of 0, and so successively by odd number section fragment sequence and the input of even number section fragment sequence, the clock cycle of adjacent two fragment sequence differences is always N.