CN106936406A - A kind of realization of 5 parallel rapid finite impact response filter - Google Patents
A kind of realization of 5 parallel rapid finite impact response filter Download PDFInfo
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- CN106936406A CN106936406A CN201710151783.7A CN201710151783A CN106936406A CN 106936406 A CN106936406 A CN 106936406A CN 201710151783 A CN201710151783 A CN 201710151783A CN 106936406 A CN106936406 A CN 106936406A
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- 238000004891 communication Methods 0.000 abstract description 3
- 238000013527 convolutional neural network Methods 0.000 abstract 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
Abstract
The invention discloses a kind of 5 parallel rapid finite shock response (FIR) wave filters and its corresponding hardware structure.5 parallel quick FIR filters are the parallelizations for realizing FIR filter that tap coefficient is 5, while reducing computation complexity.It is of the invention first theoretically to have derived 5 parallel quick FIR filters algorithm (FFA), then according to 5 parallel FFA, design corresponding 5 parallel fast convolution hardware structures.Due to having reused the hardware cell in original filter, compared to 5 traditional tap FIR filters algorithms, under the conditions of identical throughput, this algorithm can simultaneously save 40% multiplication operation on the basis of some add operations are increased.And due to being realized in hardware, the area and power consumption of multiplier are much larger than adder, therefore this framework can save 40% area and power consumption.The present invention is used in needs the occasion of 5 parallel FIR filters, such as convolutional neural networks, Computer Vision, radio communication etc., can improve the effective throughput of original filter, or the power consumption for reducing original filter.
Description
Technical field
The present invention relates to integrated circuit and communication technical field, the realization of more particularly to a kind of 5 parallel quick FIR filters
Structure.
Background technology
One finite impulse response (FIR) of N taps (FIR) wave filter can be expressed as：
Wherein x (n) is an endless list entries, and h (n) is the coefficient of the FIR filter of N comprising length.Formula (1.1)
Can be write as in z domains：
One basic rank FIR filter structure of Direct-type 5 is as shown in figure 1, it is by data shift register, co-efficient multiplication
Device and the part of operand adder three constitute.For a 5 rank FIR filters, Direct-type structure needs 5 shift registers, 5
Individual multiplier and 4 adders.
Above-mentioned Direct-type structure can only export a result of calculation within each clock cycle, need high-speed data communication
With the occasion of high-throughput, Direct-type structure obviously can not meet demand, therefore parallelization is treated as a kind of important solution
Scheme.But in general, consumption hardware resource with degree of parallelism it is linearly increasing, under many design conditions, by parallel
The hardware spending that reason is brought is waste that is can not put up with and can causing resource.
The content of the invention
The present invention is for the FIR filter that tap coefficient is 5, it is proposed that a kind of 5 parallel output scheme, while can reduce
Computation complexity, improves throughput and reduces power consumption well.
Theory analysis of the invention is as follows：
List entries { x (0), x (1), x (2) ... } can be broken down into even number and odd number part, as shown in (1.3) formula：
Wherein X0And X1The z-transform of the x (2k+1) of respectively x (2k).Equally, filter coefficient H (z) of N length can be by
It is decomposed into：
H (z)=H0+z-1H1 (1.4)
So output sequence Y (z) is similarly expressed as even number and odd number part：
Wherein
Formula (1.6) is 2 parallel FIR algorithms, and 2 parallel quick FIR algorithms (FFA) can be become by the form for rewriting above formula
[11]：
This 2 parallel fast electric-wave filter includes 5 subfilters, X therein0H0And X1H1It is public keys, is calculating Y0With
Y1When can share.
The derivation quick FIR algorithm parallel with 2 of 5 parallel quick FIR algorithms is similar, first list entries and tap coefficient point
It is 5 parts to solve, and then exports and is also represented with 5 sub- output sequences：
Then (1.11) formula is rewritten into the form of 2 parallel FIR filters：
Y=(X0+z-1V)(H0+z-1W) (1.9)
Wherein V and W are respectively equal to：
V and W and middle entry VW are write again as the form of 2 parallel FIR filters, recursively call 2 parallel quick FIR to calculate
Method is iterated to calculate, and finally can be obtained by 5 parallel quick FIR algorithms.
For the convenience on expressing, we provide the matrix form of 5 parallel quick FFA：
Y5=Q5H5P5X5
Wherein P5And Q5Respectively pre-process and post-process matrix, H5It is the subfilter matrix of diagonalization.
Parallel quick FIR algorithm is substantially that a large-sized filter equalizer is filtered into the son of several small sizes
Device, each subfilter does short convolution operation respectively, then the short convolution results that each subfilter is obtained are by certain group
Close and be added, while calculating multiple outputs.Because the filter tap coefficients 5 in the present invention, if this wave filter point
If solution, 5 subfilters can only be broken down into, and the short convolution of each subfilter is then correspondingly degenerated to multiplication behaviour
Make.
The particular circuit configurations of inventive algorithm are as shown in Figure 2.Modules of the invention are as shown in figure 3, including input
Sampling module, 5 input datas are sent out for sampled data and simultaneously to preposition addition module；Preposition addition module, for inciting somebody to action
5 parallel input datas after sampling are grouped and are added up by certain rule；Co-efficient multiplication module, for will be pretreated
Filter tap coefficients are multiplied with the output data of preposition addition module；Rearmounted addition module, for by co-efficient multiplication module
Output data is transformed into the output result of traditional 5 tap FIR filters；Output module, for 5 output datas of parallel output.
The preposition addition module also includes 10 preposition adders, and the sampled data for that will be grouped is added.
The co-efficient multiplication module also includes 15 coefficient multipliers, for will be grouped it is cumulative after sampled data and in advance
The tap coefficient that packet transaction is crossed is corresponded and is multiplied.
The rearmounted addition module also includes 21 rearmounted adders, for the result of co-efficient multiplication module to be transformed into most
Whole output result；And 4 data registers, for the intermediate result that registered data is calculated, calculated for next round and used.
Brief description of the drawings
Fig. 1 is the rank FIR filter structure figure of Direct-type 5；
Fig. 2 is the physical circuit figure of 5 parallel quick FIR filters；
Fig. 3 is 5 parallel quick FIR filter modules schematic diagrames.
Specific embodiment
As shown in Fig. 2 input sample module is sampled input data, then successively continuous 5 input datas
x0, x1, x2, x3, x4Preposition accumulator module is sent into parallel；In preposition accumulator module, input sampling data x0, x1, x2, x3, x4Quilt
It is divided into 15 groups, every group is respectively x0, x1, x2, x3, x4, x0+x1, x1+x2, x2+x3, x3+x4, x0+x1+x2, x1+x2+x3, x2+x3+
x4, x0+x1+x2+x3, x1+x2+x3+x4, x0+x1+x2+x3+x4；In co-efficient multiplication module, above-mentioned each group of result respectively with advance
First good h0, h1..., h0+h1+h2+h3+h4It is multiplied, and result is sent into rearmounted adder Module；In rearmounted addition module
In, in data register deposit last round of calculating intermediate result participate in epicycle calculate in, and by epicycle calculate centre
Result is deposited, for use in the calculating of next round.In the output module, the parallel output 5 of output module one time output knot
Really.Calculating 5 output results with traditional rank FIR filter of Direct-type 5 needs 25 multiplication, 20 sub-additions, with this hair
The parallel quick FIR filter in bright 5 calculates 5 output results needs 15 sub-additions, 31 sub-additions.In being realized in hardware,
The area and power consumption of multiplier consumption are far longer than adder, therefore compared to traditional Direct-type FIR Filter, the present invention is situated between
The 5 parallel quick FIR filters for continuing can save 40% hardware resource.
Claims (4)
1. a kind of 5 parallel quick FIR filter, including：
Input sample module, 5 input datas are sent out for sampled data and simultaneously to preposition addition module；
Preposition addition module, is grouped and is added up for 5 parallel input datas after by sampling by certain rule；
Co-efficient multiplication module, for pretreated filter tap coefficients to be multiplied with the output data of preposition addition module；
Rearmounted addition module, the output knot for the output data of co-efficient multiplication module to be transformed into traditional 5 tap FIR filters
Really；
Output module, for 5 output datas of parallel output.
2. according to claim 15 parallel quick FIR filter, wherein, the preposition addition module also includes：
10 preposition adders, the sampled data for that will be grouped is added.
3. according to claim 15 parallel quick FIR filter, wherein, the co-efficient multiplication module also includes：
15 coefficient multipliers, for will be grouped it is cumulative after sampled data and a pair of the tap coefficient 1 crossed of advance packet transaction
Should be multiplied.
4. according to claim 15 parallel quick FIR filter, wherein, the rearmounted addition module also includes：
21 rearmounted adders, for the result of co-efficient multiplication module to be transformed into final output result；And
4 data registers, for the intermediate result that registered data is calculated, calculate for next round and use.
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Cited By (5)
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| CN107769755A (en) * | 2017-10-24 | 2018-03-06 | 中国科学院电子学研究所 | A kind of design method of parallel FIR decimation filters and parallel FIR decimation filters |
| CN107862381A (en) * | 2017-11-06 | 2018-03-30 | 南京大学 | A kind of FIR filter suitable for a variety of convolution patterns is realized |
| CN108108812A (en) * | 2017-12-20 | 2018-06-01 | 南京大学 | For the efficiently configurable convolutional calculation accelerator of convolutional neural networks |
| CN110138358A (en) * | 2019-04-30 | 2019-08-16 | 南京大学 | A kind of long linear phase limited impulse response digital filter of idol |
| CN112327111A (en) * | 2020-10-21 | 2021-02-05 | 南京信息职业技术学院 | Denoising method of partial discharge signal |
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| CN103093052A (en) * | 2013-01-25 | 2013-05-08 | 复旦大学 | Design method of low-power dissipation parallel finite impulse response (FIR) digital filter |
| CN103956991A (en) * | 2014-04-10 | 2014-07-30 | 北京遥测技术研究所 | FIR filter parallel realization method based on CPU/GPU heterogeneous platform |
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| CN103093052A (en) * | 2013-01-25 | 2013-05-08 | 复旦大学 | Design method of low-power dissipation parallel finite impulse response (FIR) digital filter |
| CN103956991A (en) * | 2014-04-10 | 2014-07-30 | 北京遥测技术研究所 | FIR filter parallel realization method based on CPU/GPU heterogeneous platform |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107769755A (en) * | 2017-10-24 | 2018-03-06 | 中国科学院电子学研究所 | A kind of design method of parallel FIR decimation filters and parallel FIR decimation filters |
| CN107862381A (en) * | 2017-11-06 | 2018-03-30 | 南京大学 | A kind of FIR filter suitable for a variety of convolution patterns is realized |
| CN108108812A (en) * | 2017-12-20 | 2018-06-01 | 南京大学 | For the efficiently configurable convolutional calculation accelerator of convolutional neural networks |
| CN108108812B (en) * | 2017-12-20 | 2021-12-03 | 南京风兴科技有限公司 | Efficient configurable convolution computation accelerator for convolutional neural networks |
| CN110138358A (en) * | 2019-04-30 | 2019-08-16 | 南京大学 | A kind of long linear phase limited impulse response digital filter of idol |
| CN112327111A (en) * | 2020-10-21 | 2021-02-05 | 南京信息职业技术学院 | Denoising method of partial discharge signal |
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