CN103093052A - Design method of low-power dissipation parallel finite impulse response (FIR) digital filter - Google Patents

Design method of low-power dissipation parallel finite impulse response (FIR) digital filter Download PDF

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CN103093052A
CN103093052A CN2013100278597A CN201310027859A CN103093052A CN 103093052 A CN103093052 A CN 103093052A CN 2013100278597 A CN2013100278597 A CN 2013100278597A CN 201310027859 A CN201310027859 A CN 201310027859A CN 103093052 A CN103093052 A CN 103093052A
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impulse response
finite impulse
subfilter
coefficient
transform
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李宁
刘珍奇
叶凡
代国宪
任俊彦
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Fudan University
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Abstract

The invention belongs to the technical field of digital integrated circuits, and particularly relates to a design method of a low-power dissipation parallel finite impulse response (FIR) digital filter. The method is used for parallel realization of two circuits and three circuits of the linear phase FIR digital filter, through a new polynomial decomposition method, all subfilters are enabled to have coefficient symmetry, and the subfilters achieve the needed number of multiplying units, and accordingly the number of the multiplying units can be reduced to be a half of an original number, the whole parallel structural filter achieve the needed number of multiplying units to be reduced to the half of the original number, and the corresponding cost is the increasing of summing units. Due to the fact that realization of the summing units is far easier than that of the multiplying units, the way that the summing units replace the multiplying units is worth. Compared with a traditional structure and an existing fast FIR algorithms (FFA) structure, the structure of the design method can save hardware resources and reduce power consumption of realization.

Description

A kind of method for designing of low power consumption parallel Finite Impulse Response filter
Technical field
The invention belongs to the digital integrated circuit field, be specifically related to a kind of method for designing of low power consumption parallel Finite Impulse Response filter.
Background technology
FIR (Finite Impulse Response) digital filter is one of basic element of character the most frequently used in digital information processing system, is widely used in the occasions such as radio communication, video and image processing.Some are used as video and image processing needs the FIR wave filter to be operated under high frequency clock, yet other application need the FIR wave filter to have high-throughput and low-power consumption as the mimo system in wireless mobile communications.Parallel processing technique can effectively improve throughput and reduce power consumption.Yet traditional parallel Finite Impulse Response filter is owing to taking more hardware resource and impracticable, the hardware implementation complexity that therefore the reduces parallel Finite Impulse Response filter study hotspot for over ten years that becomes history.
One 2 tunnel parallel FIR wave filter as shown in Figure 1.Traditional 2 road parallelism wave filters need 4 subfilters that length is N/2,2 aftertreatment totalizers, and 1 delay cell needs 2N multiplier and (2N-2) individual totalizer altogether.
One 3 tunnel parallel FIR wave filter as shown in Figure 2.Traditional 3 road parallelism wave filters need 9 subfilters that length is N/3,6 aftertreatment totalizers, and 3 delay cells need 3N multiplier and (3N-3) individual totalizer altogether.
At present, optimization method for Traditional parallel Finite Impulse Response filter project organization is mainly quick FIR algorithm (Fast FIR Algorithm, be called for short the FFA algorithm), the FIR algorithm is realized required subfilter number by adopting specific Polynomial Method to reduce on the basis of traditional algorithm fast, thereby reduces implementation complexity.On the basis of quick FIR algorithm, a lot of methods of further optimizing have also been produced.Such as utilizing the fast linear convolution, at first a long paper amasss and is broken down into some short convolution, and short convolution realizes with the fast linear convolution.Be that larger parallel filtering structure can be by the scale less cascade of parallel filtering structure or iterative construction.
Yet method for designing has in the past all adopted identical FFA filter structure, does not all consider the symmetry of linear phase FIR filter coefficient.When realizing serial FIR wave filter, utilize the symmetry of filter coefficient, can reduce the number of multipliers of half.This thought can be applied in the design of parallel FIR wave filter equally.Therefore tradition and existing algorithm still have the space of optimizing and promoting.
Summary of the invention
The object of the invention is to propose the method for designing of the area-optimized parallel Finite Impulse Response filter of a kind of low-power consumption.
The method for designing of a kind of low power consumption parallel Finite Impulse Response filter provided by the invention, concrete steps are as follows:
(1) determine the parallelism wave filter one-piece construction;
(2) determine the subfilter implementation structure;
(3) determine multiplier and totalizer implementation, obtain the low power consumption parallel Finite Impulse Response filter;
Wherein, during the described definite parallelism wave filter one-piece construction of step (1), utilize the coefficient symmetry of Linear phase FIR digital filter, adopt the Factoring Polynomials method to make whole subfilters have symmetry coefficient, reduce and realize required number of multipliers;
Consider the FIR wave filter of a N tap, can be expressed as:
Figure DEST_PATH_IMAGE001
(1)
{ x (n) } is the endless list entries, and { h (n) } is that length is the FIR filter coefficient of N, has symmetry (linear phase).Traditional parallel FIR wave filter in L road can be expressed as:
Figure 2013100278597100002DEST_PATH_IMAGE002
(2)
Wherein,
Figure DEST_PATH_IMAGE003
, ,
Figure DEST_PATH_IMAGE005
,
Wherein, p, q, r=0,1,2 ..., L-1.Can be found out by formula (2), the traditional parallel FIR wave filter in L road needs L2 subfilter, and the length of each subfilter is N/L.
Got by formula (2), the parallel FIR wave filter of tradition 2 tunnel can be expressed as:
Figure 2013100278597100002DEST_PATH_IMAGE006
Figure DEST_PATH_IMAGE007
（3）
Also namely:
Figure 2013100278597100002DEST_PATH_IMAGE008
Figure DEST_PATH_IMAGE009
（4）
Wherein,
Figure 2013100278597100002DEST_PATH_IMAGE010
It is the 1 road input signal sequence
Figure DEST_PATH_IMAGE011
Transform,
Figure 2013100278597100002DEST_PATH_IMAGE012
It is the 2 road input signal sequence
Figure DEST_PATH_IMAGE013
Transform,
Figure DEST_PATH_IMAGE014
It is the 1 road output signal sequence
Figure DEST_PATH_IMAGE015
Transform,
Figure DEST_PATH_IMAGE016
It is the 2 road output signal sequence
Figure DEST_PATH_IMAGE017
Transform,
Figure DEST_PATH_IMAGE018
Coefficient for subfilter 1
Figure DEST_PATH_IMAGE019
(
Figure DEST_PATH_IMAGE020
Impulse response for wave filter) transform also claims the transport function of subfilter 1.
Figure DEST_PATH_IMAGE021
Coefficient for subfilter 2
Figure DEST_PATH_IMAGE022
Transform, also claim the transport function of subfilter 2.
By formula (2), the parallel FIR wave filter of tradition 3 tunnel can be expressed as equally:
Figure DEST_PATH_IMAGE023
Figure DEST_PATH_IMAGE024
Figure DEST_PATH_IMAGE025
（5）
Wherein,
Figure 13566DEST_PATH_IMAGE010
It is the 1 road input signal sequence
Figure DEST_PATH_IMAGE026
Transform,
Figure 221825DEST_PATH_IMAGE012
It is the 2 road input signal sequence
Figure DEST_PATH_IMAGE027
Transform,
Figure DEST_PATH_IMAGE028
It is the 3 road input signal sequence
Figure DEST_PATH_IMAGE029
Transform,
Figure 472415DEST_PATH_IMAGE014
It is the 1 road output signal sequence
Figure DEST_PATH_IMAGE030
Transform,
Figure 107927DEST_PATH_IMAGE016
It is the 2 road output signal sequence
Figure DEST_PATH_IMAGE031
Transform,
Figure DEST_PATH_IMAGE032
It is the 3 road output signal sequence Transform,
Figure 751792DEST_PATH_IMAGE018
Coefficient for subfilter 5 (
Figure 13009DEST_PATH_IMAGE020
Impulse response for wave filter) transform also claims the transport function of subfilter 5.
Figure 494937DEST_PATH_IMAGE021
Coefficient for subfilter 6
Figure DEST_PATH_IMAGE035
Transform, also claim the transport function of subfilter 6.
Figure DEST_PATH_IMAGE036
Coefficient for subfilter 7
Figure DEST_PATH_IMAGE037
Transform, also claim the transport function of subfilter 7.
The present invention adopts the Factoring Polynomials method of proposition, and formula (4) can be rewritten as:
Figure DEST_PATH_IMAGE038
（6）
Figure DEST_PATH_IMAGE039
Wherein, identical in every symbolic significance and formula (4).
According to formula (6), the novel 2 tunnel parallel Finite Impulse Response filter structures that the present invention proposes as shown in Figure 3.X(2k) and x(2k+1) be input, y(2k) and y(2k+1) be output.
Structure of the present invention needs 4 subfilters that length is N/2.Subfilter
Figure DEST_PATH_IMAGE040
With
Figure DEST_PATH_IMAGE041
All has symmetrical coefficient.The symmetry of usage factor, the multiplier that each subfilter needs become original half, i.e. N/4.The 2 tunnel parallel Finite Impulse Response filters that propose also need 2 pre-service totalizers and 7 aftertreatment totalizers, and delay unit and 1 shift unit of 1 subfilter outside.The number of multipliers that whole subfilters take is N, and number of adders is 2N-4, and therefore whole wave filter realizes that required number of multipliers is N, and number of adders is 2N+5, and wherein N is filter order.
For the characteristics of 3 tunnel parallel Finite Impulse Response filters, adopt the Factoring Polynomials method of proposition according to the present invention, formula (5) can be rewritten as:
Figure DEST_PATH_IMAGE042
Figure DEST_PATH_IMAGE043
Figure DEST_PATH_IMAGE044
（7）
Wherein, identical in every symbolic significance and formula (5).
This moment subfilter ,
Figure DEST_PATH_IMAGE046
,
Figure DEST_PATH_IMAGE047
All has symmetrical coefficient.
According to formula (7), the novel 3 tunnel parallel Finite Impulse Response filters that the present invention proposes as shown in Figure 4.X(3k) and x(3k+1), x(3k+2) be input, y(3k) and y(3k+1), y(3k+2) be output.
Structure of the present invention needs 9 subfilters that length is N/3, and the subfilter of this moment all has symmetrical coefficient, the symmetry of usage factor, and the multiplier that each subfilter needs becomes original half, i.e. N/6.The 3 tunnel parallel Finite Impulse Response filters that propose also need 15 aftertreatment totalizers, delay unit and 3 shift units of 2 subfilter outsides.The number of multipliers that whole subfilters take is 3N/2, and number of adders is 3N-9, and therefore whole wave filter realizes that required number of multipliers is 3N/2, and number of adders is 3N+6, and wherein N is filter order.
The present invention also provides the low power consumption parallel Finite Impulse Response filter by the method for designing acquisition of low power consumption parallel Finite Impulse Response filter.
Beneficial effect of the present invention is: this filter design method makes subfilter realize that required number of multipliers is reduced to original 1/2, whole parallel organization wave filter realizes that required number of multipliers also just is reduced to original half, and corresponding cost is the increase of totalizer.But because the totalizer realization is simple more than multiplier, therefore exchanging multiplier for totalizer is worth.Method of the present invention makes the structure of realization compare and all save hardware resource, reduce and realized power consumption with existing FFA (Fast FIR Algorithms) structure with traditional structure.
Description of drawings
Fig. 1 is traditional 2 tunnel parallel Finite Impulse Response filter structural representations.
Fig. 2 is traditional 3 tunnel parallel Finite Impulse Response filter structural representations.
Fig. 3 is 2 tunnel and the type Finite Impulse Response filter implementation structure schematic diagram that the present invention proposes.
Fig. 4 is 3 tunnel and the type Finite Impulse Response filter implementation structure schematic diagram that the present invention proposes.
Fig. 5 is the implementation structure schematic diagram of subfilter in the present invention.
Number in the figure: 1,2,5,6,7,10,11,15,16,17-subfilter; 3,8,12,19-aftertreatment totalizer; 4,9,13,20-delay unit; 14,18-shift unit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.Carry out with the parallelism wave filter structure that the clearer introduction of example adopts the present invention to propose the process that digital filter design realizes.
Embodiment 1
Consider the linear phase FIR filter of 24 taps, filter coefficient is { h0, h1, h2, h3, h4, h5, h6, h7, h8, h9 ... h22, h23} is owing to being linear phase, wave filter has symmetry coefficient, i.e. h0=h23, and h1=h22, h2=h21.h3=h20 ..., h11=h12.
Adopt the topdown design thinking:
The first step is determined the parallelism wave filter one-piece construction.If adopt traditional 2 tunnel parallel FIR filter constructions to realize, as Fig. 1, needing 4 length is 12 subfilter, and the subfilter transport function is respectively
Figure 420124DEST_PATH_IMAGE018
With
Figure 987503DEST_PATH_IMAGE021
, note
Figure 52411DEST_PATH_IMAGE018
Coefficient be the even item of former coefficient, i.e. { h0, h2, h4 ... h22},
Figure 575796DEST_PATH_IMAGE021
Coefficient be the odd term of former coefficient, i.e. { h1, h3, h5 ... h23}.
Figure 54575DEST_PATH_IMAGE018
With
Figure 296201DEST_PATH_IMAGE021
Coefficient no longer have the coefficient symmetry.This implementation needs 48 multipliers and 46 totalizers, and the resource that takies is a lot.
Adopt the 2 tunnel parallel FIR filter constructions that the present invention proposes to realize, i.e. the structure of Fig. 3.
It is 12 subfilter that this implementation method still needs 4 length, yet the subfilter transport function becomes
Figure 899220DEST_PATH_IMAGE040
With , wherein
Figure DEST_PATH_IMAGE048
Figure DEST_PATH_IMAGE049
Figure DEST_PATH_IMAGE050
Figure DEST_PATH_IMAGE051
…
Subfilter has symmetry coefficient, and the multiplier of half can be multiplexing, so the realization of subfilter only needs the multiplier of half.This implementation needs 24 multipliers and 53 totalizers altogether, has saved hardware resource.
Second step is determined the subfilter implementation structure.The realization of subfilter is the same with the realization of serial wave filter, is made of multiplier, totalizer and delay unit.The realization of serial wave filter has the structures such as Direct-type, transposition type, cascade connection type.Adopt transposition type structure in this example, as shown in Figure 5.List entries first passes through multiplier, multiply by corresponding filter coefficient, then obtains output sequence by delay unit and totalizer successively.Because the coefficient of subfilter herein has symmetry, therefore only need the multiplier of half.
In the 3rd step, determine multiplier and totalizer implementation.Multiplier has the various structures such as booth multiplier, wallace tree multiplier, CSD multiplier.Because the multiplier in the FIR wave filter is the multiplication of constant coefficient device, namely the coefficient of wave filter is determined, so the multiply operation of filter coefficient can be realized by the CSD multiplier.Based on the Multiplier Design thought of CSD coding be with constant coefficient be expressed as adding of 2 integral number power and, multiply operation is reduced to displacement adds, reduce the complexity that realizes.Totalizer adopts the most frequently used carry lookahead adder to realize.
The 4th step, adopt hardware description language (Verilog HDL or VHDL) to carry out the RTL design, use emulation tool such as Modelsim to carry out simulating, verifying, use synthesis tool such as Design Compiler that this design is carried out comprehensively, obtain gate level netlist, carry out at last automatic placement and routing and DRC﹠amp; The LVS inspection obtains physical layout, and the final realization of digital filter is namely completed in flow.

Claims (3)

1. the method for designing of a low power consumption parallel Finite Impulse Response filter, is characterized in that, concrete steps are as follows:
(1) determine the parallelism wave filter one-piece construction;
(2) determine the subfilter implementation structure;
(3) determine multiplier and totalizer implementation, obtain the low power consumption parallel Finite Impulse Response filter;
Wherein, during the described definite parallelism wave filter one-piece construction of step (1), utilize the coefficient symmetry of Linear phase FIR digital filter, adopt the Factoring Polynomials method to make whole subfilters have symmetry coefficient, reduce and realize required number of multipliers; Concrete grammar is as follows:
When 1. described parallelism wave filter one-piece construction was 2 tunnel parallel Finite Impulse Response filter structure, described Factoring Polynomials method formula was as follows:
Figure 265196DEST_PATH_IMAGE002
Wherein,
Figure 736498DEST_PATH_IMAGE003
It is the 1 road input signal sequence
Figure 821128DEST_PATH_IMAGE004
Transform,
Figure 849127DEST_PATH_IMAGE005
It is the 2 road input signal sequence
Figure 214731DEST_PATH_IMAGE006
Transform,
Figure 669983DEST_PATH_IMAGE007
It is the 1 road output signal sequence Transform,
Figure 73599DEST_PATH_IMAGE009
It is the 2 road output signal sequence Transform, Coefficient for subfilter (1) in Traditional parallel Finite Impulse Response filter structure
Figure 982015DEST_PATH_IMAGE012
Transform,
Figure 351817DEST_PATH_IMAGE013
Coefficient for subfilter (2) in Traditional parallel Finite Impulse Response filter structure
Figure 694942DEST_PATH_IMAGE014
Transform;
When 2. described parallelism wave filter one-piece construction was 3 tunnel parallel Finite Impulse Response filter structure, described Factoring Polynomials method formula was:
Figure 429680DEST_PATH_IMAGE015
Figure 38516DEST_PATH_IMAGE016
Figure 133380DEST_PATH_IMAGE017
Wherein,
Figure 144061DEST_PATH_IMAGE003
It is the 1 road input signal sequence
Figure 49700DEST_PATH_IMAGE018
Transform, It is the 2 road input signal sequence
Figure 47317DEST_PATH_IMAGE019
Transform,
Figure 178084DEST_PATH_IMAGE020
It is the 3 road input signal sequence
Figure 254624DEST_PATH_IMAGE021
Transform,
Figure 759424DEST_PATH_IMAGE007
It is the 1 road output signal sequence
Figure 274719DEST_PATH_IMAGE022
Transform,
Figure 197675DEST_PATH_IMAGE009
It is the 2 road output signal sequence Transform,
Figure 499530DEST_PATH_IMAGE024
It is the 3 road output signal sequence
Figure 490619DEST_PATH_IMAGE025
Transform,
Figure 330399DEST_PATH_IMAGE011
Coefficient for subfilter (5) in Traditional parallel Finite Impulse Response filter structure Transform,
Figure 493713DEST_PATH_IMAGE013
Coefficient for subfilter (6) in Traditional parallel Finite Impulse Response filter structure
Figure 269253DEST_PATH_IMAGE027
Transform,
Figure 229119DEST_PATH_IMAGE028
Coefficient for subfilter (7) in Traditional parallel Finite Impulse Response filter structure
Figure 818363DEST_PATH_IMAGE029
Transform.
2. the low power consumption parallel Finite Impulse Response filter that obtains of method for designing according to claim 1.
3. the low power consumption parallel Finite Impulse Response filter that obtains of method for designing according to claim 2, it is characterized in that: the 2 tunnel parallel Finite Impulse Response filter structures that it obtains are comprised of delay unit and 1 shift unit of 4 subfilters with symmetry coefficient, 2 pre-service totalizers, 7 aftertreatment totalizers and 1 subfilter outside; The 3 tunnel parallel Finite Impulse Response filter structures that it obtains are comprised of delay unit and 3 shift units of 9 subfilters with symmetry coefficient, 15 aftertreatment totalizers, 2 subfilter outsides.
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CN103716011B (en) * 2014-01-13 2016-07-06 中国科学院电子学研究所 Finite impulse response CSD wave filter
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CN103955585A (en) * 2014-05-13 2014-07-30 复旦大学 FIR (finite impulse response) filter structure for low-power fault-tolerant circuit
CN103955585B (en) * 2014-05-13 2017-02-15 复旦大学 FIR (finite impulse response) filter structure for low-power fault-tolerant circuit
CN104021246A (en) * 2014-05-28 2014-09-03 复旦大学 Self-adaptive length predictor applied to low power consumption fault-tolerant circuit
CN104504205B (en) * 2014-12-29 2017-09-15 南京大学 A kind of two-dimentional dividing method of the parallelization of symmetrical FIR algorithm and its hardware configuration
CN104504205A (en) * 2014-12-29 2015-04-08 南京大学 Parallelizing two-dimensional division method of symmetrical FIR (Finite Impulse Response) algorithm and hardware structure of parallelizing two-dimensional division method
CN107979354A (en) * 2016-10-25 2018-05-01 三星电子株式会社 Multiphase equipment and its manufacture method and test method for sample rate conversion
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CN106936406A (en) * 2017-03-10 2017-07-07 南京大学 A kind of realization of 5 parallel rapid finite impact response filter
CN107645287A (en) * 2017-05-24 2018-01-30 南京大学 A kind of size based on 6 parallel rapid finite impact response filter cascade structures can configure convolution hardware and realize
CN110138358A (en) * 2019-04-30 2019-08-16 南京大学 A kind of long linear phase limited impulse response digital filter of idol
WO2021046709A1 (en) * 2019-09-10 2021-03-18 深圳市南方硅谷半导体有限公司 Fir filter optimization method and device, and apparatus
CN111125976A (en) * 2019-12-06 2020-05-08 中国电子科技集团公司第五十八研究所 Automatic generation method of RTL model
CN111125976B (en) * 2019-12-06 2022-09-06 中国电子科技集团公司第五十八研究所 Automatic generation method of RTL model

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Application publication date: 20130508