CN101340182B - Low-complexity implementing method and apparatus for FIR digital filter group - Google Patents

Abstract

The invention relates to a low complexity realization method and a device of an FIR digital filter group, the method comprises the following steps: an inner core filter of the filter group is constituted according to the common inner core of a plurality of similar filters in the filter group; the original input vector which is obtained by a tapped delay line is converted according to the corresponding linear convolution relationship between various filters in the group and the inner core filters, thereby constituting a plurality of new input vectors aiming at the inner core filter; the filter group shares a weighted sum unit of the inner core filter, and the respective filter operation of each filter in the group is realized by time-division multiplexing. The realization device of the FIR digital filter group comprises a tapped delay line unit, a vector conversion unit, a gating unit, the weighted sum unit of the inner core filter and a parallel output unit of the inner core filter. The realization method and the device multiplex the inner core filter operational structure which occupies more resources to the maximum extent, thereby reducing the complexity of the hardware realization of the FIR digital filter group and improving the flexibility and the applicability of a system.

Description

The low complex degree implementation method and the device of Finite Impulse Response filter group

Technical field

The invention belongs to digital signal processing technique field, relate to the realization of digital filter, relate in particular to the low complex degree implementation method and the device of Finite Impulse Response filter group.

Background technology

FIR (Finite Impulse Response, finite impulse response) digital filter is a basic module commonly used in digital communication and the signal processing system, occupies important status.Finite Impulse Response filter is widely used in audio-video signal processing and transmission, base band shaping filtering, goes multiple occasions such as mirror image filtering and matched filtering.In the middle of the application of reality, Finite Impulse Response filter often need be realized in various programmable logic devices, digital signal processor spare or application-specific integrated circuit (ASIC).

In recent years, along with expansion and the raising of communication with the signal processing demand, Finite Impulse Response filter more and more is subjected to extensive concern.Regular meeting runs into the situation of having to design higher order filter because of the filtering requirements raising during researcher.For example in China Digital TV terrestrial broadcasting transmission national standard (GB20600-2006), it is 0.05 that the rolloff-factor of the Square-root Raised Cosine FIR filter of modulated terminal shaping filter is required, its transition band is very narrow, the availability of frequency spectrum is very high, this has high requirements to filter order, for hardware is realized, directly caused very high complexity.Therefore the hard-wired optimization of Finite Impulse Response filter is a very real problem.

Finite Impulse Response filter can determine that establishing filter order is finite value N by system function is unique, and its system function Z-transformation can be expressed as:

$H\left(z\right)=\underset{n=0}{\overset{N}{\mathrm{\Σ}}}h\left[n\right]\·z^{-n}---\left(1\right)$

H[n wherein] be the filter finite impulse response, i.e. the coefficient of Finite Impulse Response filter.Then the filter input/output relation is

$y\left[n\right]=x\left[n\right]*h\left[n\right]=\underset{m=0}{\overset{N}{\mathrm{\Σ}}}x[n-m]\·h\left[m\right],---\left(2\right)$

Wherein * represents linear convolution, x[n] be input signal, y[n] be output signal.

The direct type implementation structure of Finite Impulse Response filter as shown in Figure 1, its part mainly comprises tapped delay line, multiplication unit and sum unit three parts, the main composition of other implementation structure (as the transposition type) is with directly type is similar.Directly the computing flow process of type structure as shown in Figure 2, length is the different delayed time that the tapped delay line of N obtains input signal, delay input signal x[n-m] with FIR filter coefficient h[m] multiply each other, whole multiplied result summations are obtained filtering output.

For the linear phase fir digital filter, according to the intrinsic symmetric properties of its filter coefficient, remake multiplication after can merging the tap of coefficient symmetry (as identical or opposite), its implementation structure is as shown in Figure 3.Make like this quantity of required multiplying almost reduce to original half, saved the resource occupation amount during filter hardware is realized greatly.

Directly merge symmetrical taps and realize it being effective processing method for the hardware of an independent linear phase fir digital filter.But this does not utilize symmetry to reduce the complexity of tapped delay line, comprises and reduces delay line length and tap number.Particularly for the realization up to the Large N FIR digital filter on hundreds of rank, the complexity that reduces tapped delay line is very necessary behave.Utilize self similitude (as symmetry) or according to the demand of practical application, a higher order filter can resolve into the subfilter of two or more lower-orders, forms bank of filters.In the digital communication or signal processing system of reality; Shi Changhui runs into this Large N FIR digital filter and decomposes back composition bank of filters is carried out filtering simultaneously to same input signal situation; such as the interpolation or the decimation filter group that adopt heterogeneous (Polyphase) structure, interpolation multiphase filter group as shown in Figure 4.Be not difficult to find that each subfilter in the group may nonlinear phase filter, may there be symmetry in himself coefficient, and the method that merges symmetrical taps just may lose efficacy.

For realizing the Finite Impulse Response filter group, traditional prioritization scheme can only be shared the tapped delay line of input signal, the delay input signal x[n-m of gained] respectively with a plurality of subfilters coefficient h separately _i[m] is weighted summation operation and obtains a plurality of filtering output y _i[n].Above-mentioned traditional implementation structure as shown in Figure 5, there are the following problems for it:

1. hard-wired complexity is still higher, and each subfilter works alone fully, does not make cooperate optimization.Need particularly to realize that the demand of its hardware resource is more huge under the situation of Large N FIR digital filter;

2. if the whole filter group need be adjusted or change, then wherein each subfilter all needs to realize again separately and optimize that system flexibility and adaptability are not high.

Summary of the invention

At the particularly big and flexibility of the complexity height, the hardware resource occupancy that exist of the traditional implementation method of higher order filter group in various programmable logic devices, digital signal processor spare or application-specific integrated circuit (ASIC) of Finite Impulse Response filter group, the not high many weak points of adaptability, the purpose of this invention is to provide the low complex degree implementation method and the implement device of Finite Impulse Response filter group.

For reaching above-mentioned purpose, on the one hand, technical scheme of the present invention provides the low complex degree implement device of Finite Impulse Response filter group, and this Finite Impulse Response filter group comprises M N rank Finite Impulse Response filter, and wherein M is more than or equal to 2, and this device comprises:

The clock source unit provides the clock of f and two kinds of frequencies of Mf;

The tapped delay line unit in the frequency that the clock source unit provides is under the clock driving of f, with input signal x[n] delaying time obtains input time delay signal x[n-m], be expressed as

Input vector;

Vector transduced cell is used for the input vector that the tapped delay line unit is obtained

Change, by changing

In element ordering and sign and shift left accordingly, obtain the new input vector of M

Make

With

Corresponding relation and similar filter coefficient vector

With the kernel filters coefficient vector

Corresponding relation mate fully, promptly

1≤i≤M;

Gating unit is under the Mf that the clock source unit provides leads, to M new input vector The timesharing gating;

The kernel filters weighted sum unit under the Mf frequency that the clock source unit provides, is exported from gating unit

Timesharing is carried out and the kernel filters coefficient vector

The weighted sum computing, obtain M group filtering operation result;

The kernel filters output unit that walks abreast, under the Mf frequency that the clock source unit provides, the M group filtering operation result that kernel filter weight sum unit is obtained is with 0 to M-1 clock cycle of not waiting of frequency Mf time-delay, and the output M that runs simultaneously organizes the filtering operation result.

In addition, this device also comprises:

The error-filter weighted sum unit is under the f frequency that the clock source unit provides, to input vector

Carry out and the error-filter coefficient vector The weighted sum computing;

The summation output unit with M group filtering operation result and its each self-corresponding error-filter operation result addition that the parallel output unit of kernel filters is run simultaneously and exported, obtains the filtering operation result and the output of each Finite Impulse Response filter.

On the other hand, technical scheme of the present invention also provides the low complex degree implementation method of Finite Impulse Response filter group, and this Finite Impulse Response filter group comprises M N rank Finite Impulse Response filter, and wherein M may further comprise the steps more than or equal to 2:

The input signal x[n of described Finite Impulse Response filter group] obtain input vector through tapped delay line

The coefficient vector of each Finite Impulse Response filter is respectively in the group

1≤i≤M;

The kernel filters constitution step, similar characteristic according to each Finite Impulse Response filter in the group, extract the same section of each Finite Impulse Response filter kernel, construct one with the kernel of the error minimum of each Finite Impulse Response filter kernel kernel as the Finite Impulse Response filter group, and the formation kernel filters, its coefficient vector is

The Finite Impulse Response filter decomposition step, from the set that the similar filter of all kernels similar to above-mentioned kernel filters constitutes, according to the filter error criterion, by search, obtain respectively and the similar filter of kernel of organizing interior each Finite Impulse Response filter coefficient error minimum, constitute coefficient vector and be respectively The similar bank of filters of kernel, 1≤i≤M, and each Finite Impulse Response filter in former group is decomposed into the similar filter of kernel of coefficient error minimum with it, and (coefficient vector is

) (coefficient vector is with error-filter corresponding to the similar filter of this kernel ) two parts, the filtering operation of former group of interior each Finite Impulse Response filter is y as a result _i[n] also correspondingly is decomposed into the similar filter operation result of kernel y _Kerneli[n] and corresponding error-filter operation result y _Errori[n] two parts;

The vector switch process is to input vector

Change, by changing

In element ordering and sign and shift left accordingly, structure is at the M of the similar filter of kernel new input vector

Make

With

Corresponding relation mate fully With

Corresponding relation, promptly

1≤i≤M;

The multiplexing step of kernel filters weighted sum, the similar bank of filters of kernel is multiplexing kernel filters weighted sum unit in the different time periods, realizes the filtering operation of the similar filter of each kernel in the similar bank of filters of kernel;

Error-filter weighted sum step is weighted summation to the corresponding error-filter of each Finite Impulse Response filter, realizes the filtering operation of each error-filter

1≤i≤M;

Summation output step, the error-filter that the output of the similar filter of each kernel in the similar bank of filters of above-mentioned kernel is corresponding with it is exported addition, thereby obtains the output of each Finite Impulse Response filter in the Finite Impulse Response filter group:

$y_i\left[n\right]=y_{\mathrm{kerneli}}\left[n\right]+y_{\mathrm{errori}}\left[n\right]=\stackrel{\→}{x}\·{\stackrel{\→}{h}}_{\mathrm{kerneli}}+\stackrel{\→}{x}\·{\stackrel{\→}{h}}_{\mathrm{errori}}=\stackrel{\→}{{x_i}^{\′}}\·{\stackrel{\→}{h}}_{\mathrm{kernel}}+\stackrel{\→}{x}\·{\stackrel{\→}{h}}_{\mathrm{errori}},$ 1≤i≤M。

Wherein, the low complex degree implementation method of above-mentioned Finite Impulse Response filter group, described filter error criterion are meant the mean square error minimum criteria of filter time domain impulse response or the mean square error minimum criteria of filter frequency domain response.

On the one hand, technical scheme of the present invention also provides the low complex degree implementation method of Finite Impulse Response filter group again, and this Finite Impulse Response filter group comprises M N rank FIR similarity number character filter, and wherein M may further comprise the steps more than or equal to 2:

The input signal x[n of described Finite Impulse Response filter group] obtain input vector through tapped delay line

The coefficient vector of each Finite Impulse Response filter in the Finite Impulse Response filter group is respectively 1≤i≤M;

The kernel filters constitution step, the kernel total according to similar filter constitutes kernel filters, establishes its coefficient vector and is

The vector switch process is to input vector

Change, by changing In element ordering and sign and shift left accordingly, structure is at the M of kernel filters new input vector Make

With

Corresponding relation mate fully

With

Corresponding relation, promptly

Here 1≤i≤M;

The multiplexing step of kernel filters weighted sum, described Finite Impulse Response filter group is multiplexing kernel filters weighted sum unit in the different time periods, realizes the filtering operation of each filter in the described Finite Impulse Response filter group.

The beneficial effect of technical scheme provided by the invention is: the present invention makes full use of the similar characteristic between each Finite Impulse Response filter in the Finite Impulse Response filter group, deeply excavate optimization potentiality wherein, the multiplexing to greatest extent more kernel filtering operation structure of resource that takies is optimized and is realized particularly higher order filter group of Finite Impulse Response filter group.Compare with traditional implementation method, effectively reduce hard-wired complexity, reduced hardware resource and taken, improved the flexibility and the applicability of system, and be convenient to expand, realize the bank of filters of a plurality of Finite Impulse Response filters compositions.

Description of drawings

Fig. 1 is the direct type structural representation of existing Finite Impulse Response filter;

Fig. 2 is the computing schematic flow sheet of the direct type structure of existing Finite Impulse Response filter;

Fig. 3 is the direct type structural representation of existing linear phase fir digital filter (supposition N is an even number);

Fig. 4 is the general structural representation of existing interpolation multiphase filter group;

Fig. 5 is traditional implementation structure schematic diagram of existing Finite Impulse Response filter group;

Fig. 6 is the optimization multiplexing structure schematic diagram of similar bank of filters provided by the invention;

Fig. 7 is the operating process schematic diagram of the Finite Impulse Response filter group low complex degree implementation method of being made up of similar filter provided by the invention;

Fig. 8 is the structural representation (M=2) of the Finite Impulse Response filter group low complex degree implement device of being made up of similar filter provided by the invention;

Fig. 9 is the principle schematic (M=2) of kernel filters weighted sum unit provided by the invention;

Figure 10 is the principle schematic (M=2) of the parallel output unit of kernel filters provided by the invention;

Figure 11 is the structural representation (M=2) of the Finite Impulse Response filter group low complex degree implement device of being made up of the incomplete similarity filter provided by the invention;

Figure 12 is the structural representation (M＞2) of the Finite Impulse Response filter group low complex degree implement device of being made up of the incomplete similarity filter provided by the invention.

Embodiment

Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.

For making purpose of the present invention, technical method and advantage clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.

The invention provides the low complex degree implementation method and the implement device of Finite Impulse Response filter group.Realize optimizing at the hardware of Finite Impulse Response filter group.With reference to Fig. 1, Fig. 2, represent direct type structure of Finite Impulse Response filter and computing schematic flow sheet thereof respectively; Fig. 3 represents the direct type structural representation of linear phase fir digital filter (supposition N is an even number), is characterized in that the tap that at first merges symmetry under the prerequisite of coefficient symmetry remakes multiplication; Fig. 4 represents the general structural representation (L is an interpolation factor) of interpolation multiphase filter group; Fig. 5, Fig. 6 represent the traditional implementation structure schematic diagram of bank of filters and the optimization multiplexing structure schematic diagram of similar bank of filters provided by the invention respectively.Below abbreviate Finite Impulse Response filter as filter.

In fact, above-mentioned bank of filters is made up of a plurality of filters, its input signal is identical, and general certain inner link that exists between a plurality of filters, the present invention is referred to as the similar characteristic between a plurality of filters in the bank of filters with it, make a general reference have between the coefficient of each filter absolute value identical or similarly (become 2 ⁿRelation doubly, n is an integer, down with) number, but the difference that puts in order.So, after the tapped delay line of sharing input signal, at the weighted sum computing

If can make full use of the similar characteristic between the filter, just can be by the weighted sum computing that repeats between multiplexing each filter, significantly reduce the operand of the inner repeated and redundant of bank of filters, thereby reduce its hard-wired complexity, save valuable hardware resource.For this reason, be necessary to propose a kind of new general implementation method and optimize the above-mentioned Finite Impulse Response filter group of realization, the independent realization of a plurality of filters in the replacement group.

The present invention is referred to as the low complex degree implementation method of Finite Impulse Response filter group, as shown in Figure 6, optimize the filtering operation that multiplexer is finished a plurality of filters, reduced hard-wired complexity with a similar filter, save hardware resource, improved the flexibility and the adaptability of system simultaneously.

For convenience of description, the bank of filters implementation method of the present invention's proposition need at first be carried out description below:

(1) radix: the coefficient of a Finite Impulse Response filter is h[n], 0≤n≤N, N are the exponent number of Finite Impulse Response filter, wherein the absolute value of arbitrary coefficient

I ∈ n, A _iBe odd number, m _iBe nonnegative integer, here A _iRadix for this coefficient h [i].

(2) kernel: the set of the radix of all coefficients of a Finite Impulse Response filter is the kernel of this filter, and the same cardinality of different coefficients is defined as the element of inequality in this set.

(3) similar filter: the similar each other filter of a plurality of Finite Impulse Response filters that kernel is identical.

(4) kernel filters: any filter that constitutes its coefficient that sorts of the radix by kernel is a kernel filters.

(5) the similar filter of kernel: the identical a plurality of kernel filters of kernel are the similar filter of kernel each other.

Below describe the concrete enforcement of Finite Impulse Response filter group implementation method and device thereof in detail, the Finite Impulse Response filter group of forming with two similar filters is that example is set forth technical scheme of the present invention.

If the input signal of Finite Impulse Response filter group is x[n], the coefficient of its median filter I is h ₁[n], output signal is y ₁[n], then its time domain linear filtering expression formula is:

$y_1\left[n\right]=x\left[n\right]*h_1\left[n\right]=\underset{m=0}{\overset{N}{\mathrm{\Σ}}}x[n-m]\·h_1\left[m\right]---\left(3\right)$

* represents linear convolution in the following formula, x[n-m] be delay input signal, be expressed as input vector

Filter coefficient is expressed as coefficient vector

According to the vector multiplication rule, (3) formula can be converted into:

$y_1\left[n\right]=\stackrel{\&RightArrow;}{x}\&CenterDot;\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="1"\; label="h"\; filenames="H2008101190648E00011.png,H2008101190648E00021.png"\; state="\{\{state\}\}">h</figure-callout>}}_1}---\left(4\right)$

For the sake of simplicity, establish the kernel filters coefficient h of this bank of filters _KernelThe ordering of [n] just in time is to construct according to the ordering of the coefficient of correspondence of filter I, and vector representation is

H then ₁[n] and h _KernelThe pass of [n] is:

$\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="1"\; label="h"\; filenames="H2008101190648E00011.png,H2008101190648E00021.png"\; state="\{\{state\}\}">h</figure-callout>}}_1}=\left(h_1\right[0],h_1[1],...,h_1[N\left]\right)=(\&PlusMinus;h_{\mathrm{kernel}}[0]\&times;2^{{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="H2008101190648E00011.png,H2008101190648E00012.png"\; state="\{\{state\}\}">p</figure-callout>}}_0},\&PlusMinus;h_{\mathrm{kernel}}[1]\&times;2^{{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H2008101190648E00011.png,H2008101190648E00021.png"\; state="\{\{state\}\}">p</figure-callout>}}_1},...,\&PlusMinus;h_{\mathrm{kernel}}[N]\&times;2^{p_N})---\left(5\right)$

" ± " number expresses possibility and to get one of positive negative value, p in the following formula ₀, p ₁..., p _NBe nonnegative integer.According to (5) formula, construct new input vector

Its " ± " number and

With (5) formula

Corresponding fully, then be not difficult to find out by the vector multiplication rule:

$\stackrel{\&RightArrow;}{{x_1}^{\&prime;}}\&CenterDot;{\stackrel{\&RightArrow;}{h}}_{\mathrm{kernel}}=\stackrel{\&RightArrow;}{x}\&CenterDot;{\stackrel{\&RightArrow;}{h}}_1=y_1\left[n\right]---\left(6\right)$

If the coefficient of filter II is h in the group ₂[n], output signal is y ₂[n].Because two filter is similar filter, kernel is identical, so the coefficient of filter II can pass through the kernel filters coefficient h _KernelThe rearrangement of [n], sign change and operation such as shift left is represented.Corresponding coefficient vector:

$\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="2"\; label="h"\; filenames="H2008101190648E00011.png,H2008101190648E00021.png"\; state="\{\{state\}\}">h</figure-callout>}}_2}=(\&PlusMinus;h_{\mathrm{kernel}}[i_0]\&times;2^{{\mathrm{<figure-callout\; id="0"\; label="q"\; filenames="H2008101190648E00011.png,H2008101190648E00012.png"\; state="\{\{state\}\}">q</figure-callout>}}_0},\&PlusMinus;h_{\mathrm{kernel}}[i_1]\&times;2^{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="H2008101190648E00011.png,H2008101190648E00021.png"\; state="\{\{state\}\}">q</figure-callout>}}_1},...,\&PlusMinus;h_{\mathrm{kernel}}[i_N\left]2^{q_N}\right)---\left(7\right)$

" ± " number expresses possibility and to get one of positive negative value, i in the following formula ₀, i ₁..., i _NMutually unequal and constitute 0 to N integer set, q ₀, q ₁..., q _NBe nonnegative integer, then the output y of filter II ₂[n] can be expressed as:

$y_2\left[n\right]=\stackrel{\&RightArrow;}{x}\&CenterDot;\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="2"\; label="h"\; filenames="H2008101190648E00011.png,H2008101190648E00021.png"\; state="\{\{state\}\}">h</figure-callout>}}_2}---\left(8\right)$

Simultaneously, construct new input vector

Its " ± " number and

With (7) formula Corresponding fully, then can get by the vector multiplication rule:

${{\stackrel{\&RightArrow;}{x}}_2}^{\&prime;}\&CenterDot;{\stackrel{\&RightArrow;}{h}}_{\mathrm{kernel}}=\stackrel{\&RightArrow;}{x}\&CenterDot;\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="2"\; label="h"\; filenames="H2008101190648E00011.png,H2008101190648E00021.png"\; state="\{\{state\}\}">h</figure-callout>}}_2}=y_2\left[n\right]---\left(9\right)$

By (6) formula and (9) Shi Kede, with the input vector of the similar characteristic between the similar filter coefficient " transfer " to tapped delay line

On, according to the relation of each filter coefficient and kernel filters coefficient, change accordingly

In element ordering and sign and shift left accordingly, structure is at the new input vector of kernel filters Then the different filtering operation of each filter in the weighted sum unit realization group of reusable kernel filters obtains filtering result separately.What deserves to be explained is, in the middle of hardware such as programmable logic device, digital signal processor spare and application-specific integrated circuit (ASIC) are realized, above-mentioned for input vector

Conversion, comprise that rearrangement, sign change and shift left etc., can realize that these need take few hardware resource by corresponding line and displacement, compared to because of optimizing the required amount of hardware resources that takies of the multiplexing filtering operation that saves, can ignore fully.

With reference to Fig. 7, Fig. 8, represent the operating process schematic diagram of the Finite Impulse Response filter group low complex degree implementation method of forming by similar filter provided by the invention and the structural representation that adopts the implement device (M=2) of this method respectively.Finite Impulse Response filter group low complex degree implement device is made up of modules such as the parallel output units of clock source unit, tapped delay line unit, vector transduced cell, gating unit, kernel filters weighted sum unit and kernel filters.

The clock source unit provides the clock of f and two kinds of frequencies of 2f.

Former filter all is operated under the sample frequency f separately, described tapped delay line unit, the frequency that provides in the clock source is under the clock of f drives, with input signal x[n] delaying time obtains input time delay signal x[n-m], vector representation is

It is input vector.

Described vector transduced cell is one of core cell of Finite Impulse Response filter group low complex degree implement device.Similar characteristic in the Finite Impulse Response filter group between each filter is fully transferred to input vector

On, realize in this unit.In described vector transduced cell, the linear convolution that is complementary according to each filter and kernel filters in the group concerns With

The former input vector that tapped delay line is obtained

Change, by changing

In ordering and sign and the operation such as shift left accordingly of element, obtain new input vector respectively at kernel filters

With

Make

With

Corresponding relation mate fully

With

Corresponding relation, With

Corresponding relation mate fully

With

Corresponding relation.

Described gating unit, the frequency that provides in the clock source are under the clock of 2f drives, to described two groups of new input vectors

With

Carry out the timesharing gating.For example will

Propose the clock cycle gating output of previous frequency 2f, form the input signal of kernel filters weighted sum unit.

With reference to Fig. 9, represent the principle schematic of kernel filters weighted sum unit provided by the invention, this unit is one of core cell of Finite Impulse Response filter group low complex degree implement device.Under the sample frequency of the 2f that this cell operation provides in the clock source,, finish respectively by the weighted sum computing structure of time division multiplexing kernel filters

With The weighted sum computing.For example, import in the clock cycle of previous frequency 2f

With the kernel filters coefficient vector

Be weighted summation operation, the filtering operation that obtains filter I is y as a result ₁₁[n]; In the clock cycle of a back frequency 2f, input

With the kernel filters coefficient vector

Be weighted summation operation, the filtering operation that obtains filter II is y as a result ₂[n].

With reference to Figure 10, represent the principle schematic of the parallel output unit of kernel filters provided by the invention, this unit is operated under the sample frequency of the 2f that the clock source provides equally.If

Carry the clock cycle of previous frequency 2f and finish the weighted sum computing, then this unit is with the operation result y of filter I ₁₁The clock cycle of a frequency 2f of [n] time-delay, obtain operation result y with filter II ₂The time delayed signal y that [n] is synchronous ₁[n] is with y ₁[n] and y ₂[n] and line output, realize described bank of filters two filter and the line output demand.

With reference to Figure 11, represent the structural representation of the Finite Impulse Response filter group low complex degree implement device of forming by two incomplete similarity filters provided by the invention.Finite Impulse Response filter group implementation method provided by the invention and device thereof are equally applicable to the realization of the bank of filters be made up of the incomplete similarity filter.The bank of filters that constitutes with two filters is an example, if the kernel major part of two filters is identical, and the similar bank of filters implementation method that then can adopt the present invention to propose equally.Concrete operations can be as follows: with the kernel of filter A kernel as bank of filters, and the structure kernel filters, coefficient vector is made as

Then can realize filter A with kernel filters as previously mentioned; Utilize the definition of kernel filters, search for the similar filter set that the similar filter of all kernels constitutes,, obtain the similar filter B of kernel to filter B coefficient error minimum according to the filter error criterion _Kernel, then can realize filter B with kernel filters as previously mentioned _KernelAccording to supposition, the kernel major part of two filters is identical, so filter B _KernelAnd the coefficient error between the filter B is very little, can directly realize filter B according to input vector _KernelAnd the error-filter B between the filter B _Error, filter B _KernelWith error-filter B _ErrorThe output sum is exactly the output of filter B.Above-mentioned filter error criterion is meant the mean square error minimum criteria of filter time domain impulse response or the mean square error minimum criteria of filter frequency domain response.

The low complex degree implement device of Finite Impulse Response filter group also comprises in the present embodiment: error-filter weighted sum unit and summation output unit.Wherein, the error-filter weighted sum unit is under the f frequency that the clock source unit provides, to input vector

Carry out and the error-filter coefficient vector

The weighted sum computing, obtain error-filter B _ErrorOperation result; The summation output unit will run simultaneously output kernel filters corresponding to B _KernelOperation result and error-filter B _ErrorThe operation result addition, obtain operation result and the output of filter B in the former Finite Impulse Response filter group.

With reference to Figure 12, represent the structural representation of the Finite Impulse Response filter group low complex degree implement device of forming by a plurality of incomplete similarity filters provided by the invention.Finite Impulse Response filter group implementation method provided by the invention and device thereof are convenient to described Finite Impulse Response filter group is expanded to plural filter very much.If bank of filters comprises the individual filter of M (M 〉=2), then need similar characteristic according to each filter in the group, extract the same section of each filter kernel, construct one with the kernel of the error minimum of each filter kernel kernel as bank of filters, and (coefficient vector is made as to constitute kernel filters

), preceding for another example described, (coefficient vector is made as by searching for the similar filter of kernel that obtains respectively to organizing interior each filter coefficient error minimum

) and corresponding with it error-filter (coefficient vector is made as ).Wherein the similar bank of filters of kernel realizes according to similar bank of filters implementation method and device.

The low complex degree implement device of Finite Impulse Response filter group comprises in the present embodiment: the clock source unit provides the clock of f and two kinds of frequencies of Mf; The tapped delay line unit in the frequency that the clock source unit provides is under the clock driving of f, with input signal x[n] delaying time obtains input time delay signal x[n-m], be expressed as

Input vector; Vector transduced cell is used for the input vector that the tapped delay line unit is obtained Change, by changing

In element ordering and sign and shift left accordingly and wait operation, obtain M input vector newly

1≤i≤M makes

With

Corresponding relation mate the similar filter coefficient vector of kernel fully

With the kernel filters coefficient vector

Corresponding relation, also be

Gating unit is under the Mf frequency that the clock source unit provides, to M new input vector

The timesharing gating; The kernel filters weighted sum unit under the Mf frequency that the clock source unit provides, is exported from gating unit

Timesharing is carried out and the kernel filters coefficient vector

The weighted sum computing, obtain M group filtering operation result; The error-filter weighted sum unit is under the f frequency that the clock source unit provides, to input vector

Carry out and the error-filter coefficient vector

The weighted sum computing; The error-filter coefficient vector

Be to obtain by the Finite Impulse Response filter decomposition step, be specially from the set that the similar filter of all kernels similar to above-mentioned kernel filters constitutes, according to the filter error criterion, by search, obtain respectively and the similar filter of kernel of organizing interior each Finite Impulse Response filter coefficient error minimum, constitute coefficient vector and be respectively

The similar bank of filters of kernel, 1≤i≤M, and each Finite Impulse Response filter in former group is decomposed into the similar filter of kernel of coefficient error minimum with it, and (coefficient vector is

) (coefficient vector is with error-filter corresponding to the similar filter of this kernel ) two parts, the filtering operation of former group of interior each Finite Impulse Response filter is y as a result _i[n] also correspondingly is decomposed into the similar filter operation result of kernel y _Kerneli[n] and corresponding error-filter operation result y _Errori[n] two parts; The kernel filters output unit that walks abreast, under the Mf frequency that the clock source unit provides, the M group filtering operation result that kernel filter weight sum unit is obtained arrives M-1 the clock cycle of not waiting with frequency Mf time-delay 0, the described M group of the output of running simultaneously filtering operation result; The summation output unit with kernel filters operation result and its each self-corresponding error-filter operation result addition of the above-mentioned output of running simultaneously, obtains the filtering operation result and the output of each Finite Impulse Response filter.

The present invention makes full use of the similar characteristic between each filter in the Finite Impulse Response filter group, deeply excavate optimization potentiality wherein, the multiplexing to greatest extent more kernel filtering operation structure of resource that takies is optimized and is realized particularly higher order filter group of Finite Impulse Response filter group.Compare with traditional implementation method, effectively reduce hard-wired complexity, reduced hardware resource and taken, improved the flexibility and the applicability of system, and be convenient to expand, realize the bank of filters of a plurality of Finite Impulse Response filters compositions.

The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (5)

1.FIR the low complex degree implement device of digital filter bank, this Finite Impulse Response filter group comprise M N rank Finite Impulse Response filter, wherein M is characterized in that more than or equal to 2, and this device comprises:

The clock source unit provides the clock of f and two kinds of frequencies of Mf;

The tapped delay line unit in the frequency that the clock source unit provides is under the clock driving of f, with input signal x[n] delaying time obtains input time delay signal x[n-m], be expressed as

Input vector;

Vector transduced cell is used for the input vector that the tapped delay line unit is obtained Change, by changing

In element ordering and sign and shift left accordingly, obtain the new input vector of M

Make

With Corresponding relation and similar filter coefficient vector With the kernel filters coefficient vector

Corresponding relation mate fully, promptly

1≤i≤M;

Gating unit is under the Mf frequency that the clock source unit provides, to M new input vector

The timesharing gating;

The kernel filters weighted sum unit is under the Mf frequency that the clock source unit provides, to what export from gating unit

Timesharing is carried out and the kernel filters coefficient vector

The weighted sum computing, obtain M group filtering operation result;

The kernel filters output unit that walks abreast, under the Mf frequency that the clock source unit provides, M group filtering operation result to kernel filter weight sum unit obtains with 0 to M-1 clock cycle of not waiting of frequency Mf time-delay, runs simultaneously and exports M group filtering operation result.

2. the low complex degree implement device of Finite Impulse Response filter group as claimed in claim 1 is characterized in that, this device also comprises:

The error-filter weighted sum unit is under the f frequency that the clock source unit provides, to input vector

Carry out and the error-filter coefficient vector

The weighted sum computing;

The summation output unit with M group filtering operation result and its each self-corresponding error-filter operation result addition that the parallel output unit of kernel filters is run simultaneously and exported, obtains the filtering operation result and the output of each Finite Impulse Response filter.

3. implementation method of utilizing the described device of claim 1 to reach Finite Impulse Response filter group low complex degree, this Finite Impulse Response filter group comprises M N rank FIR similarity number character filter, wherein M is characterized in that more than or equal to 2, may further comprise the steps:

The input signal x[n of described Finite Impulse Response filter group] obtain input vector through tapped delay line

The coefficient vector of each Finite Impulse Response filter in the group is respectively

1≤i≤M;

The kernel filters constitution step: the kernel total according to similar filter constitutes kernel filters, and its coefficient vector is

Vector switch process: to input vector

Change, by changing

In element ordering and sign and shift left accordingly, structure is at the M of kernel filters new input vector

Make With Corresponding relation mate fully

With

Corresponding relation, promptly

1≤i≤M;

The multiplexing step of kernel filters weighted sum: described Finite Impulse Response filter group is multiplexing kernel filters weighted sum unit in the different time periods, the filtering operation of each Finite Impulse Response filter in the realization group.

4. implementation method of utilizing the described device of claim 2 to reach Finite Impulse Response filter group low complex degree, this Finite Impulse Response filter group comprises M N rank Finite Impulse Response filter, wherein M is characterized in that more than or equal to 2, may further comprise the steps:

The input signal x[n of described Finite Impulse Response filter group] obtain input vector through tapped delay line

The coefficient vector of each Finite Impulse Response filter is respectively in the group

1≤i≤M;

Kernel filters constitution step: according to the similar characteristic of each Finite Impulse Response filter in the group, extract the same section of each Finite Impulse Response filter kernel, construct one with the kernel of the error minimum of each Finite Impulse Response filter kernel kernel as the Finite Impulse Response filter group, and the formation kernel filters, its coefficient vector is

Finite Impulse Response filter decomposition step: from the set that the similar filter of all kernels similar to above-mentioned kernel filters constitutes, according to the filter error criterion, by search, obtain respectively and the similar filter of kernel of organizing interior each Finite Impulse Response filter coefficient error minimum, constitute coefficient vector and be respectively

The similar bank of filters of kernel, 1≤i≤M, and each Finite Impulse Response filter in former group is decomposed into the similar filter of kernel of coefficient error minimum with it, and (coefficient vector is ) (coefficient vector is with error-filter corresponding to the similar filter of this kernel

) two parts, the filtering operation of former group of interior each Finite Impulse Response filter is y as a result _i[n] also correspondingly is decomposed into the similar filter operation result of kernel y _Kerneli[n] and corresponding error-filter operation result y _Errori[n] two parts;

Vector switch process: to input vector

Change, by changing In element ordering and sign and shift left accordingly, structure is at the M of the similar filter of kernel new input vector

Make

With

Corresponding relation mate fully

With

Corresponding relation, promptly

1≤i≤M;

The multiplexing step of kernel filters weighted sum: the similar bank of filters of kernel is multiplexing kernel filters weighted sum unit in the different time periods, realizes the filtering operation of the similar filter of each kernel in the similar bank of filters of kernel;

Error-filter weighted sum step: the corresponding error-filter of each Finite Impulse Response filter is weighted summation, realizes the filtering operation of each error-filter

1≤i≤M;

Summation output step: the error-filter that the output of the similar filter of each kernel in the similar bank of filters of above-mentioned kernel is corresponding with it is exported addition, thereby obtains the output of each Finite Impulse Response filter in the Finite Impulse Response filter group:

$y_i\left[n\right]=y_{\mathrm{kerneli}}\left[n\right]+y_{\mathrm{errori}}\left[n\right]=\stackrel{\&RightArrow;}{x}\&CenterDot;{\stackrel{\&RightArrow;}{h}}_{\mathrm{kerneli}}+\stackrel{\&RightArrow;}{x}\&CenterDot;{\stackrel{\&RightArrow;}{h}}_{\mathrm{errori}}=\stackrel{\&RightArrow;}{{x_i}^{\&prime;}}\&CenterDot;{\stackrel{\&RightArrow;}{h}}_{\mathrm{kernel}}+\stackrel{\&RightArrow;}{x}\&CenterDot;{\stackrel{\&RightArrow;}{h}}_{\mathrm{errori}},$ 1≤i≤M。

5. the low complex degree implementation method of Finite Impulse Response filter group as claimed in claim 4 is characterized in that, described filter error criterion is meant the mean square error minimum criteria of filter time domain impulse response or the mean square error minimum criteria of filter frequency domain response.

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