CN105827217B - One kind having limit for length's impulse response filter circuit and programmable logic device - Google Patents
One kind having limit for length's impulse response filter circuit and programmable logic device Download PDFInfo
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- CN105827217B CN105827217B CN201610120510.1A CN201610120510A CN105827217B CN 105827217 B CN105827217 B CN 105827217B CN 201610120510 A CN201610120510 A CN 201610120510A CN 105827217 B CN105827217 B CN 105827217B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
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Abstract
The invention discloses one kind limit for length's impulse response filter circuit and programmable logic device.The present invention provides a kind of FIR circuit and FPGA, which includes：First input end x, second input terminal h, output end p, multiplier and adder, the first branch being connect with the inputs of first input end x and first cascade data cxi, the second branch being connect with the second input terminal h, connect the third branch of adder and output end p, the first branch exports the first output cascade data cxo, the output result of the first branch and the output result of the second branch input multiplier, the output result of multiplier is connected to adder, the output result of multiplier and the second input cascade data cpi are carried out operation by adder, export the second output cascade data cpo；The first branch, the second branch and third branch routing stone configure to be formed.Implementation through the invention is directly configured by stone and realizes FIR, need not solve the problems, such as that existing FIR needs to be realized by soft IP by external register and coiling.
Description
Technical field
The present invention relates to FPGA (Field-Programmable GateArray, programmable logic device) digital dock necks
Domain more particularly to one kind having limit for length's impulse response filter circuit and FPGA.
Background technology
There is limit for length's impulse response (FIR) filter, is element most basic in digital information processing system, it can protected
With stringent linear phase-frequency characteristic while holding arbitrary amplitude versus frequency characte, at the same because its unit sample respo be it is time-limited, because
And FIR filter is stable system.Therefore FIR filter suffers from extensively in fields such as communication, image procossing, pattern-recognitions
Effect.
The FIR carried in existing FPGA is required for being realized by soft IP, as shown in Figure 1, the L-1 and L-2 in Direct-type FIR prolong
Shi Danyuan is not embedded in hardware circuit A, realizes that this is consumed in a large amount of FPGA by coiling outside stone by soft IP
Coiling resource will increase delay of the data-link to logical unit simultaneously as the length of external coiling increases, to meeting
Influence maximum clock frequency.
Therefore, those skilled in the art urgently provide a kind of FIR filter, are realized by soft IP with solving existing FIR needs
The technical issues of.
Invention content
The present invention provides one kind limit for length's impulse response filter circuit and FPGA, is needed by soft IP with solving existing FIR
The problem of realization.
The present invention provides one kind limit for length's impulse response filter circuit comprising：First input end x, the second input terminal
H, output end p, multiplier and adder, with first input end x and first input cascade data cxi connect the first branch, and
The second branch of second input terminal h connections, the third branch for connecting adder and output end p, the first output of first branch output
Cascade data cxo, the output result of the first branch and the output result of the second branch input multiplier, the output result of multiplier
It is connected to adder, the output result of multiplier and the second input cascade data cpi are carried out operation by adder, and output second is defeated
Go out cascade data cpo；
The first branch includes first selector mux0, the first input register reg0, second selector mux1, first choice
Device mux0 is for selecting data for the input cascade data cxi of first input end x or first, first selector mux0 connections first
Input register reg0 or second selector mux1, the first input register reg0 connection second selectors mux1, second selects
Device mux1 is selected for choosing whether that bypass the first input register reg0, second selector mux1 export the first output cascade data
The output result of cxo, second selector mux1 input multiplier；
The second branch includes the second input register reg1, third selector mux2, the second input register reg1 connections
The output of second input terminal h, the second input register reg1 connects third selector mux2, and third selector mux2 is for selecting
Whether second input register reg1 is bypassed, and the output result of third selector mux2 inputs multiplier；
Third branch includes output register reg4, the 4th selector mux5, and the input connection of output register reg4 adds
The output of musical instruments used in a Buddhist or Taoist mass, output register reg4 connects the 4th selector mux5, and the 4th selector mux5 is defeated for choosing whether to bypass
Go out register reg4, the 4th selector mux5 connection output end ps, the 4th selector mux5 exports the second output cascade data cpo.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enabled second
Input register reg1, the 4th selector mux5 bypass output register reg4, and forming Direct-type has the filtering of limit for length's impulse response
Circuit.
Further, second selector mux1 bypasses the first input register reg0, third selector mux2 bypasses second
Input register reg1, the 4th selector mux5 use output register reg4, and forming transposition type has the filtering of limit for length's impulse response
Circuit.
Further, further include the 4th branch, second selector mux1 passes through the 4th branch and exports the first output cascade number
According to cxo；4th branch includes the first pipeline register reg2, the 5th selector mux3, and the first pipeline register reg2 connects
Meet output connection the 5th selector mux3, the 5th selector mux3 of second selector mux1, the first pipeline register reg2
For choosing whether that the first pipeline register of bypass reg2, the 5th selector mux3 export the first output cascade data cxo.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enabled second
Input register reg1, the 4th selector mux5 bypass output register reg4, and the 5th selector mux3 bypasses the first assembly line
Register reg2, forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enabled second
Input register reg1, the 4th selector mux5 enabled output register reg4, the 5th selector mux3 enable the first assembly line
Register reg2, forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 bypasses the first input register reg0, third selector mux2 bypasses second
Input register reg1, the 4th selector mux5 use output register reg4, the 5th selector mux3 to bypass the first assembly line
Register reg2, forming transposition type has limit for length's impulse response filter circuit.
Further, further include the 5th branch, multiplier passes through the 5th branch and connects adder；5th branch includes second
Pipeline register reg3, the 6th selector mux4, the second pipeline register reg3 connection multipliers, the deposit of the second assembly line
The output of device reg2 connects the 6th selector mux4, and the 6th selector mux4 is for choosing whether the second pipeline register of bypass
Reg2, the 6th selector mux4 are exported to adder.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enabled second
Input register reg1, the 4th selector mux5 bypass output register reg4, and the 6th selector mux4 bypasses the second assembly line
Register reg2, forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enabled second
Input register reg1, the 4th selector mux5 bypass output register reg4, and the 6th selector mux4 enables the second assembly line
Register reg2, forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 bypasses the first input register reg0, third selector mux2 bypasses second
Input register reg1, the 4th selector mux5 use output register reg4, the 6th selector mux4 to bypass the second assembly line
Register reg2, forming transposition type has limit for length's impulse response filter circuit.
Further, second selector mux1 bypasses the first input register reg0, third selector mux2 bypasses second
Input register reg1, the 4th selector mux5 use output register reg4, the 6th selector mux4 to enable the second assembly line
Register reg2, forming transposition type has limit for length's impulse response filter circuit.
The present invention provides a kind of programmable logic device, being provided with provided by the invention has the filtering of limit for length's impulse response
Circuit.
Beneficial effects of the present invention：
The present invention provides one kind limit for length's impulse response filter circuit, is directly configured by stone and realizes FIR, not needed
It by external register and coiling, solves the problems, such as that existing FIR needs to be realized by soft IP, reduces register and be output to and patrol
The delay between arithmetic element is collected, its timing performance is made to be better than the FIR realized by soft IP.It further, can be straight by stone
The FIR filter that Direct-type and transposition type are supported in configuration is connect, soft IP resources are saved.Further, directly using be configured can
Realize that FIR filter can save a large amount of FPGA coilings resource and register resources.
Description of the drawings
Fig. 1 is the circuit connection diagram of existing FIR circuit；
Fig. 2 is the circuit connection diagram for the FIR circuit that first embodiment of the invention provides；
Fig. 3 is the structural schematic diagram of Direct-type FIR circuit；
Fig. 4 is the structural schematic diagram of transposition type FIR circuit；
Fig. 5 is the circuit connection diagram for the FIR circuit that second embodiment of the invention provides；
Fig. 6 is a kind of Direct-type FIR circuit connection diagram in second embodiment of the invention；
Fig. 7 is another Direct-type FIR circuit connection diagram in second embodiment of the invention；
Fig. 8 is a kind of transposition type FIR circuit connection diagram in second embodiment of the invention；
Fig. 9 is another transposition type FIR circuit connection diagram in second embodiment of the invention.
Specific implementation mode
Further annotation explanation now is made to the present invention by way of specific implementation mode combination attached drawing.
First embodiment：
Fig. 2 is the circuit connection diagram for the FIR circuit that first embodiment of the invention provides, as shown in Figure 2, in this implementation
In example, FIR circuit provided by the invention includes：It includes：First input end x, the second input terminal h, output end p, multiplier and
Adder, the first branch being connect with the inputs of first input end x and first cascade data cxi, connect with the second input terminal h the
Two branches, the third branch for connecting adder and output end p, the first branch export the first output cascade data cxo, the first branch
Output result and the output result of the second branch input multiplier, the output result of multiplier is connected to adder, adder
The output result of multiplier and the second input cascade data cpi are subjected to operation, export the second output cascade data cpo；
The first branch includes first selector mux0, the first input register reg0, second selector mux1, first choice
Device mux0 is for selecting data for the input cascade data cxi of first input end x or first, first selector mux0 connections first
Input register reg0 or second selector mux1, the first input register reg0 connection second selectors mux1, second selects
Device mux1 is selected for choosing whether that bypass the first input register reg0, second selector mux1 export the first output cascade data
The output result of cxo, second selector mux1 input multiplier；
The second branch includes the second input register reg1, third selector mux2, the second input register reg1 connections
The output of second input terminal h, the second input register reg1 connects third selector mux2, and third selector mux2 is for selecting
Whether second input register reg1 is bypassed, and the output result of third selector mux2 inputs multiplier；
Third branch includes output register reg4, the 4th selector mux5, and the input connection of output register reg4 adds
The output of musical instruments used in a Buddhist or Taoist mass, output register reg4 connects the 4th selector mux5, and the 4th selector mux5 is defeated for choosing whether to bypass
Go out register reg4, the 4th selector mux5 connection output end ps, the 4th selector mux5 exports the second output cascade data cpo.
In some embodiments, the second selector mux1 in above-described embodiment enables the first input register reg0, the
Three selector mux2 enabled second input register reg1, the 4th selector mux5 bypass output register reg4, and formation is direct
Type has limit for length's impulse response filter circuit.
In some embodiments, the second selector mux1 in above-described embodiment bypasses the first input register reg0, the
Three selector mux2 the second input registers of bypass reg1, the 4th selector mux5 use output register reg4, form transposition
Type has limit for length's impulse response filter circuit.
In some embodiments, above-described embodiment further includes the 4th branch, and second selector mux1 is defeated by the 4th branch
Go out the first output cascade data cxo；4th branch includes the first pipeline register reg2, the 5th selector mux3, first-class
The output of pipeline register reg2 connection second selectors mux1, the first pipeline register reg2 connect the 5th selector
Mux3, the 5th selector mux3 are for choosing whether the first pipeline register reg2 of bypass, the 5th selector mux3 output the
One output cascade data cxo.
In some embodiments, the second selector mux1 in above-described embodiment enables the first input register reg0, the
Three selector mux2 enabled second input register reg1, the 4th selector mux5 bypass output register reg4, the 5th selection
Device mux3 bypasses the first pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In some embodiments, the second selector mux1 in above-described embodiment enables the first input register reg0, the
Three selector mux2 enabled second input register reg1, the 4th selector mux5 enable output register reg4, the 5th selection
Device mux3 enables the first pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In some embodiments, the second selector mux1 in above-described embodiment bypasses the first input register reg0, the
Three selector mux2 the second input registers of bypass reg1, the 4th selector mux5 use output register reg4, the 5th selection
Device mux3 bypasses the first pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
In some embodiments, above-described embodiment further includes the 5th branch, and multiplier connects adder by the 5th branch；
5th branch includes the second pipeline register reg3, the 6th selector mux4, the second pipeline register reg3 connection multiplication
The output of device, the second pipeline register reg2 connects the 6th selector mux4, and the 6th selector mux4 is for choosing whether side
Road the second pipeline register reg2, the 6th selector mux4 are exported to adder.
In some embodiments, the second selector mux1 in above-described embodiment enables the first input register reg0, the
Three selector mux2 enabled second input register reg1, the 4th selector mux5 bypass output register reg4, the 6th selection
Device mux4 bypasses the second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In some embodiments, the second selector mux1 in above-described embodiment enables the first input register reg0, the
Three selector mux2 enabled second input register reg1, the 4th selector mux5 bypass output register reg4, the 6th selection
Device mux4 enables the second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In some embodiments, the second selector mux1 in above-described embodiment bypasses the first input register reg0, the
Three selector mux2 the second input registers of bypass reg1, the 4th selector mux5 use output register reg4, the 6th selection
Device mux4 bypasses the second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
In some embodiments, the second selector mux1 in above-described embodiment bypasses the first input register reg0, the
Three selector mux2 the second input registers of bypass reg1, the 4th selector mux5 use output register reg4, the 6th selection
Device mux4 enables the second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
Corresponding, the present invention provides a kind of programmable logic device, being provided with provided by the invention has limit for length's impulse
Respond filter circuit.
Further annotation explanation is done to the present invention in conjunction with concrete application scene.
Second embodiment：
There is limit for length's impulse response (FIR) filter, is element most basic in digital information processing system, it can protected
With stringent linear phase-frequency characteristic while holding arbitrary amplitude versus frequency characte, at the same because its unit sample respo be it is time-limited, because
And FIR filter is stable system.Therefore FIR filter is communicating, and image procossing, the fields such as pattern-recognition suffer from extensively
Effect.
The formula expression formula of FIR is：
K is the tap number of FIR filter in formula；X [n-k] is delay, the input signal of k tap；H [k] is that kth grade is taken out
Head number (unit impulse response)；L is the class number of filter；Y [n] indicates the output sequence of filter.FIR is according to the knot of realization
Structure can be divided into Direct-type and transposition type FIR filter, and Fig. 3 is Direct-type FIR structure diagrams, and Fig. 4 is transposition type FIR structural frames
Figure.
The present embodiment can be directly realized by both FIR structures by configuring, as shown in figure 5, normally being patrolled guaranteeing to do
It collects and embeds pipeline register reg2 under operation, can directly be configured to obtain Direct-type and transposition type FIR filter by stone.In circuit
All delay units are all controlled by static configuration or dynamic select, and bypass may be selected or use register.Constituting FIR
When, the reg0 in Fig. 5, delay unit of the reg1 registers as FIR, and when doing common logical operation, reg0, reg1 are again
It can be used as input register and play the role of Improving Working Timing.
Circuit structure proposed by the present invention as shown in figure 5, mux0 is input selector, select data from input terminal x or
Cxi on person's cascade chain.Reg0 and reg1 is input register, mux1 and mux2 selectors may choose whether that bypass input is deposited
Device.Reg2 is the pipeline register cascaded on path, and bypass pipeline register can be chosen whether by mux3 selectors.
Multiplier is the multiplier in logical unit, and the unit of multiplying is carried out for input data.Reg3 logical operations
Pipeline register on path can choose whether to bypass by mux4 selectors.Adder is adder, is output cascade number
The unit of adder logic operation is carried out according to cpi and multiplier output result.Reg4 is output register, can pass through mux5 selectors
It chooses whether to bypass.In circuit structure proposed by the present invention, all delay units are all can static configuration or dynamic select control
System, and the FIR of different structure can be constituted according to configuration.
Fig. 6 is a kind of Direct-type FIR being configured to according to the structure diagram of Direct-type FIR, can be configured by circuit structure Fig. 5
It forms, the enabled path of mux1 and mux2 selector mask registers, mux3, mux4, by mux5 selectors all mask registers
The path on road.
Fig. 7 show a kind of higher Direct-type FIR structure charts of operation frequency, can be configured by circuit structure Fig. 5,
The enabled path of mux1, mux2, mux3, mux5 selector mask register, the road of mux4 selectors all mask register bypasses
Diameter.Reg2 and reg4 registers in Fig. 7 structures all play the role of timing optimization, reg0 registers as pipeline register
Timing optimization is not only carried out to input data, but also plays delay unit.
A kind of transposition type FIR that Fig. 8 is configured to according to the structure diagram of transposition type FIR, can be configured by circuit structure Fig. 5,
The enabled path of mux5 selector mask registers, mux1, mux2, the path of mux3 selectors all mask register bypasses.
The reg3 of mux4 selectors control is the pipeline register in logical unit, in transposition type FIR, selection
The register bypasses or the enabled function of not influencing transposition type FIR of register, when reg3 registers are enabled, transposition type FIR's
Arithmetic speed can faster, as shown in Figure 9.
In summary, at least there is following advantageous effect in implementation through the invention：
The present invention provides one kind limit for length's impulse response filter circuit, is directly configured by stone and realizes FIR, not needed
It by external register and coiling, solves the problems, such as that existing FIR needs to be realized by soft IP, reduces register and be output to and patrol
The delay between arithmetic element is collected, its timing performance is made to be better than the FIR realized by soft IP.It further, can be straight by stone
The FIR filter that Direct-type and transposition type are supported in configuration is connect, soft IP resources are saved.Further, directly using be configured can
Realize that FIR filter can save a large amount of FPGA coilings resource and register resources.
It the above is only the specific implementation mode of the present invention, limitation in any form not done to the present invention, it is every
Arbitrary simple modification, equivalent variations, combination or the modification that embodiment of above is made according to the technical essence of the invention, still
Belong to the protection domain of technical solution of the present invention.
Claims (13)
1. one kind having limit for length's impulse response filter circuit, which is characterized in that including：First input end x, the second input terminal h, output
End p, multiplier and adder input the first branch and institute that cascade data cxi is connect with the first input end x and first
It states the second branch of the second input terminal h connections, connect the third branch of the adder and the output end p, described first
Road exports the first output cascade data cxo, and the output result of the first branch is inputted with the output result of the second branch
The multiplier, the output result of the multiplier are connected to the adder, and the adder is by the output of the multiplier
As a result operation is carried out with the second input cascade data cpi, exports the second output cascade data cpo；
The first branch includes first selector mux0, the first input register reg0, second selector mux1, and described first
Selector mux0 is for selecting data for the first input end x or the first input cascade data cxi, first choosing
Select device mux0 connections the first input register reg0 or second selector mux1, first input register
Reg0 connections the second selector mux1, the second selector mux1 bypass the first input deposit for choosing whether
Device reg0, the second selector mux1 export the first output cascade data cxo, the output of the second selector mux1
As a result the multiplier is inputted；
The second branch includes the second input register reg1, third selector mux2, the second input register reg1
Connecting the second input terminal h, the output of the second input register reg1 connects the third selector mux2, and described the
Three selector mux2 are for choosing whether to bypass the second input register reg1, the output knot of the third selector mux2
Fruit inputs the multiplier；
The third branch includes output register reg4, the 4th selector mux5, and the input of the output register reg4 connects
The adder is connect, the output of the output register reg4 connects the 4th selector mux5, the 4th selector
For mux5 for choosing whether to bypass the output register reg4, the 4th selector mux5 connections output end p is described
4th selector mux5 exports the second output cascade data cpo.
2. having limit for length's impulse response filter circuit as described in claim 1, which is characterized in that the second selector mux1 makes
Can the first input register reg0, the third selector mux2 enables the second input register reg1, described the
Four selector mux5 bypass the output register reg4, and forming Direct-type has limit for length's impulse response filter circuit.
3. having limit for length's impulse response filter circuit as described in claim 1, which is characterized in that by the second selector mux1
First input register reg0 described in road, the third selector mux2 bypass the second input register reg1, and described the
Four selector mux5 use the output register reg4, and forming transposition type has limit for length's impulse response filter circuit.
4. having limit for length's impulse response filter circuit as described in claim 1, which is characterized in that further include the 4th branch, it is described
Second selector mux1 exports the first output cascade data cxo by the 4th branch；4th branch includes the
One pipeline register reg2, the 5th selector mux3, the first pipeline register reg2 connections second selector
The output of mux1, the first pipeline register reg2 connect the 5th selector mux3, the 5th selector mux3
For choosing whether to bypass the first pipeline register reg2, the 5th selector mux3 exports first output stage
Join data cxo.
5. having limit for length's impulse response filter circuit as claimed in claim 4, which is characterized in that the second selector mux1 makes
Can the first input register reg0, the third selector mux2 enables the second input register reg1, described the
Four selector mux5 bypass the output register reg4, and the 5th selector mux3 bypasses first pipeline register
Reg2, forming Direct-type has limit for length's impulse response filter circuit.
6. having limit for length's impulse response filter circuit as claimed in claim 4, which is characterized in that the second selector mux1 makes
Can the first input register reg0, the third selector mux2 enables the second input register reg1, described the
Four selector mux5 enable the output register reg4, and the 5th selector mux3 enables first pipeline register
Reg2, forming Direct-type has limit for length's impulse response filter circuit.
7. having limit for length's impulse response filter circuit as claimed in claim 4, which is characterized in that by the second selector mux1
First input register reg0 described in road, the third selector mux2 bypass the second input register reg1, and described the
Four selector mux5 use the output register reg4, the 5th selector mux3 to bypass first pipeline register
Reg2, forming transposition type has limit for length's impulse response filter circuit.
8. as described in any one of claim 1 to 7 have limit for length's impulse response filter circuit, which is characterized in that further include the 5th
Branch, the multiplier connect the adder by the 5th branch；5th branch is deposited including the second assembly line
Device reg3, the 6th selector mux4, the second pipeline register reg3 connections multiplier, second assembly line are posted
The output of storage reg2 connects the 6th selector mux4, and the 6th selector mux4 is for choosing whether to bypass described the
Two pipeline register reg2, the 6th selector mux4 are exported to the adder.
9. having limit for length's impulse response filter circuit as claimed in claim 8, which is characterized in that the second selector mux1 makes
Can the first input register reg0, the third selector mux2 enables the second input register reg1, described the
Four selector mux5 bypass the output register reg4, and the 6th selector mux4 bypasses second pipeline register
Reg2, forming Direct-type has limit for length's impulse response filter circuit.
10. having limit for length's impulse response filter circuit as claimed in claim 8, which is characterized in that the second selector mux1
The first input register reg0 is enabled, the third selector mux2 enables the second input register reg1, described
4th selector mux5 bypasses the output register reg4, and the 6th selector mux4 enables the second assembly line deposit
Device reg2, forming Direct-type has limit for length's impulse response filter circuit.
11. having limit for length's impulse response filter circuit as claimed in claim 8, which is characterized in that the second selector mux1
The first input register reg0 is bypassed, the third selector mux2 bypasses the second input register reg1, described
4th selector mux5 uses the output register reg4, the 6th selector mux4 to bypass the second assembly line deposit
Device reg2, forming transposition type has limit for length's impulse response filter circuit.
12. having limit for length's impulse response filter circuit as claimed in claim 8, which is characterized in that the second selector mux1
The first input register reg0 is bypassed, the third selector mux2 bypasses the second input register reg1, described
4th selector mux5 uses the output register reg4, the 6th selector mux4 to enable the second assembly line deposit
Device reg2, forming transposition type has limit for length's impulse response filter circuit.
13. a kind of programmable logic device, which is characterized in that be arranged has limit for length just like claim 1 to 12 any one of them
Impulse response filter circuit.
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| CN106788331B (en) * | 2016-11-21 | 2020-04-17 | 深圳市紫光同创电子有限公司 | Finite long impulse response filter circuit and programmable logic device |
| CN109032561B (en) * | 2018-07-20 | 2022-10-14 | 福州大学 | Reversible logic adder circuit with carry bypass output as carry selection |
| CN109902040B (en) * | 2019-02-01 | 2021-05-14 | 京微齐力(北京)科技有限公司 | System chip integrating FPGA and artificial intelligence module |
| CN109871950A (en) * | 2019-02-01 | 2019-06-11 | 京微齐力(北京)科技有限公司 | Unit has the chip circuit and System on Chip/SoC of the artificial intelligence module of bypass functionality |
| CN109919321A (en) * | 2019-02-01 | 2019-06-21 | 京微齐力(北京)科技有限公司 | Unit has the artificial intelligence module and System on Chip/SoC of local accumulation function |
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