CN105827217A - Finite long impulse response filter circuit and field-programmable gate array - Google Patents
Finite long impulse response filter circuit and field-programmable gate array Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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- H—ELECTRICITY
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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- H03H2017/0081—Theoretical filter design of FIR filters
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Abstract
The invention discloses a finite long impulse response filter circuit and a field-programmable gate array. The invention provides the FIR circuit and the FPGA. The FIR circuit comprises a first input end x, a second input end h, an output end p, a multiplier and an adder, a first branch which is connected with the first input end x and first input cascade data cxi, a second branch which is connected with the second input end h, and a third branch which is connected with the adder and the output end p. The first branch outputs first output cascade data cxo. The output result of the first branch and the output result of the second branch are inputted to the multiplier. The output result of the multiplier is connected to the adder. The adder performs operation on the output result of the multiplier and second input cascade data cpi so as to output second output cascade data cpo. The first branch, the second branch and the third branch are formed by hardcore configuration. With application of the finite long impulse response filter circuit and the field-programmable gate array, the FIR is realized through hardcore configuration directly with no requirement for an external register or a winding so that the problem that the existing FIR requires to be realized by soft IP can be solved.
Description
Technical field
The present invention relates to FPGA (Field-ProgrammableGateArray, PLD) digital dock field, particularly relating to one has limit for length's impulse response filter circuit and FPGA.
Background technology
There is limit for length's impulse response (FIR) wave filter, it it is element most basic in digital information processing system, it can keep having while any amplitude-frequency characteristic strict linear phase-frequency characteristic, is time-limited because of its unit sample respo simultaneously, thus FIR filter is stable system.Therefore FIR filter suffers from acting on widely in fields such as communication, image procossing, pattern recognitions.
The FIR carried in existing FPGA is required for being realized by soft IP, as shown in Figure 1, L-1 and L-2 delay unit in Direct-type FIR is not the most embedded in hardware circuit A, realized by the outside coiling of stone by soft IP, this consumes the coiling resource in a large amount of FPGA, simultaneously as the length of outside coiling increases, the Data-Link time delay to ALU can be increased, thus maximum clock frequency can be affected.
Therefore, those skilled in the art urgently provide a kind of FIR filter, the technical problem realized to solve existing FIR to need by soft IP.
Summary of the invention
The invention provides one and have limit for length's impulse response filter circuit and FPGA, to solve the problem that existing FIR needs to be realized by soft IP.
The invention provides one and have limit for length's impulse response filter circuit, comprising: first input end x, second input h, output end p, multiplier and adder, the first branch road being connected with first input end x and first input cascade data cxi, the second branch road being connected with the second input h, connect the 3rd branch road of adder and output end p, first branch road exports the first output cascade data cxo, the output result of the first branch road inputs multiplier with the output result of the second branch road, the output result of multiplier is connected to adder, the output result of multiplier is carried out computing with the second input cascade data cpi by adder, export the second output cascade data cpo；
First branch road includes first selector mux0, the first input register reg0, second selector mux1, it is first input end x or first input cascade data cxi that first selector mux0 is used for selecting data, first selector mux0 connects the first input register reg0 or second selector mux1, first input register reg0 connects second selector mux1, second selector mux1 is used for choosing whether to bypass the first input register reg0, second selector mux1 exports the first output cascade data cxo, the output result input multiplier of second selector mux1；
Second branch road includes the second input register reg1, third selector mux2, second input register reg1 connects the second input h, the output of the second input register reg1 connects third selector mux2, third selector mux2 is used for choosing whether to bypass the second input register reg1, the output result input multiplier of third selector mux2；
3rd branch road includes output register reg4, the 4th selector mux5, the input of output register reg4 connects adder, the output of output register reg4 connects the 4th selector mux5,4th selector mux5 is used for choosing whether to bypass output register reg4,4th selector mux5 connects output end p, and the 4th selector mux5 exports the second output cascade data cpo.
Further, second selector mux1 enables the first input register reg0, and third selector mux2 enables the second input register reg1, the 4th selector mux5 and bypasses output register reg4, and forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 bypasses the first input register reg0, and third selector mux2 bypasses the second input register reg1, the 4th selector mux5 and uses output register reg4, and forming transposition type has limit for length's impulse response filter circuit.
Further, also include that the 4th branch road, second selector mux1 export the first output cascade data cxo by the 4th branch road；4th branch road includes first-class pipeline register reg2, the 5th selector mux3, first-class pipeline register reg2 connects second selector mux1, the output of first-class pipeline register reg2 connects the 5th selector mux3,5th selector mux3 is used for choosing whether to bypass first-class pipeline register reg2, the 5th selector mux3 and exports the first output cascade data cxo.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 bypasses output register reg4,5th selector mux3 bypasses first-class pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 enables output register reg4,5th selector mux3 enables first-class pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 bypasses the first input register reg0, third selector mux2 bypasses the second input register reg1,4th selector mux5 uses output register reg4,5th selector mux3 bypasses first-class pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
Further, also including the 5th branch road, multiplier connects adder by the 5th branch road；5th branch road includes second pipeline register reg3, the 6th selector mux4, second pipeline register reg3 connects multiplier, the output of second pipeline register reg2 connects the 6th selector mux4,6th selector mux4 is used for choosing whether to bypass second pipeline register reg2, the 6th selector mux4 and exports to adder.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 bypasses output register reg4,6th selector mux4 bypasses second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 bypasses output register reg4,6th selector mux4 enables second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
Further, second selector mux1 bypasses the first input register reg0, third selector mux2 bypasses the second input register reg1,4th selector mux5 uses output register reg4,6th selector mux4 bypasses second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
Further, second selector mux1 bypasses the first input register reg0, third selector mux2 bypasses the second input register reg1,4th selector mux5 uses output register reg4,6th selector mux4 enables second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
The invention provides a kind of PLD, what it was provided with that the present invention provides has limit for length's impulse response filter circuit.
Beneficial effects of the present invention:
The invention provides one and have limit for length's impulse response filter circuit, directly realize FIR by stone configuration, need not by outside depositor and coiling, solve the problem that existing FIR needs to be realized by soft IP, decrease the time delay that depositor exports between ALU so that it is timing performance is better than the FIR realized by soft IP.Further, can directly be configured support Direct-type and the FIR filter of transposition type by stone, save soft IP resource.Further, direct use has been configured and can realize FIR filter and can save substantial amounts of FPGA coiling resource and register resources.
Accompanying drawing explanation
Fig. 1 is the circuit connection diagram of existing FIR circuit；
The circuit connection diagram of the FIR circuit that Fig. 2 provides for first embodiment of the invention；
Fig. 3 is the structural representation of Direct-type FIR circuit；
Fig. 4 is the structural representation of transposition type FIR circuit；
The circuit connection diagram of the FIR circuit that Fig. 5 provides for second embodiment of the invention；
Fig. 6 is a kind of Direct-type FIR circuit connection diagram in second embodiment of the invention；
Fig. 7 is the another kind of Direct-type FIR circuit connection diagram in second embodiment of the invention；
Fig. 8 is a kind of transposition type FIR circuit connection diagram in second embodiment of the invention；
Fig. 9 is the another kind of transposition type FIR circuit connection diagram in second embodiment of the invention.
Detailed description of the invention
Now by the way of detailed description of the invention combines accompanying drawing, the present invention is made and further annotate explanation.
First embodiment:
The circuit connection diagram of the FIR circuit that Fig. 2 provides for first embodiment of the invention, as shown in Figure 2, in the present embodiment, the FIR circuit that the present invention provides includes: comprising: first input end x, second input h, output end p, multiplier and adder, the first branch road being connected with first input end x and first input cascade data cxi, the second branch road being connected with the second input h, connect the 3rd branch road of adder and output end p, first branch road exports the first output cascade data cxo, the output result of the first branch road inputs multiplier with the output result of the second branch road, the output result of multiplier is connected to adder, the output result of multiplier is carried out computing with the second input cascade data cpi by adder, export the second output cascade data cpo；
First branch road includes first selector mux0, the first input register reg0, second selector mux1, it is first input end x or first input cascade data cxi that first selector mux0 is used for selecting data, first selector mux0 connects the first input register reg0 or second selector mux1, first input register reg0 connects second selector mux1, second selector mux1 is used for choosing whether to bypass the first input register reg0, second selector mux1 exports the first output cascade data cxo, the output result input multiplier of second selector mux1；
Second branch road includes the second input register reg1, third selector mux2, second input register reg1 connects the second input h, the output of the second input register reg1 connects third selector mux2, third selector mux2 is used for choosing whether to bypass the second input register reg1, the output result input multiplier of third selector mux2；
3rd branch road includes output register reg4, the 4th selector mux5, the input of output register reg4 connects adder, the output of output register reg4 connects the 4th selector mux5,4th selector mux5 is used for choosing whether to bypass output register reg4,4th selector mux5 connects output end p, and the 4th selector mux5 exports the second output cascade data cpo.
In certain embodiments, second selector mux1 in above-described embodiment enables the first input register reg0, third selector mux2 enables the second input register reg1, the 4th selector mux5 and bypasses output register reg4, and forming Direct-type has limit for length's impulse response filter circuit.
In certain embodiments, second selector mux1 in above-described embodiment bypasses the first input register reg0, third selector mux2 bypasses the second input register reg1, the 4th selector mux5 and uses output register reg4, and forming transposition type has limit for length's impulse response filter circuit.
In certain embodiments, above-described embodiment also includes that the 4th branch road, second selector mux1 export the first output cascade data cxo by the 4th branch road；4th branch road includes first-class pipeline register reg2, the 5th selector mux3, first-class pipeline register reg2 connects second selector mux1, the output of first-class pipeline register reg2 connects the 5th selector mux3,5th selector mux3 is used for choosing whether to bypass first-class pipeline register reg2, the 5th selector mux3 and exports the first output cascade data cxo.
In certain embodiments, second selector mux1 in above-described embodiment enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 bypasses output register reg4,5th selector mux3 bypasses first-class pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In certain embodiments, second selector mux1 in above-described embodiment enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 enables output register reg4,5th selector mux3 enables first-class pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In certain embodiments, second selector mux1 in above-described embodiment bypasses the first input register reg0, third selector mux2 bypasses the second input register reg1,4th selector mux5 uses output register reg4,5th selector mux3 bypasses first-class pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
In certain embodiments, above-described embodiment also includes the 5th branch road, and multiplier connects adder by the 5th branch road；5th branch road includes second pipeline register reg3, the 6th selector mux4, second pipeline register reg3 connects multiplier, the output of second pipeline register reg2 connects the 6th selector mux4,6th selector mux4 is used for choosing whether to bypass second pipeline register reg2, the 6th selector mux4 and exports to adder.
In certain embodiments, second selector mux1 in above-described embodiment enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 bypasses output register reg4,6th selector mux4 bypasses second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In certain embodiments, second selector mux1 in above-described embodiment enables the first input register reg0, third selector mux2 enables the second input register reg1,4th selector mux5 bypasses output register reg4,6th selector mux4 enables second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
In certain embodiments, second selector mux1 in above-described embodiment bypasses the first input register reg0, third selector mux2 bypasses the second input register reg1,4th selector mux5 uses output register reg4,6th selector mux4 bypasses second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
In certain embodiments, second selector mux1 in above-described embodiment bypasses the first input register reg0, third selector mux2 bypasses the second input register reg1,4th selector mux5 uses output register reg4,6th selector mux4 enables second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
Corresponding, the invention provides a kind of PLD, what it was provided with that the present invention provides has limit for length's impulse response filter circuit.
In conjunction with concrete application scenarios the present invention done and further annotate explanation.
Second embodiment:
There is limit for length's impulse response (FIR) wave filter, it it is element most basic in digital information processing system, it can keep having while any amplitude-frequency characteristic strict linear phase-frequency characteristic, is time-limited because of its unit sample respo simultaneously, thus FIR filter is stable system.The fields such as therefore FIR filter is communicating, image procossing, pattern recognition suffer from acting on widely.
The formula expression formula of FIR is:
In formula, k is the tap number of FIR filter；X [n-k] is time delay, the input signal of k tap；H [k] is kth level tap number (unit impulse response)；L is class's number of wave filter；Y [n] represents the output sequence of wave filter.FIR can be divided into Direct-type and transposition type FIR filter according to the structure realized, and Fig. 3 is Direct-type FIR structured flowchart, and Fig. 4 is transposition type FIR structured flowchart.
The present embodiment can be directly realized by both FIR structures by configuring, as it is shown in figure 5, guaranteeing to be embedded pipeline register reg2 under normal logical operations, directly can be obtained Direct-type and transposition type FIR filter by stone configuration.In circuit, all of delay unit all passes through static configuration or dynamically selects to control, optional bypass or use depositor.When constituting FIR, the reg0 in Fig. 5, reg1 depositor is as the delay unit of FIR, and when doing common logical operations, reg0, reg1 can play again the effect of Improving Working Timing as input register.
The circuit structure that the present invention proposes, as it is shown in figure 5, mux0 is input selector, selects data from the cxi on input x or cascade chain.Reg0 and reg1 is input register, mux1 and mux2 selector may choose whether bypass input depositor.Reg2 is the pipeline register on cascade path, can be chosen whether by-pass pipeline register by mux3 selector.Multiplier is the multiplier in ALU, carries out the unit of multiplying for input data.Pipeline register on reg3 logical operations path, can choose whether bypass by mux4 selector.Adder is adder, carries out the unit of adder logic computing for output cascade data cpi and multiplier output result.Reg4 is output register, can choose whether bypass by mux5 selector.In the circuit structure that the present invention proposes, all of delay unit all can static configuration or dynamically select to control, it is possible to constitute the FIR of different structure according to configuration.
Fig. 6 is a kind of Direct-type FIR that the structured flowchart according to Direct-type FIR is configured to, and can be formed by circuit structure Fig. 5 configuration, the path that mux1 and mux2 selector mask register enables, the path of mux3, mux4, mux5 selector all mask registers bypass.
Fig. 7 show the higher a kind of Direct-type FIR structure chart of operation frequency, can be formed by circuit structure Fig. 5 configuration, the path that mux1, mux2, mux3, mux5 selector mask register enables, the path of mux4 selector all mask registers bypass.Reg2 Yu reg4 depositor in Fig. 7 structure all plays the effect of timing optimization as pipeline register, and reg0 register pair input data had both carried out timing optimization, and played again the effect of delay unit.
A kind of transposition type FIR that Fig. 8 is configured to according to the structured flowchart of transposition type FIR, can be configured by circuit structure Fig. 5, the path that mux5 selector mask register enables, the path of mux1, mux2, mux3 selector all mask registers bypass.
The reg3 that mux4 selector controls is the pipeline register on ALU, in transposition type FIR, the bypass of this depositor or depositor is selected to enable the function not affecting transposition type FIR, when reg3 depositor enables, the arithmetic speed of transposition type FIR can faster, as shown in Figure 9.
In summary, by the enforcement of the present invention, at least there is following beneficial effect:
The invention provides one and have limit for length's impulse response filter circuit, directly realize FIR by stone configuration, need not by outside depositor and coiling, solve the problem that existing FIR needs to be realized by soft IP, decrease the time delay that depositor exports between ALU so that it is timing performance is better than the FIR realized by soft IP.Further, can directly be configured support Direct-type and the FIR filter of transposition type by stone, save soft IP resource.Further, direct use has been configured and can realize FIR filter and can save substantial amounts of FPGA coiling resource and register resources.
Below it is only the detailed description of the invention of the present invention; not the present invention is done any pro forma restriction; any simple modification, equivalent variations that embodiment of above is done by every technical spirit according to the present invention, combine or modify, all still fall within the protection domain of technical solution of the present invention.
Claims (13)
1. one kind has limit for length's impulse response filter circuit, it is characterized in that, including: first input end x, second input h, output end p, multiplier and adder, the first branch road being connected with described first input end x and first input cascade data cxi, the second branch road being connected with described second input h, connect the 3rd branch road of described adder and described output end p, described first branch road exports the first output cascade data cxo, the output result of described first branch road inputs described multiplier with the output result of described second branch road, the output result of described multiplier is connected to described adder, the output result of described multiplier is carried out computing with the second input cascade data cpi by described adder, export the second output cascade data cpo；
Described first branch road includes first selector mux0, first input register reg0, second selector mux1, it is described first input end x or described first input cascade data cxi that described first selector mux0 is used for selecting data, described first selector mux0 connects described first input register reg0 or described second selector mux1, described first input register reg0 connects described second selector mux1, described second selector mux1 is used for choosing whether to bypass described first input register reg0, described second selector mux1 exports described first output cascade data cxo, the output result of described second selector mux1 inputs described multiplier；
Described second branch road includes the second input register reg1, third selector mux2, described second input register reg1 connects described second input h, the output of described second input register reg1 connects described third selector mux2, described third selector mux2 is used for choosing whether to bypass described second input register reg1, and the output result of described third selector mux2 inputs described multiplier；
Described 3rd branch road includes output register reg4, the 4th selector mux5, the input of described output register reg4 connects described adder, the output of described output register reg4 connects described 4th selector mux5, described 4th selector mux5 is used for choosing whether to bypass described output register reg4, described 4th selector mux5 connects described output end p, and described 4th selector mux5 exports described second output cascade data cpo.
There is limit for length's impulse response filter circuit the most as claimed in claim 1, it is characterized in that, described second selector mux1 enables described first input register reg0, described third selector mux2 enables described second input register reg1, described 4th selector mux5 bypasses described output register reg4, and forming Direct-type has limit for length's impulse response filter circuit.
There is limit for length's impulse response filter circuit the most as claimed in claim 1, it is characterized in that, described second selector mux1 bypasses described first input register reg0, described third selector mux2 bypasses described second input register reg1, described 4th selector mux5 uses described output register reg4, and forming transposition type has limit for length's impulse response filter circuit.
Having limit for length's impulse response filter circuit the most as claimed in claim 1, it is characterised in that also include the 4th branch road, described second selector mux1 exports described first output cascade data cxo by described 4th branch road；Described 4th branch road includes first-class pipeline register reg2, described 5th selector mux3, described first-class pipeline register reg2 connects described second selector mux1, the output of described first-class pipeline register reg2 connects described 5th selector mux3, described 5th selector mux3 is used for choosing whether to bypass described first-class pipeline register reg2, described 5th selector mux3 and exports described first output cascade data cxo.
There is limit for length's impulse response filter circuit the most as claimed in claim 4, it is characterized in that, described second selector mux1 enables described first input register reg0, described third selector mux2 enables described second input register reg1, described 4th selector mux5 bypasses described output register reg4, described 5th selector mux3 bypasses described first-class pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
There is limit for length's impulse response filter circuit the most as claimed in claim 4, it is characterized in that, described second selector mux1 enables described first input register reg0, described third selector mux2 enables described second input register reg1, described 4th selector mux5 enables described output register reg4, described 5th selector mux3 enables described first-class pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
There is limit for length's impulse response filter circuit the most as claimed in claim 4, it is characterized in that, described second selector mux1 bypasses described first input register reg0, described third selector mux2 bypasses described second input register reg1, described 4th selector mux5 uses described output register reg4, described 5th selector mux3 bypasses described first-class pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
8. having limit for length's impulse response filter circuit as described in any one of claim 1 to 7, it is characterised in that also include the 5th branch road, described multiplier connects described adder by described 5th branch road；Described 5th branch road includes second pipeline register reg3, described 6th selector mux4, described second pipeline register reg3 connects described multiplier, the output of described second pipeline register reg2 connects described 6th selector mux4, described 6th selector mux4 is used for choosing whether to bypass described second pipeline register reg2, and described 6th selector mux4 output is to described adder.
There is limit for length's impulse response filter circuit the most as claimed in claim 8, it is characterized in that, described second selector mux1 enables described first input register reg0, described third selector mux2 enables described second input register reg1, described 4th selector mux5 bypasses described output register reg4, described 6th selector mux4 bypasses described second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
There is limit for length's impulse response filter circuit the most as claimed in claim 8, it is characterized in that, described second selector mux1 enables described first input register reg0, described third selector mux2 enables described second input register reg1, described 4th selector mux5 bypasses described output register reg4, described 6th selector mux4 enables described second pipeline register reg2, and forming Direct-type has limit for length's impulse response filter circuit.
11. have limit for length's impulse response filter circuit as claimed in claim 8, it is characterized in that, described second selector mux1 bypasses described first input register reg0, described third selector mux2 bypasses described second input register reg1, described 4th selector mux5 uses described output register reg4, described 6th selector mux4 bypasses described second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
12. have limit for length's impulse response filter circuit as claimed in claim 8, it is characterized in that, described second selector mux1 bypasses described first input register reg0, described third selector mux2 bypasses described second input register reg1, described 4th selector mux5 uses described output register reg4, described 6th selector mux4 enables described second pipeline register reg2, and forming transposition type has limit for length's impulse response filter circuit.
13. 1 kinds of PLDs, it is characterised in that arrange just like having limit for length's impulse response filter circuit described in any one of claim 1 to 12.
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| CN106788331A (en) * | 2016-11-21 | 2017-05-31 | 深圳市紫光同创电子有限公司 | One kind has limit for length's impulse response filter circuit and PLD |
| CN109032561A (en) * | 2018-07-20 | 2018-12-18 | 福州大学 | A kind of carry bypass output is the reversible logic adder circuit of carry select |
| CN109871950A (en) * | 2019-02-01 | 2019-06-11 | 京微齐力(北京)科技有限公司 | Unit has the chip circuit and System on Chip/SoC of the artificial intelligence module of bypass functionality |
| CN109902040A (en) * | 2019-02-01 | 2019-06-18 | 京微齐力(北京)科技有限公司 | A kind of System on Chip/SoC of integrated FPGA and artificial intelligence module |
| CN109919321A (en) * | 2019-02-01 | 2019-06-21 | 京微齐力(北京)科技有限公司 | Unit has the artificial intelligence module and System on Chip/SoC of local accumulation function |
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| CN106788331A (en) * | 2016-11-21 | 2017-05-31 | 深圳市紫光同创电子有限公司 | One kind has limit for length's impulse response filter circuit and PLD |
| CN106788331B (en) * | 2016-11-21 | 2020-04-17 | 深圳市紫光同创电子有限公司 | Finite long impulse response filter circuit and programmable logic device |
| CN109032561A (en) * | 2018-07-20 | 2018-12-18 | 福州大学 | A kind of carry bypass output is the reversible logic adder circuit of carry select |
| CN109032561B (en) * | 2018-07-20 | 2022-10-14 | 福州大学 | Reversible logic adder circuit with carry bypass output as carry selection |
| CN109871950A (en) * | 2019-02-01 | 2019-06-11 | 京微齐力(北京)科技有限公司 | Unit has the chip circuit and System on Chip/SoC of the artificial intelligence module of bypass functionality |
| CN109902040A (en) * | 2019-02-01 | 2019-06-18 | 京微齐力(北京)科技有限公司 | A kind of System on Chip/SoC of integrated FPGA and artificial intelligence module |
| CN109919321A (en) * | 2019-02-01 | 2019-06-21 | 京微齐力(北京)科技有限公司 | Unit has the artificial intelligence module and System on Chip/SoC of local accumulation function |
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