CN106708467B - A kind of width bit accumulator circuit and its design method, programmable logic device - Google Patents
A kind of width bit accumulator circuit and its design method, programmable logic device Download PDFInfo
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The present invention provides a kind of wide bit accumulator circuit and its design methods, programmable logic device, the width bit accumulator circuit includes first input end A, second input terminal B, third input terminal C, 4th input terminal PI, first output end P0, first adder and with the first input end A, second input terminal B and the first branch of third input terminal C connection, the second branch being connect with the 4th input terminal PI, the third branch being connect with the first output end P0, the output result of the output result of the first branch and the second branch is carried out operation by the first adder, the first parallel data is exported by third branch；The first branch, second branch and third branch routing stone configure to be formed.Implementation through the invention, the wide bit accumulator that can be directly realized by directly is configured by stone, it does not need to reduce register by external register and coiling and be output to the delay between logical unit, its timing performance is made to be better than the accumulator realized by soft IP.
Description
Technical field
The present invention relates to FPGA (Field Programmable Gate Array, programmable logic device) technical field,
More particularly to a kind of wide bit accumulator circuit and its design method, programmable logic device.
Background technique
Accumulator is the operand and operation knot that specially can be used to store arithmetic or logical operation in arithmetic unit
The register of fruit, can be carried out add, subtract, reading, shifting, the operation such as cyclic shift and supplement, be the chief component of arithmetic unit.
It also has a wide range of applications in digital display circuit, is the important operation component in many digital display circuit data paths, especially exists
In high-performance microprocessor, digital signal processor, graphic image system, scientific algorithm and certain specific data processing equipments
Even more indispensable component part has very important status, can usually become the bottleneck of system performance.
Currently, DSP (Digital Signal Processor, digital signal processor) is embedded in existing FPGA
Accumulator function, but DSP embedded accumulator is fixed, in practical applications, if being needed when the wide bit accumulator of demand
To configure and be realized by DSP external resource, this can consume the coiling resource of a large amount of FPGA, simultaneously as outside DSP around
Line length increases, and will increase the delay of register to DSP, to will affect the maximum clock frequency for realizing accumulator.
Therefore, those skilled in the art urgently provide a kind of wide bit accumulator, to solve existing wide bit accumulator needs
The technical issues of by being realized by exterior arrangement resource.
Summary of the invention
It is existing to solve the present invention provides a kind of wide bit accumulator circuit and its design method, programmable logic device
The technical issues of accumulator needs are just able to achieve by DSP external circuit arrangement resource.
In order to solve the above technical problems, the present invention provides a kind of wide bit accumulator circuits, comprising: first input end A, the
Two input terminal B, third input terminal C, the 4th input terminal PI, the first output end P0, first adder and with it is described first input
End A, the second input terminal B and the C connection of third input terminal the first branch, connect with the 4th input terminal PI second branch,
The third branch being connect with the first output end P0, the first adder by the output result of the first branch with it is described
The output result of second branch carries out operation, exports the first parallel data by the third branch；
The first branch includes multiplier and first selector, the multiplier be used for the first input end A and
The data of second input terminal B input carry out multiplying, obtain the first operational data, and export to the first selector, institute
State the data that first selector is inputted according to first selection signal sel0 from first operational data and the third input terminal C
A data are selected to export to the first adder in two data；
The second branch includes second selector, and the second selector is used for according to the second selection signal sel1 from institute
One data of selection at least three data of the 4th input terminal PI input are stated to export to the first adder；
The third branch include the first output register preg1, the input terminal of the first output register preg1 with
The output end of the first adder connects, the output end of the first output register preg1 and the first output end P0
Connection, for exporting the first parallel data.
Further, the wide bit accumulator circuit further includes the 4th branch, the 4th branch and first addition
The output end of device connects, and the first output cascade data for exporting the first adder carry out operation, and output second is simultaneously
Row data.
Further, the 4th branch include third selector, second adder, the second output register preg2 with
And the second output terminal P1 being connect with the second output register preg2, the third selector is according to third selection signal
Sel2 selection is exported by moving to right the cascade data that M obtain to the second adder by the first output cascade data,
The second adder moves to right the cascade data and second output register that M obtain for what the third selector exported
The data of preg2 output carry out add operation, and export to the second output register preg2.
Further, if at least three data of the 4th input terminal PI input include: by the first input cascade data
Move to right M obtained cascade datas, the data of the first output register preg1 output and first output register
When three data of low M-bit data of the data of preg1 output, the second selector is one-out-three selector, the one-out-three
Selector selects an output to the first adder according to the second selection signal sel1 from three data.
Further, when the first selection signal sel0 be first operational data selection signal, described second
When selection signal sel1 is the selection signal of the data of the first output register preg1 output, the first adder will
First operational data and the data of the first output register preg1 output carry out add operation, export operation result
To the first output register preg1, the first parallel data is obtained.
Further, when the first selection signal sel0 be first operational data selection signal, described second
When selection signal sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 output, described the
One adder carries out the low M-bit data of first operational data and the data of the first output register preg1 output
Add operation exports operation result to the first output register preg1, obtains third parallel data.
Further, when the first selection signal sel0 be first operational data selection signal, described second
Selection signal sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 output, the third
When selection signal sel2 is the selection signal by the first output cascade data by moving to right the cascade data that M obtain, institute
First adder is stated by the low M-bit data of first operational data and the data of the first output register preg1 output
Carrying out add operation, the first adder exports the first output cascade data to the third selector according to operation result,
The third selector is connect with the second adder, will through moving to right the first output cascade data that M obtain export to
The second adder, the second adder is by the first output cascade data that M obtain and described second defeated of moving to right
The data of register preg2 output carry out add operation out, export operation result to the second output register preg2, obtain
To the 4th parallel data.
In order to solve the above-mentioned technical problem, the present invention also provides a kind of programmable logic device, including it is as described above
Wide bit accumulator circuit.
In order to solve the above-mentioned technical problem, the present invention also provides a kind of wide bit accumulator circuit design method, the width
Bit accumulator circuit includes the first branch, second branch, the first output register preg1 and first output register
The the first output end P0 and first adder of preg1 connection, which is characterized in that the described method includes:
Multiplier and first selector be set in the first branch, and the multiplier is by first input end A and second
The data of input terminal B input carry out obtained the first operational data of multiplying and export to the first selector, and described first
Selector is according to first selection signal sel0 from two data of data that first operational data and third input terminal C input
A data are selected to export to the first adder；
Second selector is set in the second branch, wherein the second selector is one-out-three selector, it is described
Second selector is used to select one from least three data that the 4th input terminal PI is inputted according to the second selection signal sel1
Data are exported to the first adder, and the first adder is by the data exported according to the first selector and described the
The data of two selectors output carry out operation, export the first parallel data by the first output register preg1；
4th branch, the 4th branch and the first adder are set on the output end of the first adder
Output end connection, the first output cascade data for exporting the first adder carry out operation, output second and line number
According to.
Further, described that the 4th is arranged between the first adder and the first output register preg1
Road includes: the setting third selector, second adder, the second output register on the output end of the first adder
Preg2 and the second output terminal P1 connecting with the second output register preg2, the third selector are selected according to third
It selects signal sel2 selection and is added by the first output cascade data by moving to right the cascade data that M obtain and exporting to described second
Musical instruments used in a Buddhist or Taoist mass, the second adder move to right the cascade data and second output that M obtain for what the third selector exported
The data of register preg2 output carry out add operation, and export to the second output register preg2, and described second is defeated
Register preg2 exports the second parallel data out.
The beneficial effects of the present invention are:
The present invention provides a kind of wide bit accumulator circuit and its design methods, programmable logic device, directly by matching
It sets and FPGA coiling resource and register resources that wide bit accumulator can be saved outside Digital Logic processing module can be achieved；Further
, the wide bit accumulator function of support can be directly configured by stone, save soft IP resource；It further, can by stone configuration
The wide bit accumulator being directly realized by does not need to reduce register by external register and coiling and be output to logical operation list
Delay between member makes its timing performance be better than the accumulator realized by soft IP.
Detailed description of the invention
Fig. 1 is the circuit connection diagram for the wide bit accumulator circuit that first embodiment of the invention provides；
Fig. 2 is the circuit connection signal of the wide bit accumulator circuit for 2 cascaded-outputs that first embodiment of the invention provides
Figure；
Fig. 3 is that the circuit of the wide bit accumulator circuit for output 48 bit of maximum bit wide that first embodiment of the invention provides connects
Connect schematic diagram；
Fig. 4 is that the circuit of the wide bit accumulator circuit for output 66 bit of maximum bit wide that first embodiment of the invention provides connects
Connect schematic diagram；
Fig. 5 is the design method flow chart for the wide bit accumulator circuit that second embodiment of the invention provides.
Specific embodiment
Scheme proposed by the present invention is described in further detail below by specific embodiment combination attached drawing.
First embodiment:
Referring to Figure 1, Fig. 1 is the circuit connection diagram for the wide bit accumulator circuit that first embodiment of the invention provides,
As shown in Figure 1, in the present embodiment, wide bit accumulator circuit provided by the invention includes: first input end A, the second input terminal
B, third input terminal C, the 4th input terminal PI, the first output end P0, first adder adder0 and with the first input end
A, the second input terminal B and the first branch of third input terminal C connection, connect with the 4th input terminal PI second branch,
The third branch being connect with the first output end P0, wherein two input terminals of first adder adder0adder0 are distinguished
It is connect with the output end of the first branch and second branch, for carrying out the output result of the first branch and second branch at operation
Reason exports the first output cascade data according to operation result, and the first adder adder0 is also defeated by the first of output
Cascade data is exported to the third branch out, exports the first parallel data by the first output end P0.
As shown in Figure 1, the first branch includes multiplier multipler and first selector mux0, the multiplier
The output end of multipler is connect with the first input end A and the second input terminal B respectively, passes through described first for receiving
The data that input terminal A and the second input terminal B are inputted parallel, and receive two data are subjected to multiplying, obtain first
Operational data；Further, the multiplier multipler exports first operational data to the first selector
One of input terminal in mux0, another input terminal of the first selector mux0 are connect with the third input terminal C,
The first operational data that the first selector mux0 is exported according to first selection signal sel0 from the multiplier multipler
And one data of selection are exported to the first adder adder0 in two data of data of third input terminal C input.
The second branch includes second selector mux1, the input terminal and the 4th input terminal of the second selector mux1
PI connection, output end are connect with the input terminal of the first adder adder0, for according to the second selection signal sel1 from institute
One data of selection at least three data of the 4th input terminal PI input are stated to export to the first adder adder0.
The third branch include the first output register preg1, the input terminal of the first output register preg1 with
The output end of the first adder adder0 connects, the output end of the first output register preg1 and described first defeated
Outlet P0 connection, for exporting the first parallel data.
As shown in Fig. 2, the wide bit accumulator circuit further includes the 4th branch, the 4th branch and first addition
The output end of device adder0 connects, and the first output cascade data for exporting the first adder adder0 are transported
It calculates, exports the second parallel data.
Specifically, the 4th branch includes third selector mux2, second adder adder1, the second output register
The preg2 and second output terminal P1 being connect with the second output register preg2, wherein preferred, the third selection
Device mux2 uses one-out-three selector, and the input terminal of the third selector mux2 and the output end of first adder adder0 connect
It connects, output end is connect with the input terminal of the second adder adder1, the output end of the second adder adder1 and institute
State the second output register preg2 connection, the output end company of the second output terminal P1 and the second output register preg2
It connects.
In the present embodiment, when the third selection signal sel2 is the cascade data after selection moves to right, the third choosing
It selects device mux2 and moves to right M obtained grades for being passed through according to third selection signal sel2 selection by the first output cascade data
Connection data, which are exported to the second adder adder1, the second adder adder1, exports the third selector mux2
Move to right cascade data that M obtain and the data of the second output register preg2 output carry out add operation, and export
To the second output register preg2, the second output register preg2 exports the second parallel data.
In the present embodiment, if at least three data of the 4th input terminal PI input include: by the first input cascade
M obtained cascade datas of data shift right, the data of the first output register preg1 output and first output are posted
When three data of low M-bit data of the data of storage preg1 output, the second selector mux1 is one-out-three selector, institute
State one-out-three selector selects an output to the first adder according to the second selection signal sel1 from three data
Adder0, it is preferred that the M is the positive integer more than or equal to 18 and less than 48 (18≤M < 48).
Further, the third input terminal C and the 4th input terminal PI can be to merge, specifically, when the third is defeated
When the data for entering to hold C to input are all the data of the first output register preg1 output, the third input terminal C and the 4th
Input terminal PI can be shared.
As shown in figure 3, to export the wide bit accumulator circuit diagram of 48 bit of maximum bit wide, if the first input end
The data of A and the second input terminal B input are the data A [17:0] and B [17:0] of 18 bits, and the first selector
Mux0, the corresponding selection signal of second selector mux1 are respectively as follows: when the first selection signal sel0 is first operation
The selection signal of data, the second selection signal sel1 are the selection of the data of the first output register preg1 output
When signal, the first adder adder0 exports first operational data and the first output register preg1
Data Pr [47:0] carries out add operation, and output operation result to the first output register preg1 obtains first and line number
According to P0 [47:0], corresponding calculation formula are as follows: P0 [47:0]=Pr [47:0]+A [17:0] * B [17:0].
As shown in figure 4, to export the schematic diagram of the wide bit accumulator circuit of 66 bit of maximum bit wide, concrete implementation 66 compares
Special output specifically realized by 2 cascade outputs, wherein the data P1 of first cascaded-output is 18 bits, the 2nd
The data P2 of a cascaded-output is 48 bits, and 2 cascaded-outputs, which are stacked, to be added up just as maximum 66 bit of parallel output.
When the selection signal that the first selection signal sel0 is first operational data, second selection signal
When sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 output, the first adder
Adder0 by first operational data and the first output register preg1 output data low M-bit data 30'h0,
Pr0 [17:0] } add operation is carried out, operation result is exported to the first output register preg1, obtains third parallel data
P1 [17:0], corresponding calculation formula are as follows: P1 [17:0]={ 30'h0, Pr0 [17:0] }+A [17:0] * B [17:0].
Further, the first selection signal sel0 be first operational data selection signal, described second
On the basis of selection signal of the selection signal sel1 for the low M-bit data of the data of the first output register preg1 output,
The third selection signal sel2 is to be believed by the first output cascade data by moving to right the selection for the cascade data that M obtain
Number when, the first adder adder0 according to operation result export the first output cascade data PO[47:0] extremely described third is selected
Select device mux2, the third selector mux2 according to third selection signal first by after the first output cascade data shift right 18,
It obtains moving to right cascade data PO[47:0] > > > 18, and this is selected to move to right cascade data output PO[47:0] > > > 18 to described second
Adder adder1, the second adder adder1 move to right described cascade data that 18 obtain and post with second output
The data Pr1 [47:0] of storage preg2 output carries out add operation, output operation result to second output register
Preg2 obtains the 4th parallel data P2 [65:18]=Pr1 [47:0]+PO[47:0]>>>18。
Corresponding, the present invention also provides a kind of programmable logic device comprising width accumulator provided in this embodiment
Circuit, the first branch, second branch, third branch, the 4th branch, multiplier multipler in the wide accumulator circuit,
Selector is realized by the stone configuration of the programmable logic device.
Width bit accumulator circuit provided in this embodiment, configures the wide bit accumulator that can be directly realized by by stone, is not required to
It to solve existing accumulator needs by external register and coiling and be just able to achieve by DSP external circuit arrangement resource
The problem of, while also reducing register and being output to the delay between logical unit, it is better than its timing performance by soft IP
The accumulator of realization.
Second embodiment:
Fig. 5 is the flow chart for the wide bit accumulator circuit design method that hungry embodiment of the invention provides, referring to FIG. 5,
The wide bit accumulator circuit includes: the first branch, second branch, the first output register preg1, exports and deposit with described first
The the first output end P0 and first adder adder0 of device preg1 connection are configured when designing the circuit particular by stone
It realizes, configuration design cycle is as follows:
Multiplier multipler and first selector mux0 is arranged in S501 in the first branch.
In this step, the first branch is configured to by stone and is configured with multiplier multipler and alternative selector,
Two input terminals of the multiplier multipler are connect with first input end A, the second input terminal B respectively, for receiving two
The data A [17:0] and B [17:0] of a input terminal input, and by A [17:0] and B [17:0] progress multiplying obtains the
One operational data is exported to alternative selector, and the alternative selector is transported according to first selection signal sel0 from described first
One data of selection are exported to first addition in the evidence that counts and two data of data Pr [47:0] of third input terminal C input
Device adder0.
Second selector mux1 is arranged in S502 in the second branch.
In this step, second branch is configured to by stone and configures one-out-three selector, in the one-out-three selector
Input terminal in input three data, including by the first data shift right M obtained cascade data of input cascade, described first defeated
Three numbers of low M-bit data of the data of register preg1 output and the data of the first output register preg1 output out
According to the one-out-three selector selects an output to add to described first according to the second selection signal sel1 from three data
Musical instruments used in a Buddhist or Taoist mass adder0.
S503, judges whether the first selection signal sel0 and the second selection signal sel1 meet first condition, if full
Foot, then export the first parallel data.
In this step, the specific first selection signal sel0 and the second selection signal sel1 meets first condition
Are as follows: when the selection signal that the first selection signal sel0 is first operational data, the second selection signal sel1 is
When the selection signal of the data of the first output register preg1 output, the first adder adder0 is by described first
Operational data and the data of the first output register preg1 output carry out add operation, output operation result to described the
One output register preg1, obtains the first parallel data.
In the present embodiment, when it is 48 bit that wide bit accumulator circuit, which only needs to export maximum data, it is only necessary to pass through
Executing step S501-S503 can be realized, and pass through the operation of control first selector mux0 selection output multiplier multipler
As a result, and control second selector mux1 selection output the first output register preg1 output data, can be realized
One maximum output is the wide bit accumulator of 48 bits, and physical circuit connection is as shown in Figure 3.
But it if also needs when the data of output are greater than 48 bit in the wide position designed by step S501-S503
On the basis of accumulator circuit, it is further added by level-one output, it is specific such as step S504-S507.
The 4th branch is arranged in S504 on the output end of the first adder adder0.
In this step, third is set on the output end of the first adder adder0 particular by stone configuration
Selector mux2, second adder adder1, the second output register preg2 and with the second output register preg2
The second output terminal P1, the third selector mux2 of connection are selected according to third selection signal sel2 by first output stage
Connection data are exported by moving to right the cascade data that M obtain to the second adder adder1, the second adder
Adder1 moves to right the cascade data and second output register that M obtain for what the third selector mux2 was exported
The data of preg2 output carry out add operation, and export to the second output register preg2.
S505, judges whether the first selection signal sel0 and the second selection signal sel1 meet second condition, if full
Foot, then export third parallel data.
When the selection signal that the first selection signal sel0 is first operational data, second selection signal
When sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 output, the first adder
Adder0 is added the low M-bit data of first operational data and the data of the first output register preg1 output
Method operation exports operation result to the first output register preg1, obtains third parallel data.
S506 selects third selection signal sel2 for by the first output cascade data on the basis of step S505
By the selection signal for moving to right the cascade data that M obtain.
S507, according to third selection signal sel2, the 4th branch first adder adder0 is exported
One output cascade data carry out operation, export the 4th parallel data.
Specifically, second parallel data is realized by 2 cascade outputs, wherein the number of the 1st cascaded-output
It is 18 bits according to P1, the data P2 of the 2nd cascaded-output is 48 bits, and it is just maximum that 2 cascaded-outputs, which are stacked and add up,
66 bit of parallel output.
Firstly, the 1st cascaded-output is by the first adder adder0 by first operational data and described the
The low M-bit data of the data of one output register preg1 output carries out add operation, output operation result to first output
Register preg1 obtains third parallel data.
After the completion of first cascaded-output, continued to output by the 2nd cascaded-output, specifically by the first adder
Adder0 exports the first output cascade data to the third selector mux2 according to operation result, will obtain by moving to right M
The first output cascade data export to the second adder adder1, the second adder adder1 and move to right M for described
The data of the first output cascade data and the second output register preg2 output that position obtains carry out add operation, output
Operation result obtains the 4th parallel data to the second output register preg2.
It is alternately exported by the way that the 1st cascade and the 2nd are cascade, so that realizing highest output digit reaches 66 bits
Parallel data.
In conclusion implementation through the invention, at least exist it is following the utility model has the advantages that
The present invention provides a kind of wide bit accumulator circuit and its design methods, programmable logic device, directly by hard
Caryogamy, which is set, can be achieved wide bit accumulator, can not only save FPGA coiling resource and register money outside Digital Logic processing module
Source can also save soft IP resource；Further, the wide bit accumulator that can be directly realized by is configured by stone, does not need to pass through
External register and coiling reduces register and is output to the delay between logical unit, make its timing performance better than logical
Cross the accumulator that soft IP is realized.
The above content is combining specific embodiment to be further described to made by the embodiment of the present invention, cannot recognize
Fixed specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs,
Without departing from the inventive concept of the premise, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the present invention
Protection scope.
Claims (10)
1. a kind of width bit accumulator circuit characterized by comprising first input end A, the second input terminal B, third input terminal C,
4th input terminal PI, the first output end P0, first adder and defeated with the first input end A, the second input terminal B and third
The first branch for entering to hold C connection, is connect with the first output end P0 the second branch connecting with the 4th input terminal PI
Third branch, the first adder transport the output result of the first branch and the output result of the second branch
It calculates, the first parallel data is exported by the third branch；
The first branch includes multiplier and first selector, and the multiplier is used for the first input end A and second
The data of input terminal B input carry out multiplying, obtain the first operational data, and export to the first selector, and described the
Inputted according to first selection signal sel0 from first operational data and the third input terminal C data two of one selector
A data are selected to export to the first adder in data；
The second branch includes second selector, and the second selector is used for according to the second selection signal sel1 from described the
One data of selection are exported to the first adder at least three data of four input terminal PI input；
The third branch include the first output register preg1, the input terminal of the first output register preg1 with it is described
The output end of first adder connects, and the output end of the first output register preg1 is connect with the first output end P0,
For exporting the first parallel data.
2. width bit accumulator circuit according to claim 1, which is characterized in that it further include the 4th branch, described 4th
Road is connect with the output end of the first adder, and the first output cascade data for exporting the first adder carry out
Operation exports the second parallel data.
3. width bit accumulator circuit according to claim 2, which is characterized in that the 4th branch includes third selection
Device, second adder, the second output register preg2 and the second output being connect with the second output register preg2
P1 is held, the third selector is selected by the first output cascade data according to third selection signal sel2 by moving to right M
Obtained cascade data is exported to the second adder, and the second adder moves to right M for what the third selector exported
The data of cascade data and the second output register preg2 output that position obtains carry out add operation, and export to described
Second output register preg2.
4. width bit accumulator circuit according to claim 3, which is characterized in that if the 4th input terminal PI input is extremely
Few three data include: to cascade data shift right M obtained cascade data, first output register by the first input
When three data of low M-bit data of the data of the data and the first output register preg1 output of preg1 output, institute
Stating second selector is one-out-three selector, and the one-out-three selector is according to the second selection signal sel1 from three data
Select an output to the first adder.
5. width bit accumulator circuit according to claim 4, which is characterized in that when the first selection signal sel0 is institute
The selection signal of the first operational data is stated, the second selection signal sel1 is the first output register preg1 output
When the selection signal of data, the first adder is defeated by first operational data and the first output register preg1
Data out carry out add operation, export operation result to the first output register preg1, obtain the first parallel data.
6. width bit accumulator circuit according to claim 4, which is characterized in that when the first selection signal sel0 is institute
The selection signal of the first operational data is stated, the second selection signal sel1 is the first output register preg1 output
When the selection signal of the low M-bit data of data, the first adder posts first operational data and first output
The low M-bit data of the data of storage preg1 output carries out add operation, output operation result to first output register
Preg1 obtains third parallel data.
7. width bit accumulator circuit according to claim 4, which is characterized in that when the first selection signal sel0 is institute
The selection signal of the first operational data is stated, the second selection signal sel1 is the first output register preg1 output
The selection signal of the low M-bit data of data, the third selection signal sel2 are by the first output cascade data by right
When moving the selection signal of M obtained cascade datas, the first adder is defeated by first operational data and described first
The low M-bit data of the data of register preg1 output carries out add operation out, and the first adder is exported according to operation result
First output cascade data to the third selector, the third selector is connect with the second adder, will be by the right side
M the first obtained output cascade data are moved to export to the second adder, the second adder by it is described move to right M must
The the first output cascade data arrived and the data of the second output register preg2 output carry out add operation, export operation
As a result to the second output register preg2, the 4th parallel data is obtained.
8. a kind of programmable logic device characterized by comprising width bit accumulator as described in any one of claim 1 to 7
Circuit.
9. a kind of width bit accumulator circuit design method, the wide bit accumulator circuit includes the first branch, second branch, first
Output register preg1, with the first output register preg1 the first output end P0 connecting and first adder, it is special
Sign is, which comprises
Multiplier and first selector are set in the first branch, and the multiplier inputs first input end A and second
The data of end B input carry out the first operational data that multiplying obtains and export to the first selector, the first choice
Device is selected from two data of data that first operational data and third input terminal C input according to first selection signal sel0
One data is exported to the first adder；
Second selector is set in the second branch, wherein the second selector be one-out-three selector, described second
Selector is used to select a data from least three data that the 4th input terminal PI is inputted according to the second selection signal sel1
Output to the first adder, the first adder selects the data exported according to the first selector and described second
The data for selecting device output carry out operation, export the first parallel data by the first output register preg1；
4th branch, the output of the 4th branch and the first adder are set on the output end of the first adder
End connection, the first output cascade data for exporting the first adder carry out operation, export the second parallel data.
10. width bit accumulator circuit design method according to claim 9, which is characterized in that described to add described first
It includes: on the output end of the first adder that the 4th branch is arranged between musical instruments used in a Buddhist or Taoist mass and the first output register preg1
Third selector, second adder, the second output register preg2 are set and connected with the second output register preg2
The second output terminal P1 connect, the third selector are selected according to third selection signal sel2 by the first output cascade data
It exports by moving to right the cascade data that M obtain to the second adder, the second adder is by the third selector
The data progress add operation for moving to right the cascade data that M obtain and the second output register preg2 output of output, and
It exports to the second output register preg2, the second output register preg2 and exports the second parallel data.
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