CN109032561A - A kind of carry bypass output is the reversible logic adder circuit of carry select - Google Patents
A kind of carry bypass output is the reversible logic adder circuit of carry select Download PDFInfo
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The present invention relates to the reversible logic adder circuits that a kind of bypass output of carry is carry select, including FG gate circuit, TOF gate circuit, first DPG gate circuit, 2nd DPG gate circuit, 3rd DPG gate circuit, 4th DPG gate circuit, first HNG gate circuit, 2nd HNG gate circuit, 3rd HNG gate circuit, 4th HNG gate circuit, 5th HNG gate circuit, 6th HNG gate circuit, 7th HNG gate circuit, 8th HNG gate circuit, first Fediken gate circuit, 2nd Fediken gate circuit, 3rd Fediken gate circuit, 4th Fediken gate circuit, 5th Fediken gate circuit, and the 6th Fediken gate circuit.The present invention, which can be realized, reduces rubbish output, reduces constant input, and reduce reversible door number.
Description
Technical field
The present invention relates to adder designs field, especially a kind of carry bypass output is that the reversible logic of carry select adds
Adder circuit.
Background technique
Bypass adder and the common selection mode that binary adder is to speed up with carry-select adder, bypass is added
The output of musical instruments used in a Buddhist or Taoist mass is selected as the position of carry-select adder, is counted as the improvement of conditional carry adder, effective to improve fortune
Calculate performance.Simultaneously with the raising of arithmetic speed, low power dissipation design cannot be ignored in adder calculating process, and according to Landor, you are former
Reason is effective approach for solving power consumption using reversible logic.Reversible logic requires to output and input that there are one-to-one mapping passes
System, while it being not allow for closed loop or feedback, commonly using reversible door at present includes: CNOT gate, FG, Fediken, TOF, DPG
With HNG, Peres and TR etc..The basic principle of reversible logic design includes: minimum rubbish output, uses constant less as far as possible
Input, minimum reversible door and modularized design etc..The hot spot that reversible logic has become next-generation technology has received widespread attention, and
Have been applied in the fields such as quantum calculation, Low Power Digital Circuit, digital information processing, the communication technology and computer picture.State
The reversible logic that outer periodical has published the decade adder indicated with binary system and BCD redundant code is realized, in circuit reality
On now, VosAD and Desoete in 2002 realizes reciprocal circuit using transistor configurations, for the first time applies to them industrial real
It is existing；K.Prudhvi Raj proposes the realization of digital circuit transistor level within 2014.
It is 8 binary adders of carry select as shown in Figure 1, low 4 are bypassed using carry to carry bypass output
Adder, low 4 carry propagations Pi=Ai ⊕ Bi, worst case delay occur be 1 when lowest order carry inputs Cin, propagate
Pass through entire adder chain and makes output carry Co3 1, and carry bypass adder is the Co3 as BP=P0P1P2P3=1
Cin is directly selected as output.If BP is 0, just gradually calculated according to the computational algorithm of ripple adder.
High 4 use and first assume that two 4 bit-serial adder lowest order carries for 0 and be 1 both of these case, calculate separately
Out they and and carry.Then the carry input terminal that alternatively device selects of low 4 bypasses output selects final sum
And carry.
Summary of the invention
In view of this, the purpose of the present invention is to propose to the reversible logic adders that a kind of bypass output of carry is carry select
Circuit can be realized and reduce rubbish output, reduce constant input, and reduce reversible door number.
The present invention uses following scheme to realize: a kind of carry bypass output is electric for the reversible logic adder of carry select
Road, including FG gate circuit, TOF gate circuit, the first DPG gate circuit, the 2nd DPG gate circuit, the 3rd DPG gate circuit, the 4th DPG
Circuit, the first HNG gate circuit, the 2nd HNG gate circuit, the 3rd HNG gate circuit, the 4th HNG gate circuit, the 5th HNG gate circuit,
6th HNG gate circuit, the 7th HNG gate circuit, the 8th HNG gate circuit, the first Fediken gate circuit, the 2nd Fediken electricity
Road, the 3rd Fediken gate circuit, the 4th Fediken gate circuit, the 5th Fediken gate circuit and the 6th Fediken electricity
Road；The input of the adder includes the end Cin, the end A0, the end B0, the end A1, the end B1, the end A2, the end B2, the end A3, the end B3, the end A4, B4
End, the end A5, the end B5, the end A6, the end B6, the end A7 and the end B7；The output of the adder includes the end Co7, the end S0, the end S1, S2
End, the end S3, the end S4, the end S5, the end S6 and the end S7；
Each HNG gate circuit and each DPG gate circuit include input terminal A, input terminal B, input terminal C, input terminal D, defeated
Outlet P, output end Q, output end R and output end S；The TOF gate circuit includes input terminal A, input terminal B, input terminal C, defeated
Enter to hold D, input terminal E, output end P, output end Q, output end R, output end S and output end T；The FG gate circuit includes defeated
Enter to hold A, input terminal B, output end P, output end Q；The Fediken gate circuit include input terminal A, input terminal B, input terminal C,
Output end P, output end Q and output end R；
Cin end of the input terminal A of the FG gate circuit as the adder, the output end P of the FG gate circuit, output
End Q is respectively connected to the input terminal B of the input terminal D of the first DPG gate circuit, the first Fediken gate circuit, and the described first DPG
A0 end, B0 end of input terminal A, the input terminal B of circuit respectively as adder, the output end R conduct of the first DPG gate circuit
The end S0 of adder, output end Q, the output end S of the first DPG gate circuit are respectively connected to the input terminal D of TOF gate circuit,
The input terminal D of the 2nd DPG gate circuit, input terminal A, the input terminal B of the 2nd DPG gate circuit are respectively as adder
The end A1, the end B1, S1 end of the output end R of the 2nd DPG gate circuit as adder, the output of the 2nd DPG gate circuit
End S, output end Q are respectively connected to the input terminal C of input terminal D, TOF gate circuit of the 3rd DPG gate circuit, and the described 3rd DPG
A2 end, B2 end of input terminal A, the input terminal B of circuit respectively as adder, output end S, the output end Q of the 3rd DPG gate circuit
It is respectively connected to the input terminal B of input terminal D, TOF gate circuit of the 4th DPG gate circuit, it is the input terminal A of the 4th DPG gate circuit, defeated
Enter to hold A3 end, B3 end of the B respectively as adder, output end S, the output end Q of the 4th DPG gate circuit are respectively connected to first
The output end T of input terminal A, the TOF gate circuit of input terminal C, TOF gate circuit of Fediken gate circuit is connected to the first Fediken
The input terminal A of gate circuit, the output end R of the first Fediken gate circuit are connected to the input terminal A of the 2nd Fediken gate circuit；
A4 end, B4 end of input terminal A, the input terminal B of the first HNG gate circuit respectively as adder, described first
Output end P, output end Q, output end R, the output end S of HNG gate circuit are respectively connected to the input terminal A of the 5th HNG gate circuit,
The input terminal B of five HNG gate circuits, the input terminal B of the 2nd Fediken gate circuit, the 2nd HNG gate circuit input terminal C, second
A5 end, B5 end of input terminal A, the input terminal B of HNG gate circuit respectively as adder, the output end P of the 2nd HNG gate circuit,
Output end Q, output end R, output end S are respectively connected to the input of the input terminal A, the 6th HNG gate circuit of the 6th HNG gate circuit
Hold the input terminal C of B, the input terminal B of the 3rd Fediken gate circuit, the 3rd HNG gate circuit, the input terminal of the 3rd HNG gate circuit
A, A6 end, B6 end of the input terminal B respectively as adder, it is the output end P of the 3rd HNG gate circuit, output end Q, output end R, defeated
Outlet S is respectively connected to the input terminal A of the 7th HNG gate circuit, the input terminal B of the 7th HNG gate circuit, the 4th Fediken electricity
The input terminal C of the input terminal B on road, the 4th HNG gate circuit, input terminal A, the input terminal B of the 4th HNG gate circuit are respectively as adding
The end A7, the end B7 of musical instruments used in a Buddhist or Taoist mass, output end P, output end Q, output end R, the output end S of the 4th HNG gate circuit are respectively connected to the 8th
The input terminal A of HNG gate circuit, the input terminal B of the 8th HNG gate circuit, the input terminal B of the 5th Fediken gate circuit, the 6th
The input terminal B of Fediken gate circuit, output end R, the output end S of the 5th HNG gate circuit are respectively connected to the 2nd Fediken
The input terminal C of the output end C of circuit, the 6th HNG gate circuit, output end R, the output end S of the 6th HNG gate circuit are separately connected
It is the output end R of the 7th HNG gate circuit, defeated to the input terminal C of the 3rd Fediken gate circuit, the input terminal C of the 7th HNG gate circuit
Outlet S is respectively connected to the input terminal C of the input terminal C of the 4th Fediken gate circuit, the 8th HNG gate circuit, the 8th HNG electricity
Output end R, the output end S on road be respectively connected to the input terminal C of the 5th Fediken gate circuit, the 6th Fediken gate circuit it is defeated
Enter and hold C, the output end P at S4 end of the output end Q of the 2nd Fediken gate circuit as adder, the 2nd Fediken gate circuit connects
It is connected to the input terminal A of the 3rd Fediken gate circuit, S5 end of the output end Q of the 3rd Fediken gate circuit as adder,
The output end P of 3rd Fediken gate circuit is connected to the input terminal A of the 4th Fediken gate circuit, the 4th Fediken gate circuit
S6 end of the output end Q as adder, the output end P of the 4th Fediken gate circuit is connected to the 5th Fediken gate circuit
Input terminal A, S7 end of the output end Q of the 5th Fediken gate circuit as adder, the output of the 5th Fediken gate circuit
End P is connected to the input terminal A of the 6th Fediken gate circuit, and the output end Q of the 6th Fediken gate circuit is as the defeated of adder
Outlet Co7.
Further, each Fediken gate circuit include the first transmission gate T1, the second transmission gate T2, third transmission gate T3,
4th transmission gate T4, the first phase inverter and the second phase inverter；The input terminal of first transmission gate T1 is defeated with the 4th transmission gate T4's
Enter end to be connected, and the input terminal B as Fediken gate circuit；The input terminal of first phase inverter respectively with the first transmission gate T1
Reverse Turning Control end, the positive control terminal of the second transmission gate T2, the Reverse Turning Control end of third transmission gate T3 and the 4th transmission gate
The positive control terminal of T4 is connected, and the input terminal A as Fediken gate circuit；The input terminal and third of second transmission gate T2 passes
The input terminal of defeated door is connected, and the input terminal C as Fediken gate circuit；The output end of first phase inverter is separately connected
It is passed to the positive control terminal of the first transmission gate T1, the Reverse Turning Control end of the second transmission gate T2, the input terminal of the second phase inverter, third
The positive control terminal of defeated door T3 and the Reverse Turning Control end of the 4th transmission gate T4；The output end conduct of second phase inverter
The output end P of Fediken gate circuit；The output end of first transmission gate T1 is connected with the output end of the second transmission gate T2, and conduct
The output end Q of Fediken gate circuit；The output end of third transmission gate T3 is connected with the output end of the 4th transmission gate T4, and conduct
The output end R of Fediken gate circuit.
Further, the TOF gate circuit includes the first transmission gate, the second transmission gate, the first phase inverter, the second reverse phase
Device, third phase inverter, the 4th phase inverter, the 5th phase inverter, first and door, second and door, third and door, XOR gate；Each with
The input of door includes the end A, the end B, the non-end A, and output is the end F；The input of the XOR gate includes the end A, the end B, is exported as F
End；The input terminal A of the TOF gate circuit is connected to the output end P of TOF gate circuit through the first transmission gate, the TOF gate circuit
Input terminal A is connected to the end B of first Yu door, and the input terminal B of the TOF gate circuit is respectively connected to the input of the first phase inverter
End, first with the end A of door, the output end of the first phase inverter is respectively connected to the input terminal of the second phase inverter, first non-with the A of door
End, the output end Q of the output end of second phase inverter as TOF gate circuit, described first and the end F of door be connected to third
With the end B of door, the input terminal C of TOF gate circuit is connected to the output end R of TOF gate circuit, the TOF electricity through the second transmission gate
The input terminal C on road is additionally coupled to the end B of second Yu door, and the input terminal D of TOF gate circuit is respectively connected to the input of third phase inverter
End, second with the end A of door, the output end of the third phase inverter is respectively connected to the input terminal of the 4th phase inverter, second and door
The non-end A, output end S of the output end of the 4th phase inverter as TOF gate circuit, described second is respectively connected to the end F of door
The end A of the input terminal of 5th phase inverter, third and door, the output end of the 5th phase inverter are connected to the non-end A of third and door, third
The end A of XOR gate is connected to the end F of door, the input terminal E of the TOF gate circuit is connected to the end B of XOR gate, the exclusive or
Output end T of the end F of door as TOF gate circuit.
Further, each DPG gate circuit include first with door, second with door, the first XOR gate, the second XOR gate,
Third XOR gate, the 4th XOR gate, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter,
And hex inverter；Each the input with door and each XOR gate includes the end A, the end B and the non-end A, and output is the end F；
The input terminal of first phase inverter as DPG input terminal A, the output end of the first phase inverter respectively with the second phase inverter
Input terminal, first are connected with the non-end A of the non-end the A of door, the first XOR gate, and the output end of the second phase inverter is defeated as DPG
Outlet P；First is connected to the input terminal of the first phase inverter with the end A of door, first with the end B of door as DPG input terminal B,
First is respectively connected to the input terminal at the end A of third XOR gate, third phase inverter, the output end of third phase inverter with the end F of door
It is connected to the non-end A of third XOR gate, the end F of third XOR gate is connected to the end B of the 4th XOR gate；The end A of first XOR gate
It is connected to the input terminal of the first phase inverter, the end B of the first XOR gate is connected to the end B of first Yu door, the end F point of the first XOR gate
Be not connected to the 4th phase inverter input terminal, second with the end A at the end A of door, the second XOR gate, the output end point of the 4th phase inverter
Be not connected to the 5th phase inverter input terminal, second with the non-end A at the non-end A of door, the second XOR gate, the output of the 5th phase inverter
Hold the output end Q as DPG；Second with the end B of door as DPG input terminal D, second and the end F of door be connected to third
The end B of XOR gate；The end B of second XOR gate is connected to the end B of second Yu door, and the end F of the second XOR gate is as DPG output
Hold R；The input terminal of hex inverter as DPG input terminal C and be connected to the end A of the 4th XOR gate, hex inverter
Output end is connected to the non-end A of the 4th XOR gate, and the output end of the 4th XOR gate is as DPG output end S.
Further, the FG gate circuit includes transmission gate, XOR gate；The input terminal of the XOR gate includes the end A, the end B,
The output end of the XOR gate is the end F；Described FG of input terminal A is connected to described FG of output end P through the transmission gate；
The end A of the XOR gate is connected to described FG of input terminal A, and the end B of the XOR gate is connected to FG of the input terminal
B, the end F of the XOR gate are connected to described FG of output end Q.
Further, each HNG gate circuit include first with door, second with door, the first XOR gate, the second XOR gate,
Third XOR gate, the 4th XOR gate, the first phase inverter, the second phase inverter, third phase inverter, transmission gate；First with door, second with
The input of door, the first XOR gate and the second XOR gate includes the end A, the end B, the non-end A, and output includes the end F；Third XOR gate
And the 4th the input of XOR gate include the end A, the end B, output includes the end F；The input terminal A of HNG gate circuit successively passes through
The input terminal B that one phase inverter, the second phase inverter are connected to output end P, the HNG gate circuit of HNG gate circuit is connected by transmission gate
To the output end Q of HNG gate circuit；First is connected to the input terminal of HNG gate circuit with the end A of door, the end A of the first XOR gate
A, first is connected to the input terminal B of HNG gate circuit with the end B at the end B of door, the first XOR gate, first with the non-end A of door, the
The non-end the A of one XOR gate is connected to the output end of the first phase inverter, and second is all connected with the end B of door, the end B of the second XOR gate
To the input terminal C of HNG gate circuit, first is connected to the end A of third XOR gate with the end F of door, and the first end XOR gate F is separately connected
To third phase inverter input terminal, second with the end A at the end A of door, the second XOR gate, the output end of third phase inverter is separately connected
To first and the non-end A at the non-end A of door, the second XOR gate, second is connected to the end B of third XOR gate with the end F of door, and second is different
Or output end R of the end F of door as HNG gate circuit, the end F of third XOR gate are connected to the end A of the 4th XOR gate, the 4th exclusive or
The end B of door is connected to the input terminal D, output end S of the end F of the 4th XOR gate as HNG gate circuit of HNG gate circuit.
Preferably, in the DPG gate circuit, HNG gate circuit, TOF gate circuit and FG gate circuit including one with door
A transmission gate and a transfer tube, the transmission gate include the first transistor and second transistor parallel with one another, two crystalline substances
The control terminal of body pipe respectively as with door the end A and the non-end A, two sys nodes respectively as with door the end B and the end F, wherein
Transistor controls end as the non-end A is connected to the control terminal of transfer tube, and the other both ends of the transfer tube are grounded respectively, meet F
End.
Preferably, the XOR gate in the DPG gate circuit and the first XOR gate in the HNG gate circuit, second different
Or door includes a transmission gate, the first transfer tube and the second transfer tube, the transmission gate includes the first crystalline substance parallel with one another
Body pipe and second transistor, the end A and the non-end A of the control terminals of two transistors respectively as XOR gate；The control of first transfer tube
The end B as XOR gate after end processed is connected with phase inverter, the drain electrode of the first transfer tube connect the end A, the source electrode of the first transfer tube and
The drain electrode of two transfer tubes is connected, and the control of the second transfer tube terminates the end B, and the source electrode of the second transfer tube connects the non-end A；The transmission gate
The sys node of two transistors is respectively connected to the source electrode of the first transfer tube, the end B, and the source electrode of first transfer tube is as different
Or the end output end F of door.
Preferably, third XOR gate, the 4th XOR gate in XOR gate, HNG gate circuit in the FG gate circuit and
XOR gate in TOF gate circuit includes the first transfer tube, the second transfer tube, third transfer tube, the 4th transfer tube；Described first
Transfer tube, third transfer tube, the 4th transfer tube are sequentially connected in series, and the inverted device of control terminal of first transfer tube is connected to described
The end A of XOR gate, the control terminal of the third transfer tube are connected to the end A of XOR gate, and the control terminal of the 4th transfer tube connects
It is connected to the end B of the XOR gate, the inverted device of control terminal of second transfer tube is respectively connected to the drain electrode of the first transfer tube
And the end B of the XOR gate, the drain electrode of second transfer tube are connected to the end A of the XOR gate, second transfer tube
Source electrode be connected with the source electrode of the first transfer tube and be connected to the end F of the XOR gate, the source electrode ground connection of the 4th transfer tube.
Transmission gate in foregoing circuit includes two switching tubes in parallel.
Compared with prior art, the invention has the following beneficial effects: the present invention realized using circuits such as transmission gates FG,
Fediken, TOF, the reversible logics gate circuit such as DPG and HNG, 8 two for realizing that carry bypass output is carry select into
The reciprocal circuit of adder processed, while can be realized and reduce rubbish output, constant input is reduced, and reduce reversible door number.
Detailed description of the invention
Fig. 1 is 8 binary adder schematic diagrams that the carry in background of invention bypasses that output is carry select.
Fig. 2 is that 4 carries of the embodiment of the present invention bypass adder reversible logic realization principle figure.
Fig. 3 is the reversible logic realization principle figure of 4 bit-serial adders of the embodiment of the present invention.
Fig. 4 is that the carry bypass output of the embodiment of the present invention is 8 binary adder reversible logics realities of carry select
Existing schematic diagram.
Fig. 5 is the Fediken gate circuit schematic diagram of the embodiment of the present invention.
Fig. 6 is the TOF gate circuit schematic diagram of the embodiment of the present invention.
Fig. 7 is the DPG gate circuit schematic diagram of the embodiment of the present invention.
Fig. 8 is the FG gate circuit schematic diagram of the embodiment of the present invention.
Fig. 9 is the HNG gate circuit schematic diagram of the embodiment of the present invention.
Figure 10 be in the DPG gate circuit of the embodiment of the present invention, HNG gate circuit, TOF gate circuit and FG gate circuit with
Gate circuit schematic diagram.
Figure 11 is first in XOR gate and the HNG gate circuit in the DPG gate circuit of the embodiment of the present invention
XOR gate, the second NOR gate circuit schematic diagram.
Figure 12 is the XOR gate in the FG gate circuit of the embodiment of the present invention, the third XOR gate in HNG gate circuit, the
NOR gate circuit schematic diagram in four XOR gates and TOF gate circuit.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings and embodiments.
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
In the present embodiment, the schematic diagram that 4 carry bypass adder reversible logic gates are realized is as shown in Fig. 2, to subtract
Few rubbish position and reversible logic gate number bypass algorithm according to carry, and for one-bit full addres using the DPG door of 4 input, 4 output, it can
Generation and S, carry Co and carry propagation signal P；Alternative selector is using the Fediken door not needed plus rubbish position inputs；
It is reversible set logic meter be not allow for be fanned out to, and lowest order carry Ci, 0 there are two being fanned out to, use FG when input B is 0
It carries out duplication and generates two identical outputs.
Control signal BP=P0P1P2P3 is 4 inputs and door, and to optimize reversible logic circuits, reduction rubbish bits number can
4 inputs and door are realized using the TOF reversible logic gate of 5 input, 5 output, its function can be described with following formula:
When E be 0 when, output T realize 4 input mutually with.It is mapping relations one by one that the reversible logic, which is output and input, and only
1 input rubbish position and 4 output rubbish positions, while logic gate number can be reduced.
The circuit diagram of 4 bit-serial adders is as shown in Figure 3.The C-terminal of leftmost one HNG connects 0, indicates to assume
When the carry digit of Co3 is 0 find out and the case where S4 '-S7 ' and carry Co7 '.
As shown in figure 4, it is electric for the reversible logic adder of carry select to present embodiments provide a kind of carry bypass output
Road, including FG gate circuit, TOF gate circuit, the first DPG gate circuit, the 2nd DPG gate circuit, the 3rd DPG gate circuit, the 4th DPG
Circuit, the first HNG gate circuit, the 2nd HNG gate circuit, the 3rd HNG gate circuit, the 4th HNG gate circuit, the 5th HNG gate circuit,
6th HNG gate circuit, the 7th HNG gate circuit, the 8th HNG gate circuit, the first Fediken gate circuit, the 2nd Fediken electricity
Road, the 3rd Fediken gate circuit, the 4th Fediken gate circuit, the 5th Fediken gate circuit and the 6th Fediken electricity
Road；The input of the adder includes the end Cin, the end A0, the end B0, the end A1, the end B1, the end A2, the end B2, the end A3, the end B3, the end A4, B4
End, the end A5, the end B5, the end A6, the end B6, the end A7 and the end B7；The output of the adder includes the end Co7, the end S0, the end S1, S2
End, the end S3, the end S4, the end S5, the end S6 and the end S7；
Each HNG gate circuit and each DPG gate circuit include input terminal A, input terminal B, input terminal C, input terminal D, defeated
Outlet P, output end Q, output end R and output end S；The TOF gate circuit includes input terminal A, input terminal B, input terminal C, defeated
Enter to hold D, input terminal E, output end P, output end Q, output end R, output end S and output end T；The FG gate circuit includes defeated
Enter to hold A, input terminal B, output end P, output end Q；The Fediken gate circuit include input terminal A, input terminal B, input terminal C,
Output end P, output end Q and output end R；
Cin end of the input terminal A of the FG gate circuit as the adder, the output end P of the FG gate circuit, output
End Q is respectively connected to the input terminal B of the input terminal D of the first DPG gate circuit, the first Fediken gate circuit, and the described first DPG
A0 end, B0 end of input terminal A, the input terminal B of circuit respectively as adder, the output end R conduct of the first DPG gate circuit
The end S0 of adder, output end Q, the output end S of the first DPG gate circuit are respectively connected to the input terminal D of TOF gate circuit,
The input terminal D of the 2nd DPG gate circuit, input terminal A, the input terminal B of the 2nd DPG gate circuit are respectively as adder
The end A1, the end B1, S1 end of the output end R of the 2nd DPG gate circuit as adder, the output of the 2nd DPG gate circuit
End S, output end Q are respectively connected to the input terminal C of input terminal D, TOF gate circuit of the 3rd DPG gate circuit, and the described 3rd DPG
A2 end, B2 end of input terminal A, the input terminal B of circuit respectively as adder, output end S, the output end Q of the 3rd DPG gate circuit
It is respectively connected to the input terminal B of input terminal D, TOF gate circuit of the 4th DPG gate circuit, it is the input terminal A of the 4th DPG gate circuit, defeated
Enter to hold A3 end, B3 end of the B respectively as adder, output end S, the output end Q of the 4th DPG gate circuit are respectively connected to first
The output end T of input terminal A, the TOF gate circuit of input terminal C, TOF gate circuit of Fediken gate circuit is connected to the first Fediken
The input terminal A of gate circuit, the output end R of the first Fediken gate circuit are connected to the input terminal A of the 2nd Fediken gate circuit；
A4 end, B4 end of input terminal A, the input terminal B of the first HNG gate circuit respectively as adder, described first
Output end P, output end Q, output end R, the output end S of HNG gate circuit are respectively connected to the input terminal A of the 5th HNG gate circuit,
The input terminal B of five HNG gate circuits, the input terminal B of the 2nd Fediken gate circuit, the 2nd HNG gate circuit input terminal C, second
A5 end, B5 end of input terminal A, the input terminal B of HNG gate circuit respectively as adder, the output end P of the 2nd HNG gate circuit,
Output end Q, output end R, output end S are respectively connected to the input of the input terminal A, the 6th HNG gate circuit of the 6th HNG gate circuit
Hold the input terminal C of B, the input terminal B of the 3rd Fediken gate circuit, the 3rd HNG gate circuit, the input terminal of the 3rd HNG gate circuit
A, A6 end, B6 end of the input terminal B respectively as adder, it is the output end P of the 3rd HNG gate circuit, output end Q, output end R, defeated
Outlet S is respectively connected to the input terminal A of the 7th HNG gate circuit, the input terminal B of the 7th HNG gate circuit, the 4th Fediken electricity
The input terminal C of the input terminal B on road, the 4th HNG gate circuit, input terminal A, the input terminal B of the 4th HNG gate circuit are respectively as adding
The end A7, the end B7 of musical instruments used in a Buddhist or Taoist mass, output end P, output end Q, output end R, the output end S of the 4th HNG gate circuit are respectively connected to the 8th
The input terminal A of HNG gate circuit, the input terminal B of the 8th HNG gate circuit, the input terminal B of the 5th Fediken gate circuit, the 6th
The input terminal B of Fediken gate circuit, output end R, the output end S of the 5th HNG gate circuit are respectively connected to the 2nd Fediken
The input terminal C of the output end C of circuit, the 6th HNG gate circuit, output end R, the output end S of the 6th HNG gate circuit are separately connected
It is the output end R of the 7th HNG gate circuit, defeated to the input terminal C of the 3rd Fediken gate circuit, the input terminal C of the 7th HNG gate circuit
Outlet S is respectively connected to the input terminal C of the input terminal C of the 4th Fediken gate circuit, the 8th HNG gate circuit, the 8th HNG electricity
Output end R, the output end S on road be respectively connected to the input terminal C of the 5th Fediken gate circuit, the 6th Fediken gate circuit it is defeated
Enter and hold C, the output end P at S4 end of the output end Q of the 2nd Fediken gate circuit as adder, the 2nd Fediken gate circuit connects
It is connected to the input terminal A of the 3rd Fediken gate circuit, S5 end of the output end Q of the 3rd Fediken gate circuit as adder,
The output end P of 3rd Fediken gate circuit is connected to the input terminal A of the 4th Fediken gate circuit, the 4th Fediken gate circuit
S6 end of the output end Q as adder, the output end P of the 4th Fediken gate circuit is connected to the 5th Fediken gate circuit
Input terminal A, S7 end of the output end Q of the 5th Fediken gate circuit as adder, the output of the 5th Fediken gate circuit
End P is connected to the input terminal A of the 6th Fediken gate circuit, and the output end Q of the 6th Fediken gate circuit is as the defeated of adder
Outlet Co7.
As shown in figure 5, in the present embodiment, each Fediken gate circuit includes the first transmission gate T1, the second transmission gate
T2, third transmission gate T3, the 4th transmission gate T4, the first phase inverter and the second phase inverter；The input terminal of first transmission gate T1 with
The input terminal of 4th transmission gate T4 is connected, and the input terminal B as Fediken gate circuit；The input terminal of first phase inverter is distinguished
With the Reverse Turning Control end of the first transmission gate T1, the positive control terminal of the second transmission gate T2, third transmission gate T3 Reverse Turning Control end,
And the 4th the positive control terminal of transmission gate T4 be connected, and the input terminal A as Fediken gate circuit；Second transmission gate T2's
Input terminal is connected with the input terminal of third transmission gate, and the input terminal C as Fediken gate circuit；First phase inverter
Output end is respectively connected to the positive control terminal of the first transmission gate T1, the Reverse Turning Control end of the second transmission gate T2, the second phase inverter
Input terminal, the positive control terminal of third transmission gate T3 and the Reverse Turning Control end of the 4th transmission gate T4；Second phase inverter
Output end P of the output end as Fediken gate circuit；The output end of the output end of first transmission gate T1 and the second transmission gate T2
It is connected, and the output end Q as Fediken gate circuit；The output end of third transmission gate T3 and the output end of the 4th transmission gate T4
It is connected, and the output end R as Fediken gate circuit.
As shown in fig. 6, in the present embodiment, the TOF gate circuit includes the first transmission gate, the second transmission gate, first anti-
Phase device, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, first and door, second and door, third and door,
XOR gate；It each include the end A, the end B, the non-end A with the input of door, output is the end F；The input of the XOR gate include the end A,
The end B exports as the end F；The input terminal A of the TOF gate circuit is connected to the output end P of TOF gate circuit through the first transmission gate, described
The input terminal A of TOF gate circuit is connected to the end B of first Yu door, and it is anti-that the input terminal B of the TOF gate circuit is respectively connected to first
The input terminal of phase device, first with the end A of door, the output end of the first phase inverter is respectively connected to the input terminal of the second phase inverter, the
One with the non-end A of door, the output end Q of the output end of second phase inverter as TOF gate circuit, described first and door the end F
It is connected to the end B of third and door, the input terminal C of TOF gate circuit is connected to the output end R of TOF gate circuit through the second transmission gate,
The input terminal C of the TOF gate circuit is additionally coupled to the end B of second Yu door, and the input terminal D of TOF gate circuit is respectively connected to third
The input terminal of phase inverter, second with the end A of door, the output end of the third phase inverter is respectively connected to the input of the 4th phase inverter
End, second with the non-end A of door, output end S of the output end of the 4th phase inverter as TOF gate circuit, described second and door the end F
It is respectively connected to the input terminal of the 5th phase inverter, the end A of third and door, the output end of the 5th phase inverter is connected to third and door
The end F of the non-end A, third and door is connected to the end A of XOR gate, and the input terminal E of the TOF gate circuit is connected to the end B of XOR gate,
Output end T of the end F of the XOR gate as TOF gate circuit.Wherein 5 input TOF can describe its function with following formula: F (P,
Q, R, S, T)=(A, B, C, D, ABCD ⊕ E).
As shown in fig. 7, in the present embodiment, each DPG gate circuit includes first and door, second and door, the first exclusive or
Door, the second XOR gate, third XOR gate, the 4th XOR gate, the first phase inverter, the second phase inverter, third phase inverter, the 4th reverse phase
Device, the 5th phase inverter and hex inverter；It include each the end A, the end B and A non-with the input of door and each XOR gate
End, output is the end F；The input terminal of first phase inverter is as DPG input terminal A, the output end point of the first phase inverter
Be not connected with the input terminal of the second phase inverter, first with the non-end A of the non-end the A of door, the first XOR gate, the second phase inverter it is defeated
Outlet is as DPG output end P；First is connected to the input terminal of the first phase inverter with the end A of door, and first makees with the end B of door
For DPG input terminal B, first is respectively connected to the input terminal at the end A of third XOR gate, third phase inverter with the end F of door, the
The output end of three phase inverters is connected to the non-end A of third XOR gate, and the end F of third XOR gate is connected to the end B of the 4th XOR gate；
The end A of first XOR gate is connected to the input terminal of the first phase inverter, and the end B of the first XOR gate is connected to the end B of first Yu door, the
The end F of one XOR gate be respectively connected to the input terminal of the 4th phase inverter, second with the end A at the end A of door, the second XOR gate, the 4th
The output end of phase inverter is respectively connected to the non-end A at the non-end A of the input terminal of the 5th phase inverter, second and door, the second XOR gate,
The output end of 5th phase inverter is as DPG output end Q；Second with the end B of door as DPG input terminal D, second and
The end F of door is connected to the end B of third XOR gate；The end B of second XOR gate is connected to the end B of second Yu door, the F of the second XOR gate
Hold the output end R as DPG；The input terminal of hex inverter as DPG input terminal C and be connected to the 4th XOR gate
The end A, the output end of hex inverter are connected to the non-end A of the 4th XOR gate, and the output end of the 4th XOR gate is defeated as DPG
Outlet S.
As shown in figure 8, in the present embodiment, the FG gate circuit includes transmission gate, XOR gate；The input of the XOR gate
End includes the end A, the end B, and the output end of the XOR gate is the end F；Described FG of input terminal A is connected to institute through the transmission gate
State FG output end P；The end A of the XOR gate is connected to described FG of input terminal A, and the end B of the XOR gate is connected to
Described FG of input terminal B, the end F of the XOR gate are connected to described FG of output end Q.
As shown in figure 9, in the present embodiment, each HNG gate circuit includes first and door, second and door, the first exclusive or
Door, the second XOR gate, third XOR gate, the 4th XOR gate, the first phase inverter, the second phase inverter, third phase inverter, transmission gate；
First with door, second includes the end A, the end B, the non-end A with the input of door, the first XOR gate and the second XOR gate, and output is wrapped
Include the end F；The input of third XOR gate and the 4th XOR gate includes the end A, the end B, and output includes the end F；HNG gate circuit it is defeated
Enter to hold A successively to pass through the first phase inverter, the second phase inverter be connected to HNG gate circuit output end P, HNG gate circuit input terminal B
The output end Q of HNG gate circuit is connected to by transmission gate；First is connected to HNG with the end A of door, the end A of the first XOR gate
The input terminal A of gate circuit, first is connected to the input terminal B of HNG gate circuit with the end B of door, the end B of the first XOR gate, and first
Be connected to the output end of the first phase inverter with the non-end A of door, the non-end A of the first XOR gate, second with the end B of door, second different
Or the end B of door is connected to the input terminal C of HNG gate circuit, first is connected to the end A of third XOR gate with the end F of door, and first is different
Or the end door F is respectively connected to the end A at the end A of the input terminal of third phase inverter, second and door, the second XOR gate, third phase inverter
Output end be respectively connected to the non-end A of first with the non-end A of door, the second XOR gate, second with the end F of door to be connected to third different
Or the end B of door, output end R of the end F of the second XOR gate as HNG gate circuit, it is different that the end F of third XOR gate is connected to the 4th
Or the end A of door, the end B of the 4th XOR gate are connected to the input terminal D of HNG gate circuit, the end F of the 4th XOR gate is as HNG electricity
The output end S on road.
As shown in Figure 10, in the present embodiment, preferably, the DPG gate circuit, HNG gate circuit, TOF gate circuit and
In FG gate circuit includes a transmission gate and a transfer tube with door, and the transmission gate includes the first crystalline substance parallel with one another
Body pipe and second transistor, the control terminal of two transistors is respectively as the end A and the non-end A with door, two sys node difference
As the end B and the end F with door, wherein the transistor controls end as the non-end A is connected to the control terminal of transfer tube, the transfer tube
Other both ends be grounded respectively, connect the end F.
As shown in figure 11, in the present embodiment, preferably, XOR gate in the DPG gate circuit and the HNG electricity
The first XOR gate, the second XOR gate in road include a transmission gate, the first transfer tube and the second transfer tube, the biography
Defeated door includes the first transistor and second transistor parallel with one another, the A of the control terminals of two transistors respectively as XOR gate
End and the non-end A；The end B as XOR gate after the control terminal of first transfer tube is connected with phase inverter, the drain electrode of the first transfer tube meet A
End, the source electrode of the first transfer tube are connected with the drain electrode of the second transfer tube, and the control of the second transfer tube terminates the end B, the second transfer tube
Source electrode connects the non-end A；The sys node of two transistors of the transmission gate is respectively connected to the source electrode of the first transfer tube, the end B, institute
State output end F end of the source electrode as XOR gate of the first transfer tube.
As shown in figure 12, in the present embodiment, preferably, in XOR gate, HNG gate circuit in the FG gate circuit
XOR gate in three XOR gates, the 4th XOR gate and TOF gate circuit includes the first transfer tube, the second transfer tube, third biography
Defeated pipe, the 4th transfer tube；First transfer tube, third transfer tube, the 4th transfer tube are sequentially connected in series, first transfer tube
The inverted device of control terminal is connected to the end A of the XOR gate, and the control terminal of the third transfer tube is connected to the end A of XOR gate,
The control terminal of 4th transfer tube is connected to the end B of the XOR gate, the inverted device of control terminal point of second transfer tube
It is not connected to the drain electrode of the first transfer tube and the end B of the XOR gate, the drain electrode of second transfer tube is connected to described different
Or the end A of door, the source electrode of second transfer tube are connected with the source electrode of the first transfer tube and are connected to the end F of the XOR gate,
The source electrode of 4th transfer tube is grounded.
Transmission gate in foregoing circuit includes two switching tubes in parallel.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with
Modification, is all covered by the present invention.
Claims (6)
1. the reversible logic adder circuit that a kind of bypass output of carry is carry select, it is characterised in that: including FG gate circuit,
TOF gate circuit, the first DPG gate circuit, the 2nd DPG gate circuit, the 3rd DPG gate circuit, the 4th DPG gate circuit, the first HNG electricity
Road, the 2nd HNG gate circuit, the 3rd HNG gate circuit, the 4th HNG gate circuit, the 5th HNG gate circuit, the 6th HNG gate circuit, the 7th
HNG gate circuit, the 8th HNG gate circuit, the first Fediken gate circuit, the 2nd Fediken gate circuit, the 3rd Fediken electricity
Road, the 4th Fediken gate circuit, the 5th Fediken gate circuit and the 6th Fediken gate circuit；The input of the adder
Including the end Cin, the end A0, the end B0, the end A1, the end B1, the end A2, the end B2, the end A3, the end B3, the end A4, the end B4, the end A5, the end B5, the end A6, B6
End, the end A7 and the end B7；The output of the adder includes the end Co7, the end S0, the end S1, the end S2, the end S3, the end S4, the end S5, S6
End and the end S7；
Each HNG gate circuit and each DPG gate circuit include input terminal A, input terminal B, input terminal C, input terminal D, output end
P, output end Q, output end R and output end S；The TOF gate circuit includes input terminal A, input terminal B, input terminal C, input terminal
D, input terminal E, output end P, output end Q, output end R, output end S and output end T；The FG gate circuit includes input terminal
A, input terminal B, output end P, output end Q；The Fediken gate circuit includes input terminal A, input terminal B, input terminal C, output end
P, output end Q and output end R；
Cin end of the input terminal A of the FG gate circuit as the adder, output end P, the output end Q of the FG gate circuit
It is respectively connected to the input terminal D of the first DPG gate circuit, the input terminal B of the first Fediken gate circuit, the first DPG gate circuit
The end A0, the end B0 respectively as adder input terminal A, input terminal B, the output end R of the first DPG gate circuit is as addition
The end S0 of device, output end Q, the output end S of the first DPG gate circuit are respectively connected to the input terminal D of TOF gate circuit, described
The A1 of the input terminal D of 2nd DPG gate circuit, input terminal A, the input terminal B of the 2nd DPG gate circuit respectively as adder
End, the end B1, S1 end of the output end R of the 2nd DPG gate circuit as adder, the output end of the 2nd DPG gate circuit
S, output end Q is respectively connected to the input terminal C of input terminal D, TOF gate circuit of the 3rd DPG gate circuit, the described 3rd DPG electricity
A2 end, B2 end of input terminal A, the input terminal B on road respectively as adder, output end S, output end Q points of the 3rd DPG gate circuit
It is not connected to the input terminal B of input terminal D, TOF gate circuit of the 4th DPG gate circuit, the input terminal A of the 4th DPG gate circuit, input
A3 end, B3 end of the B respectively as adder are held, output end S, the output end Q of the 4th DPG gate circuit are respectively connected to first
The output end T of input terminal A, the TOF gate circuit of input terminal C, TOF gate circuit of Fediken gate circuit is connected to the first Fediken
The input terminal A of gate circuit, the output end R of the first Fediken gate circuit are connected to the input terminal A of the 2nd Fediken gate circuit；
A4 end, B4 end of input terminal A, the input terminal B of the first HNG gate circuit respectively as adder, the described first HNG
Output end P, output end Q, output end R, the output end S of circuit are respectively connected to the input terminal A of the 5th HNG gate circuit, the 5th HNG
The input terminal B of gate circuit, the input terminal B of the 2nd Fediken gate circuit, the 2nd HNG gate circuit input terminal C, the 2nd HNG electricity
A5 end, B5 end of input terminal A, the input terminal B on road respectively as adder, the output end P of the 2nd HNG gate circuit, output end Q,
Output end R, output end S are respectively connected to the input terminal A of the 6th HNG gate circuit, the input terminal B of the 6th HNG gate circuit, third
The input terminal C, input terminal A, the input terminal B of the 3rd HNG gate circuit of the input terminal B of Fediken gate circuit, the 3rd HNG gate circuit
The end A6, the end B6 respectively as adder, the output end P of the 3rd HNG gate circuit, output end Q, output end R, output end S difference
It is connected to the input terminal of the input terminal A of the 7th HNG gate circuit, the input terminal B of the 7th HNG gate circuit, the 4th Fediken gate circuit
B, the input terminal C of the 4th HNG gate circuit, input terminal A, the input terminal B of the 4th HNG gate circuit respectively as adder the end A7,
The end B7, output end P, output end Q, output end R, the output end S of the 4th HNG gate circuit are respectively connected to the 8th HNG gate circuit
Input terminal A, the input terminal B of the 8th HNG gate circuit, the input terminal B of the 5th Fediken gate circuit, the 6th Fediken gate circuit
Input terminal B, output end R, the output end S of the 5th HNG gate circuit are respectively connected to the output end C of the 2nd Fediken gate circuit,
The input terminal C of six HNG gate circuits, output end R, the output end S of the 6th HNG gate circuit are respectively connected to the 3rd Fediken electricity
The input terminal C of the input terminal C on road, the 7th HNG gate circuit, output end R, the output end S of the 7th HNG gate circuit are respectively connected to
The input terminal C of the input terminal C of four Fediken gate circuits, the 8th HNG gate circuit, output end R, the output end of the 8th HNG gate circuit
S is respectively connected to the input terminal C of the input terminal C of the 5th Fediken gate circuit, the 6th Fediken gate circuit, the 2nd Fediken
S4 end of the output end Q of gate circuit as adder, the output end P of the 2nd Fediken gate circuit are connected to the 3rd Fediken
The end S5 of the input terminal A of circuit, the output end Q of the 3rd Fediken gate circuit as adder, the 3rd Fediken gate circuit
Output end P is connected to the input terminal A of the 4th Fediken gate circuit, and the output end Q of the 4th Fediken gate circuit is as adder
The end S6, the output end P of the 4th Fediken gate circuit is connected to the input terminal A of the 5th Fediken gate circuit, the 5th Fediken
S7 end of the output end Q of gate circuit as adder, the output end P of the 5th Fediken gate circuit are connected to the 6th Fediken
The output end Co7 of the input terminal A of circuit, the output end Q of the 6th Fediken gate circuit as adder.
2. a kind of carry bypass output according to claim 1 is the reversible logic adder circuit of carry select, special
Sign is: each Fediken gate circuit includes the first transmission gate T1, the second transmission gate T2, third transmission gate T3, the 4th transmission gate
T4, the first phase inverter and the second phase inverter；The input terminal of first transmission gate T1 is connected with the input terminal of the 4th transmission gate T4,
And the input terminal B as Fediken gate circuit；The input terminal of the first phase inverter Reverse Turning Control with the first transmission gate T1 respectively
End, the positive control terminal of the second transmission gate T2, the Reverse Turning Control end of third transmission gate T3 and the positive of the 4th transmission gate T4 are controlled
End processed is connected, and the input terminal A as Fediken gate circuit；The input of the input terminal and third transmission gate of second transmission gate T2
End is connected, and the input terminal C as Fediken gate circuit；The output end of first phase inverter is respectively connected to the first transmission
The door positive control terminal of T1, the Reverse Turning Control end of the second transmission gate T2, the input terminal of the second phase inverter, third transmission gate T3 are just
To control terminal and the Reverse Turning Control end of the 4th transmission gate T4；The output end of second phase inverter is as Fediken gate circuit
Output end P；The output end of first transmission gate T1 is connected with the output end of the second transmission gate T2, and as Fediken gate circuit
Output end Q；The output end of third transmission gate T3 is connected with the output end of the 4th transmission gate T4, and as Fediken gate circuit
Output end R.
3. a kind of carry bypass output according to claim 1 is the reversible logic adder circuit of carry select, special
Sign is: the TOF gate circuit includes the first transmission gate, the second transmission gate, the first phase inverter, the second phase inverter, third reverse phase
Device, the 4th phase inverter, the 5th phase inverter, first and door, second and door, third and door, XOR gate；Each wrapped with the input of door
The end A, the end B, the non-end A are included, output is the end F；The input of the XOR gate includes the end A, the end B, is exported as the end F；The TOF electricity
The input terminal A on road is connected to the output end P of TOF gate circuit through the first transmission gate, and the input terminal A of the TOF gate circuit is connected to
First with the end B of door, the input terminal B of the TOF gate circuit be respectively connected to the input terminal of the first phase inverter, first with the A of door
End, the output end of the first phase inverter are respectively connected to the non-end A of the input terminal of the second phase inverter, first and door, and described second is anti-
Output end Q of the output end of phase device as TOF gate circuit, described first is connected to the end B of third and door with the end F of door, and TOF
The input terminal C of circuit is connected to the output end R of TOF gate circuit through the second transmission gate, and the input terminal C of the TOF gate circuit also connects
It is connected to the end B of second Yu door, the input terminal D of TOF gate circuit is respectively connected to the A of the input terminal of third phase inverter, second and door
End, the output end of the third phase inverter are respectively connected to the non-end A of the input terminal of the 4th phase inverter, second and door, and the 4th is anti-
Output end S of the output end of phase device as TOF gate circuit, described second is respectively connected to the defeated of the 5th phase inverter with the end F of door
Enter the end A of end, third and door, the output end of the 5th phase inverter is connected to the non-end A of third and door, the end the F connection of third and door
To the end A of XOR gate, the input terminal E of the TOF gate circuit is connected to the end B of XOR gate, and the end F of the XOR gate is as TOF
The output end T of gate circuit.
4. a kind of carry bypass output according to claim 1 is the reversible logic adder circuit of carry select, special
Sign is: each DPG gate circuit include first with door, second with door, the first XOR gate, the second XOR gate, third XOR gate,
4th XOR gate, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter and the 6th are anti-
Phase device；Each the input with door and each XOR gate includes the end A, the end B and the non-end A, and output is the end F；Described first is anti-
The input terminal of phase device as DPG input terminal A, the output end of the first phase inverter respectively with the input terminal of the second phase inverter,
One is connected with the non-end A of the non-end the A of door, the first XOR gate, and the output end of the second phase inverter is as DPG output end P；First
Be connected to the input terminal of the first phase inverter with the end A of door, first with the end B of door as DPG input terminal B, first and door F
End is respectively connected to the input terminal at the end A of third XOR gate, third phase inverter, and it is different that the output end of third phase inverter is connected to third
Or the non-end A of door, the end F of third XOR gate are connected to the end B of the 4th XOR gate；It is anti-that the end A of first XOR gate is connected to first
The input terminal of phase device, the end B of the first XOR gate are connected to the end B of first Yu door, and the end F of the first XOR gate is respectively connected to the 4th
The input terminal of phase inverter, second with the end A at the end A of door, the second XOR gate, the output end of the 4th phase inverter is respectively connected to the 5th
The input terminal of phase inverter, second with the non-end A at the non-end A of door, the second XOR gate, the output end of the 5th phase inverter is as DPG
Output end Q；Second with the end B of door as DPG input terminal D, second and the end F of door be connected to the end B of third XOR gate；
The end B of second XOR gate is connected to the end B of second Yu door, and the end F of the second XOR gate is as DPG output end R；6th reverse phase
The input terminal of device as DPG input terminal C and be connected to the end A of the 4th XOR gate, the output end of hex inverter is connected to
The non-end A of 4th XOR gate, the output end of the 4th XOR gate is as DPG output end S.
5. a kind of carry bypass output according to claim 1 is the reversible logic adder circuit of carry select, special
Sign is: the FG gate circuit includes transmission gate, XOR gate；The input terminal of the XOR gate includes the end A, the end B, the XOR gate
Output end be the end F；Described FG of input terminal A is connected to described FG of output end P through the transmission gate；The XOR gate
The end A be connected to described FG of input terminal A, the end B of the XOR gate is connected to described FG of input terminal B, the exclusive or
The end F of door is connected to described FG of output end Q.
6. a kind of carry bypass output according to claim 1 is the reversible logic adder circuit of carry select, special
Sign is: each HNG gate circuit include first with door, second with door, the first XOR gate, the second XOR gate, third XOR gate,
4th XOR gate, the first phase inverter, the second phase inverter, third phase inverter, transmission gate；First with door, second with door, the first exclusive or
The input of door and the second XOR gate includes the end A, the end B, the non-end A, and output includes the end F；Third XOR gate and the 4th different
Or the input of door includes the end A, the end B, output includes the end F；The input terminal A of HNG gate circuit successively passes through the first phase inverter,
The input terminal B that two phase inverters are connected to output end P, the HNG gate circuit of HNG gate circuit is connected to HNG gate circuit by transmission gate
Output end Q；First is connected to the input terminal A of HNG gate circuit with the end A at the end A of door, the first XOR gate, first with the B of door
End, the first XOR gate the end B be connected to the input terminal B of HNG gate circuit, first is non-with the non-end A of door, the A of the first XOR gate
End is connected to the output end of the first phase inverter, and second is connected to HNG gate circuit with the end B of door, the end B of the second XOR gate
Input terminal C, first is connected to the end A of third XOR gate with the end F of door, and the first end XOR gate F is respectively connected to third phase inverter
Input terminal, second with the end A at the end A of door, the second XOR gate, the output end of third phase inverter is respectively connected to first and door
The non-end A, the second XOR gate the non-end A, second is connected to the end B of third XOR gate with the end F of door, and the end F of the second XOR gate is made
For the output end R of HNG gate circuit, the end F of third XOR gate is connected to the end A of the 4th XOR gate, the end the B connection of the 4th XOR gate
To the input terminal D of HNG gate circuit, output end S of the end F of the 4th XOR gate as HNG gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810801889.1A CN109032561B (en) | 2018-07-20 | 2018-07-20 | Reversible logic adder circuit with carry bypass output as carry selection |
Applications Claiming Priority (1)
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| CN110597485A (en) * | 2019-09-10 | 2019-12-20 | 北京嘉楠捷思信息技术有限公司 | Modular multi-bit adder and computing system |
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