CN206461580U

CN206461580U - Digital filtering equipment

Info

Publication number: CN206461580U
Application number: CN201720063501.3U
Authority: CN
Inventors: 周立功; 胡祀鹏
Original assignee: Guangzhou Zhiyuan Electronics Co Ltd
Current assignee: Guangzhou Zhiyuan Electronics Co Ltd
Priority date: 2017-01-17
Filing date: 2017-01-17
Publication date: 2017-09-01
Anticipated expiration: 2027-01-17

Abstract

The utility model is related to a kind of digital filtering equipment, including the CIC draw-out devices being sequentially connected, FIR filter and CIC interpolating apparatus, CIC draw-out devices are received after signal data to be filtered, multidiameter delay data can be obtained, extraction down coversion is carried out to multidiameter delay data by CIC draw-out devices, FIR filter is filtered to the signal after down coversion, row interpolation up-conversion is entered to filtered signal finally by CIC interpolating apparatus, by its frequency retrieval to the frequency of original signal data to be filtered, final filter result is obtained；This programme coordinates FIR filter coefficient can configure by primary frequency signal down coversion post filtering, then by filtered signal up-conversion to primary frequency, realizes and is filtered processing to the signal of optional frequency in high bandwidth；It using multidiameter delay structure, real-time to input data can handle (without first storing post processing), the Real-Time Filtering processing of high-bandwidth signals realized under less system clock.

Description

Digital filtering equipment

Technical field

The utility model is related to signal filtering technical field, more particularly to a kind of digital filtering equipment.

Background technology

In signal filtering field, generally require to complete to meet various designs using the digital filter of different cut-off frequencies It is required that.

At present, more conventional digital filter have based on FPGA (Field Programmable Gate Array, it is existing Field programmable logic array) Parallel Digital wave filter etc..

For the Parallel Digital wave filter based on FPGA, when the bandwidth of input signal is too high, it is necessary to which sample frequency can surpass System clock frequency is crossed, for example, when the bandwidth of input signal is more than 500 megahertzs, then sample frequency is greater than Gigahertz (from Sampling Theorem：Sample frequency need to be more than twice of signal highest frequency), the system clock frequency of current FPGA device Usually hundreds of megahertzs, so the Parallel Digital filter construction based on FPGA can not be completed at the filtering of high-bandwidth signals Reason.

Therefore, the above-mentioned Parallel Digital wave filter based on FPGA is poor to the filtering process effect of high-bandwidth signals.

Utility model content

Based on this, it is necessary to for filtering process of traditional Parallel Digital wave filter based on FPGA to high-bandwidth signals There is provided a kind of digital filtering equipment for the problem of effect is poor.

A kind of digital filtering equipment, including CIC draw-out devices, FIR filter and CIC interpolating apparatus；

The P of CIC draw-out devices_i1Individual input receives signal data to be filtered, wherein, P_i1For the integer more than 0；

The P of CIC draw-out devices_c1The P of individual output end and FIR filter_c1Individual input correspondence is connected, wherein, P_c1For more than 0 integer；

The P of FIR filter_c2Individual output end and the P of CIC interpolating apparatus_c2Individual input correspondence is connected, wherein, P_c2For more than 0 integer；

The P of CIC interpolating apparatus_i2Individual output end exports filtering data, wherein, P_i2For the integer more than 0.

According to above-mentioned digital filtering equipment of the present utility model, it includes CIC draw-out devices, the FIR filtering being sequentially connected Device and CIC interpolating apparatus, CIC draw-out devices are received after signal data to be filtered, can be obtained multidiameter delay data, be passed through CIC Draw-out device carries out extraction down coversion to multidiameter delay data, and FIR filter is filtered to the signal after down coversion, finally led to Cross CIC interpolating apparatus and row interpolation up-conversion is entered to filtered signal, by its frequency retrieval to original signal data to be filtered Frequency, obtains final filter result；This programme is by primary frequency signal down coversion post filtering, then by filtered signal up-conversion To primary frequency, FIR filter coefficient is coordinated to can configure, it is possible to achieve to be filtered place to the signal of optional frequency in high bandwidth Reason；Prime carries out down coversion using CIC draw-out devices in digital filtering equipment can be reduced because sample rate is not enough and causes Spectral aliasing, rear class carries out up-conversion using CIC interpolating apparatus can realize that anti-mirror image is filtered, with this can reduce up-conversion and The influence that down coversion is filtered to high-frequency signal；Meanwhile, using multidiameter delay structure, real-time to input data can handle (without First storage post processing), the Real-Time Filtering processing of high-bandwidth signals is realized under less system clock.

Brief description of the drawings

Fig. 1 is the structural representation of the digital filtering equipment of one of embodiment；

Fig. 2 (a) is the structural representation of the CIC draw-out devices of one of embodiment；

Fig. 2 (b) is the structural representation of the CIC draw-out devices of one of embodiment；

Fig. 3 (a) is the structural representation of the single-stage parallel C IC draw-out devices of one of embodiment；

Fig. 3 (b) is the structural representation of the single-stage parallel C IC draw-out devices of one of embodiment；

Fig. 3 (c) is the structural representation of the single-stage parallel C IC interpolating apparatus of one of embodiment；

Fig. 3 (d) is the structural representation of the single-stage parallel C IC interpolating apparatus of one of embodiment；

Fig. 4 is the structural representation of the parallel integration module of one of embodiment；

Fig. 5 is the structural representation of the parallel thin shape module of one of embodiment；

Fig. 6 (a) is the structural representation of the FIR filter of one of embodiment；

Fig. 6 (b) is the structural representation of the data distribution delay chain module of one of embodiment；

Fig. 7 is the data distribution delay chain module of one of embodiment and connecing for the parallel FIR filter of single-stage even-order Connect schematic diagram；

Fig. 8 is the data distribution delay chain module of one of embodiment and connecing for the parallel FIR filter of single-stage odd-order Connect schematic diagram；

Fig. 9 is the structural representation of the digital filtering equipment of one of embodiment；

Figure 10 is the structural representation of the digital filtering equipment of one of embodiment；

Figure 11 is the structural representation of the digital filtering equipment of one of embodiment；

Figure 12 is the application scenario diagram of the digital filtering equipment of one of embodiment.

Embodiment

For the purpose of this utility model, technical scheme and advantage is more clearly understood, below in conjunction with drawings and Examples, The utility model is described in further detail.It should be appreciated that embodiment described herein is only to solve The utility model is released, protection domain of the present utility model is not limited.

It is shown in Figure 1, it is the structural representation of digital filtering equipment of the present utility model.Numeral filter in the embodiment Wave device, including CIC draw-out devices 100, FIR filter 200 and CIC interpolating apparatus 300；CIC refers to that cascade integral dredges shape filter Ripple, FIR filter refers to there is limit for length's unit impact response wave filter；

The P of CIC draw-out devices 100_i1Individual input receives signal data to be filtered, wherein, P_i1For the integer more than 0；

The P of CIC draw-out devices 100_c1The P of individual output end and FIR filter 200_c1Individual input correspondence is connected, wherein, P_c1 For the integer more than 0；

The P of FIR filter 200_c2Individual output end and the P of CIC interpolating apparatus 300_c2Individual input correspondence is connected, wherein, P_c2 For the integer more than 0；

The P of CIC interpolating apparatus 300_i2Individual output end exports filtering data, wherein, P_i2For the integer more than 0.

In the present embodiment, digital filtering equipment, it includes CIC draw-out devices, FIR filter and the CIC being sequentially connected Interpolating apparatus, CIC draw-out devices are received after signal data to be filtered, can be obtained multidiameter delay data, be passed through CIC draw-out devices Extraction down coversion is carried out to multidiameter delay data, FIR filter is filtered to the signal after down coversion, inserted finally by CIC Value device enters row interpolation up-conversion to filtered signal, by its frequency retrieval to the frequency of original signal data to be filtered, obtains To final filter result；This programme is by primary frequency signal down coversion post filtering, then by filtered signal up-conversion to former frequency Rate, coordinates FIR filter coefficient can configure, it is possible to achieve to be filtered processing to the signal of optional frequency in high bandwidth；Numeral Prime carries out down coversion using CIC draw-out devices in filter apparatus can be reduced because the frequency spectrum that sample rate is not enough and causes is mixed Folded, rear class carries out up-conversion using CIC interpolating apparatus can realize that anti-mirror image is filtered, and up-conversion and down coversion can be reduced with this The influence filtered to high-frequency signal；Meanwhile, using multidiameter delay structure, real-time to input data it can handle (without first storing Post processing), the Real-Time Filtering processing of high-bandwidth signals is realized under less system clock.

It should be noted that the input input of CIC draw-out devices is data signal.Due to the utility model multiple parallel Structure can realize that the high speed of any bandwidth signal is real in the case of and resource limited in system operation clock permission in theory When filtering process.Assuming that simultaneously line number is P to input data_in, the utility model system operation clock frequency is f_sys, this practicality in addition Each module can realize processing input data in real time using pipeline organization in new, you can be inputted once in each system clock In data, each system clock cycle can input data amount be P_in, therefore the utility model can process signal maximum sample rate f_sFor：

f_s=f_sys×P_in

As long as increasing P_inThe maximum sample rate of energy process signal can just be increased, you can to increase the band of energy process signal It is wide.Certainly P is increased_inCan cause resource using increase, as long as so resource allow, no matter f_sysMore small (of course greater than 0) is as long as increase Big P_inThe filtering process of any frequency signal can be met.The use of common single parallel organization wave filter is that can not realize this characteristic 's.

It is preferred that, P_i1With P_i2With identical the data volume to be filtered of input can be made identical with the filtered data amount exported, The rear class processing of signal, P are not affected thereby using the utility model or bypass the utility model_c1With P_c2It is identical, filter FIR The input data amount of ripple device is identical with output data quantity, and the complete of signal is ensured after FIR filter is filtered processing to signal Whole property.

Optionally, P_i1、P_i2、P_c1With P_c2Can be 1, it is now actual for single parallel organization；P_i1、P_i2、P_c1With P_c2Can be with For the integer more than 1, now actual is multiple parallel structure.

In one of the embodiments, as shown in Fig. 2 (a), CIC draw-out devices 100 include output end, input and connected successively The N connect_cic1Individual single-stage parallel C IC draw-out devices the 110, the 1st to N_cic1- 1 single-stage parallel C IC draw-out device 110 is provided with P_i1 Individual input and P_i1Individual output end, N_cic1Individual single-stage parallel C IC draw-out devices 110 possess P_i1Individual input and P_c1Individual output End, the P of the 1st single-stage parallel C IC draw-out device 110_i1Individual input as CIC draw-out devices 100 P_i1Individual input, the N_cic1The P of individual single-stage parallel C IC draw-out devices 110_c1Individual output end as CIC draw-out devices 100 P_c1Individual output end；

As shown in Fig. 2 (b), the N that CIC interpolating apparatus 300 includes output end, input is sequentially connected_cic2Individual single-stage is parallel CIC interpolating apparatus the 310, the 1st to N_cic2- 1 single-stage parallel C IC interpolating apparatus 310 is provided with P_c2Individual input and P_c2Individual output End, N_cic2Individual single-stage parallel C IC interpolating apparatus 310 possesses P_c2Individual input and P_i2Individual output end；1st single-stage parallel C IC The P of interpolating apparatus 310_c2Individual input as CIC interpolating apparatus 300 P_c2Individual input, N_cic1Individual single-stage parallel C IC interpolation The P of device 310_i2Individual output end as CIC interpolating apparatus 300 P_i2Individual output end；

N_cic1、N_cic2It is the integer more than 0.

In the present embodiment, effect is preferably extracted in order to reach, parallel C IC draw-out devices usually require larger extraction Multiple, decimation factor and the extracting multiple positive correlation of parallel C IC draw-out devices, but when the extraction of a parallel C IC draw-out device When the factor is larger, the input data bit wide of parallel C IC draw-out devices is larger, resource occupation of the parallel C IC draw-out devices to system It is more, and the structure for using multiple single-stage parallel C IC draw-out devices to connect, the extracting multiple of parallel C IC draw-out devices is each The product of the extracting multiple of single-stage parallel C IC draw-out devices, can obtain larger extracting multiple with less decimation factor, It is simultaneously less to the resource occupation of system；After upper level single-stage parallel C IC draw-out devices are extracted, data are reduced, but in order to be able to Same extraction is performed in next stage single-stage parallel C IC draw-out devices, it is necessary to which the data after extraction are carried out into delayed allocation, is made Parallel output and the parallel input of next stage single-stage parallel C IC draw-out devices and line number is identical；

In order to reach preferable interpolation, parallel C IC interpolating apparatus usually requires larger interpolation multiple, parallel C IC The interpolation factor of interpolating apparatus and interpolation multiple positive correlation, but when the interpolation factor of a parallel C IC interpolating apparatus is larger, and Row CIC interpolating apparatus is more to the resource occupation of system, and the structure for using multiple single-stage parallel C IC interpolating apparatus to connect, and The interpolation multiple of row CIC interpolating apparatus is the product of the interpolation multiple of each single-stage parallel C IC interpolating apparatus, can be with less Interpolation factor obtains larger interpolation multiple, while less to the resource occupation of system；Upper level single-stage parallel C IC interpolation is filled Put after interpolation, data increase, but in order to be able to perform same interpolation in next stage single-stage parallel C IC interpolating apparatus, it is necessary to will The later data of interpolation carry out delayed allocation, make parallel output and the parallel input of next stage single-stage parallel C IC interpolating apparatus And line number is identical.

Optionally, the number N of single-stage parallel C IC draw-out devices_cic1With the number N of single-stage parallel C IC interpolating apparatus_cic2Can , can also be different with identical.

In one of the embodiments, as shown in Fig. 3 (a) and Fig. 3 (b), single-stage parallel C IC draw-out devices 110 include defeated Go out end, the N that is sequentially connected of input_i1Individual parallel integration module 112, paralleling abstracting module 114, N_c1Individual shape module 116 thin parallel And first gain regulation module 118, N_i1And N_c1It is the integer more than 0；

Each parallel integration module 112 possesses P_i1Individual input and P_i1Individual output end, paralleling abstracting module 114 possesses P_i1 Individual input and P_c1Individual output end, each shape module 116 thin parallel possesses P_c1Individual input and P_c1Individual output end；1st to N_cic1Each first gain regulation module 118 in -1 single-stage parallel C IC draw-out device 110 possesses P_c1Individual input and P_i1It is individual defeated Go out end, N_cic1The first gain regulation module in individual single-stage parallel C IC draw-out devices 110 possesses P_c1Individual input and P_c1It is individual defeated Go out end；

As shown in Fig. 3 (c) and Fig. 3 (d), single-stage parallel C IC interpolating apparatus 310 includes output end, input and is sequentially connected N_c2Individual shape module 312 thin parallel, parallel interpolation module 314, N_i2The individual Gain tuning mould of parallel integration module 316 and second Block 318；

Each shape module 312 thin parallel possesses P_c2Individual input and P_c2Individual output end, parallel interpolation module 314 possesses P_c2 Individual input and P_i2Individual output end, each parallel integration module 316 possesses P_i2Individual input and P_i2Individual output end；1st to N_cic2Each second gain regulation module 318 in -1 single-stage parallel C IC interpolating apparatus 310 possesses P_i2Individual input and P_c2It is individual defeated Go out end, N_cic2The second gain regulation module in individual single-stage parallel C IC interpolating apparatus 310 possesses P_i2Individual input and P_i2It is individual defeated Go out end.

In the present embodiment, single-stage parallel C IC draw-out devices include N_i1Individual parallel integration module, paralleling abstracting module, N_c1 Individual shape module thin parallel and the first gain regulation module, by such a annexation, can be carried out parallel to the signal of input Extract, and reduce due to the spectral aliasing that the possible caused sample rate of extraction is not enough and causes, parallel C IC abstraction modules are to letter Number there is gain amplification, therefore, need before output by the first gain regulation module, gain tune is carried out to signal It is whole；Moreover, in order to be able to make the processing that same and line number is performed in next stage single-stage parallel C IC draw-out devices, the first Gain tuning Module needs that later data progress delayed allocation will be extracted, and makes parallel output and next stage single-stage parallel C IC draw-out devices Parallel input correspondence；

Single-stage parallel C IC interpolating apparatus includes N_c2Individual shape module thin parallel, parallel interpolation module, N_i2Individual parallel integration mould Block and the second gain regulation module, by such a annexation, can carry out parallel interpolation, and realize to the signal of input The filtering of anti-mirror image, because parallel C IC interpolating modules play the role of gain amplification to signal, therefore, need before output by Second gain regulation module, Gain tuning is carried out to signal；It is same in order to be able to be performed in next stage single-stage parallel C IC interpolating apparatus Interpolation, the second gain regulation module needs the later data of interpolation carrying out delayed allocation, makes parallel output and next stage list The parallel input correspondence of level parallel C IC interpolating apparatus.

In one of the embodiments, as shown in figure 4, parallel integration module includes matrix of device [A_i,j], wherein, 1≤i ≤ p, 1≤j≤p, p are the parallel channel number of parallel integration module, and i, j, p are integer；

The device A of i-th row i-th -1 row_i,i-1The device A arranged with pth_i,pIt is adder, matrix of device [A_i,j] in it is remaining Device be storage delay register；

Matrix of device [A_i,j] in be sequentially connected per the device of a line, the adder A of the i-th row i-th -1 row_i,i-1It is sequentially connected；

Storage delay register A_1,1Input and adder A_2,1First input end connection, adder A_k,k-1Output End and adder A_k+1,kFirst input end connection, while adder A_k,k-1Output end and storage delay register A_k,kIt is defeated Enter end connection, wherein, 2≤k≤p-1, k is integer；

Storage delay register A_h,h-2Output end and adder A_h,h-1The second input connection, wherein, 3≤h≤p, H is integer；

Storage delay register A_g,p-1Output end and adder A_g,pThe second input connection, wherein, 1≤g≤p-1, G is integer, adder A_p,p-1Output end and adder A_p,pThe second input connection, adder A_p,pOutput end and addition Device A_i,pFirst input end connection；

The input of parallel integration module includes storage delay register A_1,1Input, adder A_2,1Second input End and storage delay register A_h,1Input, the output end of parallel integration module includes adder A_i,pOutput end；

Parallel integration module is parallel integration module 112 or parallel integration module 316.

In the present embodiment, parallel integration module is mainly realized by adder, is calculating the integration of a certain clock cycle As a result it is preceding, it is necessary to by before plus with result calculate and complete, integration structure to add up before data, this programme passes through device square Battle array mode is handled signal data, and storage delay register can export one clock cycle of data delay of storage, Adder can also postpone a clock cycle output after two input values are added, and first be added up in the preceding p-1 row of matrix of device each The value of level, present clock period result, last clock cycle are obtained in last row with upper clock cycle result phase Calais again Last data is the previous data that present clock period inputs first data in p data in p data of input, Need to wait last clock cycle input data to carry out the calculating of present clock period after the completion of calculating in theory, and it is our Structure used in case, it is first that present clock period input data is at different levels cumulative, when present clock period inputs at different levels added up The result of a upper clock cycle just calculates completion, and the accumulated value of present clock period input just can be with a upper clock Last result adds up in computation of Period result, obtains the integral result value of present clock period.In each clock cycle It is subjected to new data simultaneously to be handled, i.e., data can input processing in real time.

Optionally, the parallel channel number in parallel integration module 212 can with the parallel channel number in parallel integration module 416 , can also be different with identical；When parallel integration module is parallel integration module 212, parallel channel number p is P_i1；When parallel product When sub-module is parallel integration module 416, parallel channel number p is P_i2。

In one of the embodiments, as shown in figure 5, thin shape module includes q subtracter and a storage delay parallel Register, wherein, q is the parallel parallel channel number for dredging shape module；

The input of parallel thin shape module includes the first input end of all subtracters, the output end bag of parallel thin shape module Include the output end of all subtracters；

The first input end of r-th of subtracter is connected with second input of (r+1) individual subtracter；Wherein, 1≤r≤ Q-1, r, q are integer；

The first input end of q-th of subtracter is connected with the input of storage delay register, storage delay register Output end is connected with the second input of the 1st subtracter；

Thin shape module dredges shape module 116 or parallel thin shape module 312 to be parallel parallel.

In the present embodiment, thin shape module is mainly realized by subtracter parallel, the signal number of upper clock periodical input According to last data for present clock period input first data previous data, present clock period is inputted Each data and upper clock periodical input one clock cycle of last data delay after carry out making difference processing, to obtain The differentiation result value of current period.New data are subjected in each clock cycle and are handled, i.e., data can be real When input processing.

Optionally, the parallel channel number in parallel thin shape module 216 can with the parallel channel number in parallel thin shape module 412 , can also be different with identical；When parallel thin shape module is thin shape module 216 parallel, parallel channel number q is P_c1；Dredged when parallel When shape module is thin shape module 412 parallel, parallel channel number q is P_c2。

In one of the embodiments, as shown in Fig. 6 (a) and Fig. 6 (b), FIR filter 200 postpones including data distribution Chain module 210 and P_c2The individual parallel FIR filter 220 of single-stage；

Data distribution delay chain module 210 includes (N+P_c2- 1) the individual storage delay register being arranged in order, wherein, n-th The output end of individual storage delay register and (n+P_c1) individual storage delay register input connection, 1≤n≤N-1, n, N It is integer, N is the exponent number of the parallel FIR filter 220 of single-stage；

M is to the output end of (N+m-1) individual storage delay register and the input of the parallel FIR filter 220 of m-th of single-stage End correspondence connection, wherein, 1≤m≤P_c2, m is integer；

The input of FIR filter 200 includes the 1st to P_c1The input of individual storage delay register, FIR filter 200 Output end include the output end of the parallel FIR filter 220 of all single-stages.

In the present embodiment, a length of (N+P of the delay chain of data distribution delay chain module_c2- 1) individual data, each clock week Phase is from the 1st to P_c1Individual storage delay register inputs P_c1Individual data, in following clock cycle, the 1st to P_c1Individual storage delay deposit The data of device are moved to P_c1+ 1 to 2P_c1In individual storage delay register, m is exported in each clock cycle to (N+m-1) The data of individual storage delay register are to the parallel FIR filter of m-th of single-stage, and the mode similar to sliding window is exported, each The parallel FIR filter of single-stage can export a filter result, P in a clock cycle_c2The individual parallel FIR filter of single-stage is one The individual clock cycle can export P simultaneously_c2Individual filter result；Data are distributed in sliding window mode, it is possible to use less storage Delay time register realizes parallel filtering.

It is preferred that, the fan-in P of FIR filter 200_c1With the fan-out P of FIR filter 200_c2It is identical.

In one of the embodiments, it is single as shown in fig. 7, when the exponent number of the parallel FIR filter 220 of single-stage is even number The parallel FIR filter 220 of level includes N/2 adder, N/2 multiplier and an accumulator；

In the N number of storage delay register being arranged in order being connected with the parallel FIR filter of single-stage 220, s-th of storage is prolonged The output end of storage that delays in the dispatch of and the output end of (N+1-s) individual storage delay register are connected respectively to a corresponding adder Two inputs, wherein, 1≤s≤N, the input of the output end of each adder and a corresponding multiplier is connected, often The output end of individual multiplier is connected with the corresponding input of accumulator, and the output end of accumulator is the parallel FIR filter of single-stage 220 output end.

In the present embodiment, when the exponent number of the parallel FIR filter 220 of single-stage is even number, N/2 adder, N/2 are utilized Individual multiplier and an accumulator are that the filtering to one group of data can be achieved.

Optionally, accumulator can be adder tree or meet each clock cycle can multiple parallel input, output The parallel organization of one accumulation result.

In one of the embodiments, it is single as shown in figure 8, when the exponent number of the parallel FIR filter 220 of single-stage is odd number The parallel FIR filter 320 of level includes (N-1)/2 adder, delayer, (N+1)/2 multiplier and an accumulator；

In the N number of storage delay register being arranged in order being connected with the parallel FIR filter of single-stage 220, s-th of storage is prolonged The output end of storage that delays in the dispatch of and the output end of (N+1-s) individual storage delay register are connected respectively to a corresponding adder Two inputs, wherein, 1≤s≤N, the input of the output end of each adder and a corresponding multiplier is connected, the (N+1)/2 input connection of the output end of a storage delay register and delayer, the output end of delayer and corresponding one The input connection of individual multiplier, the corresponding input connection of the output end of each multiplier with accumulator, accumulator it is defeated Go out output end of the end for the parallel FIR filter 220 of single-stage.

In the present embodiment, when the exponent number of the parallel FIR filter 220 of single-stage is odd number, (N-1)/2 addition is utilized Device, delayer, (N+1)/2 multiplier and an accumulator are that the filtering to one group of data can be achieved, because exponent number is Odd number, one of storage delay register does not have corresponding adder to be attached thereto, and adder is when carrying out additional calculation Delay is had, accordingly, it would be desirable to the storage delay register is connected with delayer, while to ensure that each multiplier receives data Property.

In one of the embodiments, as shown in figure 9, digital filtering equipment also includes withdrawal device 400 and interpolater 500, Withdrawal device 400 is connected between the input of the output end of CIC draw-out devices 100 and FIR filter 200, and interpolater 500 is connected Between the delivery outlet of FIR filter 200 and the input of CIC interpolating apparatus 300.

In the present embodiment, withdrawal device can be used to carry out assisted codirectional CIC draw-out devices, general withdrawal device is directly to take out Mode is taken to be extracted, it is less to take resource, can be with taking out when causing inadequate resource using parallel C IC draw-out devices completely Device is taken to substitute part parallel CIC draw-out devices；Interpolater can be used to carry out assisted codirectional CIC interpolating apparatus, general interpolater is Row interpolation is entered in Direct interpolation mode, occupancy resource is less, when causing inadequate resource using parallel C IC interpolating apparatus completely, Part parallel CIC interpolating apparatus can be substituted with interpolater, rationally to utilize system resource.

Optionally, withdrawal device 400 possesses P_i1Individual input, P_c1Individual output end；Interpolater 500 possesses P_c2Individual input, P_i2 Individual output end.

In one of the embodiments, as shown in Figure 10, digital filtering equipment also includes host computer 600 and coefficient register Configure EBI 700；

Host computer 600 by coefficient register configure EBI 700 respectively with CIC draw-out devices 100, FIR filter 200th, CIC interpolating apparatus 300 is connected.

In the present embodiment, host computer configures EBI by coefficient register and CIC draw-out devices, FIR can be filtered Ripple device, CIC interpolating apparatus enter row coefficient setting, extraction coefficient, the filter factor of FIR filter, the CIC of such as CIC draw-out devices Interpolation coefficient of interpolating apparatus etc., Reasonable adjustment, balance numeral are carried out to CIC draw-out devices, FIR filter, CIC interpolating apparatus The performance and system resource of filter apparatus so that digital filtering equipment is more flexibly practical.

In one of the embodiments, as shown in figure 11, host computer 600 configures EBI 700 by coefficient register Also it is connected respectively with withdrawal device 400, interpolater 500.

In the present embodiment, host computer configures EBI by coefficient register to enter to withdrawal device, interpolater Row coefficient is set, extraction coefficient, the interpolation coefficient of interpolater of such as withdrawal device, and Reasonable adjustment is carried out to withdrawal device, interpolater, Balance the performance and system resource of digital filtering equipment so that digital filtering equipment is more flexibly practical.

In a specific embodiment, digital filtering equipment can be realized in FPGA, or be designed specifically for filtering Asic chip, available in the application for needing the adjustable high speed Real-Time Filtering of any cut-off frequency, in such as oscillograph instrument.

The position of digital filtering equipment in systems as shown in figure 12, simulation process of the signal by prime, ADC (moduluses Converter) etc. processing after be input in digital filtering equipment, because the structure of digital filtering equipment can make input and output data Amount is constant, so prime ADC can bypass digital filter apparatus and be directly connected to rear class processing, without influenceing the treated of rear class Journey.It can use digital filtering equipment to be handled again after filtering, can also directly handle ADC output datas, without influenceing Rear class processing.The use of digital filtering equipment and bypass circuit can be selected by selector, the selection work(of selector It can be controlled by the enable signal of Enable Pin.

Digital filtering equipment chief component is " Digital Down Convert " device, " multiple parallel FIR " wave filters, " numerically Frequency conversion " device and " coefficient register configuration " EBI.Wherein " Digital Down Convert " device is filled by " multistage parallel CIC extractions " Put and " withdrawal device " device composition；" Digital Up Convert " device is by " multistage parallel CIC interpolation " device and " interpolater " device group Into；" coefficient register configuration " EBI can be the bus on chip interfaces such as AXI-Lite, Wishbone or Avalon-MM, With coefficient register configure the cut-off frequency real time modifying that the host computer that be connected of EBI can be as needed extract, interpolation again Number and FIR filter coefficient." multistage parallel CIC extractions " device can be only included in " Digital Down Convert " device, " is numerically become Frequently " multistage parallel CIC extractions " device can be only included in device ", " withdrawal device " device and " interpolater " device can not be set Put.

Digital filtering equipment by " Digital Down Convert " device by input data down coversion, i.e., by the sampling frequency of input data Rate f_iAdjusting " (can be by the way that " coefficient register configures bus and connect in the filter range that multiple parallel FIR " wave filters satisfaction is required Mouthful " configuration " filter coefficient " changing " multiple parallel FIR " sample frequency)；Again by the way that " coefficient register configures bus and connect Mouthful " the specific filter cutoff frequency (cut-off frequencies of data after down coversion) of configuration " filter coefficient " regulation；Finally by " number Word up-conversion " device will pass through down coversion and filtered data are restored to original sample frequency f_i；So by this three Individual device coordinates the filter effect that any cut-off frequency can be achieved.Cut-off frequency if desired for filtering is f_bd, and by configuring FIR The cut-off frequency that filter coefficient obtains FIR filter can be f_bf, so by the extraction times of whole " Digital Down Convert " device Number R_lIt is configured to that (to make output identical with input data amount, the interpolation multiple of " Digital Up Convert " part will also be configured to identical Value)：

Signal frequency is down-converted to " in the sample frequency that multiple parallel FIR " wave filters are supported, thus using cut-off Frequency is f_bfWave filter realize cut-off frequency for f_bdFiltering, certain " Digital Up Convert " device needs correspondence configuration will Again up-conversion returns original frequency to signal.

Prime " multistage parallel CIC extractions " device can reduce general serial CIC and extract what is caused sample rate not enough and occur Spectral aliasing, makes parallelism wave filter reach better performance.Because CIC transmission functions can be expressed as：

Wherein N is cascade coefficient, and M is delay factor, and R is extraction or interpolation factor, and z represents Z-shaped conversion signal.By upper public affairs Formula is understood：

That is it is (RM) that CIC, which extracts gain,^N, then it is y to export maximum_out：

Wherein B_inFor CIC input datas bit wide (binary system), CIC is calculated data and not spill over, then be used in CIC devices Data bit width B_outFor：

B_out=Nlog₂(RM)+B_in

Delay factor M generally takes fixed value 1, and cascading the coefficient that coefficient N is CIC draw-out devices, (not parallel C IC extracts dress Put the number of middle single-stage parallel C IC draw-out devices), 1~3 is generally selected as needed, and decimation factor R usually requires reality Existing larger extracting multiple, the data bit width B when decimation factor R is larger_outIt is larger, because CIC is realized using parallel pipeline structure (streamline memory cell is more), so resource is taken when data bit width increases in CIC increases more, therefore used here as multistage Parallel C IC is extracted, and the extracting multiple of " multistage parallel CIC extractions " is the product of extracting multiples at different levels, can be extracted with less The factor realizes larger extracting multiple, and the resource taken is less.

, will the bypass of " withdrawal device " device if can be without using " withdrawal device " in the case where resource is enough；Certain property worked as It can reach requirement and can use during less resource and take resource less " withdrawal device " and (can directly extract mode to be simple Realize) part " multistage parallel CIC extractions " device is replaced, because CIC has the characteristic of low pass, which reduce rear class " withdrawal device " and lead The spectral aliasing of cause.If ADC is 2G sample rates, and prime " simulation process " is by signal transacting to 100M bandwidth, due to here Sample rate is much larger than signal bandwidth, and sample rate is directly reduced so may be used herein and take resource less " withdrawal device ", and Filtering performance will not be reduced completely.

By " needing to return the data of down coversion again up-conversion into original frequency after multiple parallel FIR " devices, here Interpolation also coordinates regulation resource and performance, " multistage parallel CIC interpolation " dress with " multistage parallel CIC interpolation " device and " interpolater " Put as the anti-mirror image filtering after interpolation, also using the structure of plural serial stage, to save resource, (reason is with " CIC extractions " portion Point).Interpolating portion is divided into slotting 0 value mode interpolation in " multistage parallel CIC interpolation " device；" interpolater " can be used to close on to replicate and inserted Other interpolation methods for meeting design requirement such as value, linear interpolation.

" multistage parallel CIC extractions " device, " multistage parallel CIC interpolation " device and withdrawal device, interpolater coordinate adjustment to need The performance and the balance of resource wanted, can make digital filtering equipment more practicality.

" multistage parallel CIC extractions " apparatus structure is as shown in Fig. 2 by N_cic1Individual " single-stage parallel C IC extractions " apparatus structure Series connection is realized.

Wherein " single-stage parallel C IC extractions " apparatus structure is as shown in figure 3, by N_i1Individual " parallel integration " module, " take out parallel Take " module, N_c1Individual " dredging shape parallel " module and " Gain tuning " module are constituted.Increasing due to parallel C IC abstraction modules to data Benefit is (RM)^N, so each " single-stage parallel C IC extraction " device can carry out Gain tuning (divided by gain (RM) before exporting^N) defeated afterwards Go out.

Wherein (square frame that " D " is marked in figure is storage delay register cell to " integration parallel " module, originally as shown in Figure 4 Adder can postpone a clock cycle output after two values are added in figure), include the matrix of device of a p rows p row [A_i,j], " parallel integration " modular concurrent inputs p data, due to p data inputting simultaneously between and each input data all There is precedence relationship, result of calculation needs to complete after the completion of result before and (integrate the data before structure will add up), institute With not simple multiple single stage integration structures it is in parallel it is achieved that but handled by pipeline system, first with streamline Mode is added up values at different levels, and present clock is obtained with upper clock cycle result phase Calais again before the output of afterbody streamline Cycle result.Last data (data p-1) is present clock period input p in p data of upper clock periodical input The previous data of first data (data 0) in individual data, need to wait p data of upper clock periodical input in theory It could carry out present clock period streamline after the completion of calculating, and structure used in the utility model, first will with pipeline organization Present clock period input data is at different levels cumulative, when the row of pth -1 present clock period inputs at different levels added up, upper clock week Phase result is just completed in pth column count, and the accumulated value of present clock period input just can be with upper clock computation of Period As a result the result of last in adds up, and obtains present clock period result integrated value.

" parallel dredge shape " module as shown in Figure 5 (when delay factor M takes 1), upper clock periodical input data last Individual data (data q-1) are the previous data for first data (data 0) that present clock period is inputted, so needs ought Each data of preceding clock cycle input and one clock cycle of last data delay of upper clock periodical input are laggard Row makees difference processing, obtains the result of present clock period.

Similar " multistage parallel CIC extractions " apparatus structure, " multistage parallel CIC interpolation " apparatus structure as shown in fig. 6, by N_cic2Individual " single-stage parallel C IC interpolation " device series connection is realized.

Wherein " single-stage parallel C IC interpolation " apparatus structure is as shown in fig. 7, by N_c2It is individual " parallel dredge shape " module, " parallel to insert Value " module, N_i2Individual " parallel integration " module and " Gain tuning " module are constituted.Increasing due to parallel C IC interpolating modules to data Benefit is M (RM)^N-1(because what interpolation was inserted is worth for 0, so gain is small R times compared with paralleling abstracting module gain), so each " single-stage Gain tuning can be carried out before the output of parallel C IC interpolation " device (i.e. divided by gain M (RM)^N-1) export afterwards.

Here " dredging shape parallel " module and " parallel integration " module is similar in " parallel C IC extractions "；It is " parallel to insert Value " module is worth mode to insert 0.

" structures of multiple parallel FIR " wave filters is as shown in figure 8, main by " data distribution delay chain " module and " single-stage is simultaneously Row FIR " wave filter groups into.

The a length of N+P of shift delay chain of " data distribution delay chain " module_c2(N is the parallel FIR filter of single-stage to -1 data Exponent number), each clock cycle from data distribution delay chain the 1st to P_c1Individual storage delay register inputs M data, simultaneously P is exported in sliding window mode_c2Individual data group, is separately input to P_c2It is individual " in the parallel FIR " wave filters of single-stage by filter based on Calculate.

Series connection series N wherein in parallel C IC draw-out devices_cic1With the series connection series N in parallel C IC interpolating apparatus_cic2 For the integer more than 0, and N_cic1And N_cic2Value can be with identical, can also be different；Parallel integration module and parallel thin shape module and Line number p and q, serial number N_iAnd N_cIt is the integer more than 0, and in parallel C IC draw-out devices and parallel C IC interpolating apparatus two The corresponding value of module can be with identical, can also be different；Exponent number N in the parallel FIR filter of single-stage can be the integer more than 0.

" the parallel each system clock cycle of FIR " wave filters of single-stage can export a filter result, P_c2It is individual that " single-stage is parallel FIR " wave filters can export P in each clock cycle_c2Individual filter result (P in figure_c2Represent " multiple parallel FIR " wave filters and Line number)." the parallel FIR " wave filters of single-stage can be the FIR filter of any parallel organization, such as conventional even-order, coefficient pair " the parallel FIR " filter constructions of single-stage can be called structure as shown in Figure 9 (but being not limited to this structure).The FIR filter is passed Delivery function is：

The parallel FIR filter exponent number of single-stage is N in Fig. 9 (N is even number)；H (0)~h (N/2-1) is that filter coefficient (can Configured by " coefficient register configuration " EBI)；Square frame below figure is multi-accumulator structure, is device tree side with additive here Formula adds up, and is realized using pipeline system；It can be multistage that " adder ", " multiplier " in requirement, figure can be met for sequential Streamline is realized；The square frame for owning " D " mark in figure is storage delay register cell, is " data distribution in structure is realized Storage delay register cell in delay chain " module, i.e., the structure of upper broken line inframe is " data distribution delay chain " in figure In one " data group " structure, P_c2It is individual that " the parallel FIR " wave filters of single-stage use the P in " data distribution delay chain " successively_c2 Individual " data group ", every group of N number of storage delay register cell due to being reused using sliding window mode, then uses N altogether +P_c2- 1 storage delay register cell, i.e. " each data storage delay deposit in top in the parallel FIR " filter graph architectures of single-stage The data group that the output correspondence of device is exported from " data distribution delay chain ".

It is similar, odd-order " parallel FIR " the filter constructions such as Figure 10 (N is odd number) of single-stage, due to for odd-order, wherein Between single order be directly entered multiplier (because a data need not be added, if note adder using pipeline system realize need Notebook data was delayed after the clock cycle identical with adder streamline and is input to multiplier again) it is multiplied with wave filter coefficient of correspondence After can input summer tree added up.

Accumulator in above structure can be used to differ in the adder tree that pipeline system is realized, certain practical application It is set to adder tree mode, can multi input, the flowing water knot of one accumulation result of output as long as meeting each system clock cycle Structure.

Each module is handled using pipeline system in the utility model, and each system clock cycle can be inputted, exported once Data, the delay period number D for simply entering data to output data is：

D=D₁+D_fir+D₂

Wherein D₁For " Digital Down Convert " module delays, D₂It is delayed for " Digital Up Convert " module, D_firFor " multiple parallel FIR " Filter delay：

D₁=N_cic1×(N_i1×P₁+D_r1+N_c1)+D_dr1

D₂=N_cic2×(N_i2×P₂+D_r2+N_c2)+D_dr2

Wherein N_cic1For the series of " single-stage parallel C IC extractions " device in " multistage parallel CIC extractions " device；N_i1For " list The series of parallel integration module in level parallel C IC extractions " device；P₁For parallel integration mould in " single-stage parallel C IC extractions " device Block and line number；D_r1For the delay number of paralleling abstracting module in " single-stage parallel C IC extractions " device；N_c1For " single-stage parallel C IC The series of parallel thin shape module in extraction " device；D_dr1For the delay number of withdrawal device in " Digital Down Convert ".D_multFor " multiple parallel The pipeline series of multiplier in FIR "；N_firFor the exponent number of FIR filter.N_cic2For in " multistage parallel CIC interpolation " device The series of " single-stage parallel C IC interpolation " device；N_i2For the series of parallel integration module in " single-stage parallel C IC interpolation " device；P₂ For in " single-stage parallel C IC interpolation " device parallel integration module and line number；D_r2To be parallel in " single-stage parallel C IC interpolation " device The delay number of interpolating module；N_c2For the series of parallel thin shape module in " single-stage parallel C IC interpolation " device；D_dr2" numerically to become Frequently the delay number of interpolater in ".Adder (same to subtracter) in above formula is all thought of as using level production line realization, this In the unit of delay that calculates be system clock cycle.

And the wave filter of similar structures is realized using common MCU (microcontroller), its delay for calculating a result is estimated It is：

Because MCU modes each clock cycle can only perform an instruction (only considering monokaryon MCU) D_mcuOne in delay time It is straight to be busy with calculating, it is impossible to receive new data, and the utility model based on FPGA, even if being input to output has one section of delay D, But due to streamline implementation, new data and processing, i.e. data can be continued to during this delay can be defeated in real time Enter processing.

The utility model uses the structure of CIC extractions+withdrawal device+FIR filter+CIC interpolation+interpolater.By extracting Come down coversion, FIR filter filtering after again interpolation carry out up-conversion, realize that any cut-off frequency is adjustable with this；Extracted by prime FIR filter exponent number can be reduced by reducing progress FIR filtering after sample frequency；Input data can also be made by first extracting interpolation structure Points it is identical with output data points, so make the utility model in the design whenever with or without (bypass) without influence Prime or rear class processing；Multistage CIC is extracted and multistage CIC interpolation can use fewer resource to realize larger extraction and interpolation again Number；Prime can reduce the spectral aliasing caused due to down coversion using CIC draw-out devices, and rear class uses CIC interpolating apparatus Filtered as anti-mirror image；Extracted by CIC, interpolation and withdrawal device, interpolater coordinate the structure of adjustment, can flexible modulation resource with The balance of performance, more practicality.

Each module is all Parallel Implementation in above structure：There is the implementation of parallel C IC structures, especially there is its integral part Realization, the related parallel computation of data before and after cleverly being realized using pipeline organization；Multiple parallel FIR structures, use slip Window mode distributes data, the use of less storage organization is that multiple parallel wave filter can be achieved.All modules use Parallel Implementation, can Realize that (can just be filtered without data are first stored) filters at a high speed, in real time.

Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited In contradiction, the scope of this specification record is all considered to be.

Embodiment described above only expresses several embodiments of the present utility model, and it describes more specific and detailed, But therefore it can not be interpreted as the limitation to utility model patent scope.It should be pointed out that for the common skill of this area For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to Protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.

Claims

1. a kind of digital filtering equipment, it is characterised in that inserted including CIC draw-out devices (100), FIR filter (200) and CIC It is worth device (300)；

The P of CIC draw-out devices (100)_i1Individual input receives signal data to be filtered, wherein, P_i1For the integer more than 0；

The P of CIC draw-out devices (100)_c1The P of individual output end and FIR filter (200)_c1Individual input correspondence is connected, wherein, P_c1 For the integer more than 0；

The P of FIR filter (200)_c2Individual output end and the P of CIC interpolating apparatus (300)_c2Individual input correspondence is connected, wherein, P_c2 For the integer more than 0；

The P of CIC interpolating apparatus (300)_i2Individual output end exports filtering data, wherein, P_i2For the integer more than 0.

2. digital filtering equipment according to claim 1, it is characterised in that：

The N that CIC draw-out devices (100) include output end, input is sequentially connected_cic1Individual single-stage parallel C IC draw-out devices (110), 1st to N_cic1- 1 single-stage parallel C IC draw-out device (110) is provided with P_i1Individual input and P_i1Individual output end, N_cic1Individual list Level parallel C IC draw-out devices (110) possess P_i1Individual input and P_c1Individual output end, the 1st single-stage parallel C IC draw-out device (110) P_i1Individual input as CIC draw-out devices (100) P_i1Individual input, N_cic1Individual single-stage parallel C IC draw-out devices (110) P_c1Individual output end as CIC draw-out devices (100) P_c1Individual output end；

The N that CIC interpolating apparatus (300) includes output end, input is sequentially connected_cic2Individual single-stage parallel C IC interpolating apparatus (310), 1st to N_cic2- 1 single-stage parallel C IC interpolating apparatus (310) is provided with P_c2Individual input and P_c2Individual output end, N_cic2Individual list Level parallel C IC interpolating apparatus (310) possesses P_c2Individual input and P_i2Individual output end；1st single-stage parallel C IC interpolating apparatus (310) P_c2Individual input as CIC interpolating apparatus (300) P_c2Individual input, N_cic1Individual single-stage parallel C IC interpolating apparatus (310) P_i2Individual output end as CIC interpolating apparatus (300) P_i2Individual output end；

N_cic1、N_cic2It is the integer more than 0.

3. digital filtering equipment according to claim 2, it is characterised in that：

The N that single-stage parallel C IC draw-out devices (110) include output end, input is sequentially connected_i1Individual parallel integration module (112), Paralleling abstracting module (114), N_c1Individual shape module (116) thin parallel and the first gain regulation module (118), N_i1And N_c1It is Integer more than 0；

Each parallel integration module (112) possesses P_i1Individual input and P_i1Individual output end, paralleling abstracting module (114) possesses P_i1 Individual input and P_c1Individual output end, each shape module (116) thin parallel possesses P_c1Individual input and P_c1Individual output end；1st to N_cic1Each first gain regulation module (118) in -1 single-stage parallel C IC draw-out device (110) possesses P_c1Individual input and P_i1 Individual output end, N_cic1The first gain regulation module in individual single-stage parallel C IC draw-out devices (110) possesses P_c1Individual input and P_c1Individual output end；

The N that single-stage parallel C IC interpolating apparatus (310) includes output end, input is sequentially connected_c2Individual shape module (312) thin parallel, Parallel interpolation module (314), N_i2Individual parallel integration module (316) and the second gain regulation module (318)；

Each shape module (312) thin parallel possesses P_c2Individual input and P_c2Individual output end, parallel interpolation module (314) possesses P_c2 Individual input and P_i2Individual output end, each parallel integration module (316) possesses P_i2Individual input and P_i2Individual output end；1st to N_cic2Each second gain regulation module (318) in -1 single-stage parallel C IC interpolating apparatus (310) possesses P_i2Individual input and P_c2 Individual output end, N_cic2The second gain regulation module in individual single-stage parallel C IC interpolating apparatus (310) possesses P_i2Individual input and P_i2Individual output end.

4. digital filtering equipment according to claim 3, it is characterised in that parallel integration module includes matrix of device [A_i,j], wherein, 1≤i≤p, 1≤j≤p, p is the parallel channel number of the parallel integration module, and i, j, p are integer；

The device A of i-th row i-th -1 row_i,i-1The device A arranged with pth_i,pIt is adder, matrix of device [A_i,j] in remaining device Part is storage delay register；

Storage delay register A_1,1Input and adder A_2,1First input end connection, adder A_k,k-1Output end with Adder A_k+1,kFirst input end connection, while adder A_k,k-1Output end and storage delay register A_k,kInput Connection, wherein, 2≤k≤p-1, k is integer；

Storage delay register A_h,h-2Output end and adder A_h,h-1The connection of the second input, wherein, 3≤h≤p, h is whole Number；

Storage delay register A_g,p-1Output end and adder A_g,pThe connection of the second input, wherein, 1≤g≤p-1, g is Integer, adder A_p,p-1Output end and adder A_p,pThe second input connection, adder A_p,pOutput end and adder A_i,pFirst input end connection；

The input of the parallel integration module includes storage delay register A_1,1Input, adder A_2,1Second input End and storage delay register A_h,1Input, the output end of the parallel integration module includes adder A_i,pOutput End；

The parallel integration module is parallel integration module (112) or parallel integration module (316).

5. digital filtering equipment according to claim 3, it is characterised in that parallel thin shape module include q subtracter with One storage delay register, wherein, q is the parallel parallel channel number for dredging shape module；

The input of the parallel thin shape module includes the first input end of all subtracters, the output of the parallel thin shape module End includes the output end of all subtracters；

The first input end of r-th of subtracter is connected with second input of (r+1) individual subtracter；Wherein, 1≤r≤q-1, R, q are integer；

The first input end of q-th of subtracter is connected with the input of the storage delay register, the storage delay deposit The output end of device is connected with the second input of the 1st subtracter；

The shape module thin parallel thin shape module (312) for thin shape module (116) parallel or parallel.

6. digital filtering equipment according to claim 1, it is characterised in that FIR filter (200) is prolonged including data distribution Slow chain module (210) and P_c2The individual parallel FIR filter of single-stage (220)；

Data distribution delay chain module (210) includes (N+P_c2- 1) the individual storage delay register being arranged in order, wherein, n-th The output end of storage delay register and (n+P_c1) individual storage delay register input connection, 1≤n≤N-1, n, N are equal For integer, N is the exponent number of the parallel FIR filter of single-stage (220)；

M is to the output end of (N+m-1) individual storage delay register and the input of the parallel FIR filter of m-th of single-stage (220) Correspondence connection, wherein, 1≤m≤P_c2, m is integer；

The input of FIR filter (200) includes the 1st to P_c1The input of individual storage delay register, FIR filter (200) Output end include the output end of the parallel FIR filter of all single-stages (220).

7. digital filtering equipment according to claim 6, it is characterised in that：

When the exponent number of the parallel FIR filter of single-stage (220) is even number, the parallel FIR filter of single-stage (220) includes N/2 and added Musical instruments used in a Buddhist or Taoist mass, N/2 multiplier and an accumulator；

In the N number of storage delay register being arranged in order being connected with the parallel FIR filter of single-stage (220), s-th of storage delay The output end of register and the output end of (N+1-s) individual storage delay register are connected respectively to a corresponding adder Two inputs, wherein, 1≤s≤N, the output end of each adder is connected with the input of a corresponding multiplier, each The output end of multiplier is connected with the corresponding input of the accumulator, and the output end of the accumulator is the parallel FIR of single-stage The output end of wave filter (220).

8. digital filtering equipment according to claim 6, it is characterised in that：

When the exponent number of the parallel FIR filter of single-stage (220) is odd number, the parallel FIR filter of single-stage (320) includes (N-1)/2 Individual adder, delayer, (N+1)/2 multiplier and an accumulator；

In the N number of storage delay register being arranged in order being connected with the parallel FIR filter of single-stage (220), s-th of storage delay The output end of register and the output end of (N+1-s) individual storage delay register are connected respectively to a corresponding adder Two inputs, wherein, 1≤s≤N, the output end of each adder is connected with the input of a corresponding multiplier, (N + 1)/2 the output end of a storage delay register is connected with the input of the delayer, the output end of the delayer with it is right The input connection for the multiplier answered, the output end of each multiplier is connected with the corresponding input of the accumulator, The output end of the accumulator is the output end of the parallel FIR filter of single-stage (220).

9. digital filtering equipment according to claim 1, it is characterised in that also including withdrawal device (400) and interpolater (500), withdrawal device (400) is connected between the input of the output end of CIC draw-out devices (100) and FIR filter (200), Interpolater (500) is connected between the input of the delivery outlet of FIR filter (200) and CIC interpolating apparatus (300).

10. digital filtering equipment as claimed in any of claims 1 to 9, it is characterised in that also including host computer (600) and coefficient register configuration EBI (700)；

Host computer (600) configures EBI (700) by coefficient register and filtered respectively with CIC draw-out devices (100), FIR Device (200), CIC interpolating apparatus (300) connection.