CN112118019B - Multichannel channelized receiver and application system - Google Patents
Multichannel channelized receiver and application system Download PDFInfo
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- CN112118019B CN112118019B CN202010771796.6A CN202010771796A CN112118019B CN 112118019 B CN112118019 B CN 112118019B CN 202010771796 A CN202010771796 A CN 202010771796A CN 112118019 B CN112118019 B CN 112118019B
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Abstract
The invention discloses a multichannel channelized receiver and an application system, wherein the multichannel channelized receiver receives output data of M output channels in a previous stage channelized receiver, the multichannel channelized receiver is provided with an N-phase filter bank structure, each phase filter bank structure outputs the output data of the M channels, and the multichannel channelized receiver finally outputs the data of the M channels. The multichannel channelized receiver provided by the invention can be applied to a multi-level channelized receiver structure, and the scheme that M channelized receivers are needed for receiving M data output by a previous-level channelized receiver originally is replaced by at least one multichannel channelized receiver, so that the multiplexing efficiency of chip hardware resources can be improved, and the performance of receiving signals is not reduced.
Description
Technical Field
The invention relates to the technical field of software radio in the fields of radar and communication, in particular to a multichannel channelized receiver and an application system.
Background
In the prior art, the structures of a digital channelized receiver with uniformly divided channels generally include a band pass filter bank structure, a low pass filter bank structure, a polyphase filter bank structure and a WOLA structure. The band-pass filter bank structure and the low-pass filter bank structure are only suitable for being used when the number of channels is small, when the number of channels is large, a large amount of computing resources are consumed, the energy efficiency ratio is extremely low, and the realization is possibly impossible. The latter two structures are suitable for any number of channels, can save a large number of resources, do not reduce performance, and are generally suitable for FPGA implementation.
Currently, the existing architecture for implementing a digital channelized receiver with a large number of channels generally adopts a polyphase filter bank architecture and/or a WOLA architecture. When the requirements on the prototype filter are low, the channelized receiver adopting the two structures can be realized in one stage; when the requirement for the prototype filter is high, the filter order is very large due to the adoption of the one-stage implementation structure, and the realization may not be possible, so that a method of realizing the filter in multiple stages is generally adopted. At present, the digital channelized receiver is commonly realized by two stages, the order of the filter can be effectively reduced by realizing the digital channelized receiver by stages, and the digital channelized receiver is easy to realize.
In the case of a hierarchical implementation, taking a two-stage implementation as an example, the first-stage channelized receiver is used to reduce the sampling rate, and the number of output channels of the first-stage channelized receiver determines the number of second-stage channelized receivers. For example, when the number of channels output by the first-stage channelized receiver is M, M identical second-stage channelized receivers are required, the number of simultaneously existing channelized receivers is M +1, and if the number of channels output by each second-stage channelized receiver is N, the total number of channels is M times N. In some application scenarios, the total data rate (defined as the input data rate of the first-stage channelized receiver) is significantly lower than the system processing speed, and if M second-stage channelized receivers exist at the same time, chip hardware resources, such as FPGA internal logic computation resources, are wasted. In the current implementation, M second-level channelized receivers are generally implemented in parallel at the same time, and therefore, the utilization rate of chip hardware resources is not high. For example, when the number of channels is 2048, if the number of channels in the first stage is M equal to 32, then the number of channels in the second stage of channelized receivers is N equal to 64, and then the total number of channelized receivers to be implemented is 32+ 1. Because the channelized receiver is essentially a fir filter, the input and output data stream cannot be interrupted, and if the second-stage channelized receiver adopts a single-channel channelized receiver, M second-stage channelized receivers must be simultaneously realized to ensure that the data is continuous; if the data output by the first-stage channelized receiver shares a single-channel second-stage channelized receiver in a time-sharing manner, the data stream is necessarily interrupted, and the method is not suitable for occasions requiring continuous data streams. Therefore, in order to save chip resources (usually FPGA chips) without breaking the continuity of data, an improvement on the conventional single-channel channelized receiver is needed.
Disclosure of Invention
The present invention is directed to solving at least the problems of the prior art. Therefore, the invention provides a multichannel channelized receiver and an application system.
In a first aspect of the present invention, a multichannel channelized receiver is provided, where the multichannel channelized receiver has an N-phase filter bank structure, the multichannel channelized receiver receives output data of M output channels in a previous stage channelized receiver, each phase filter bank structure outputs M output data, and the multichannel channelized receiver finally outputs data of M × N channels.
According to some embodiments of the invention, the multichannel channelized receiver alternately inputs the received data into the N-phase filter bank structure with a period of M samples.
According to some embodiments of the invention, each phase filterThe group structures all comprise a sign multiplier, a fir filter, a phase weighting multiplier and a DFT module; the sign of every M sampling points in the output data of the sign multiplier changes once; the tap number of the input delay line of the fir filter is Kp/NdspDelay depth of each tap is NdspM, the depth of the output delay line is G M +1, wherein G is 0,1,2, …, Ndsp-1，KpIs the order of the fir filter, NdspThe number of DSPs required for the fir filter.
In a second aspect of the present invention, an application system of a multichannel channelized receiver is provided, where the application system has more than two stages of channelized receivers, and a subsequent stage of channelized receiver has a multichannel channelized receiver, where the multichannel channelized receiver is configured to receive output data of M output channels of a previous stage of channelized receiver, and the multichannel channelized receiver has an N-phase filter bank structure, where each phase filter bank structure outputs M output data, and the multichannel channelized receiver finally outputs data of M × N channels.
According to some embodiments of the invention, the number of multichannel channelized receivers is one or more.
According to the embodiment of the invention, at least the following technical effects are achieved:
the multichannel channelized receiver provided by the invention can be applied to a multi-stage channelized receiver structure, and the scheme that M channelized receivers are needed for receiving M data output by a previous stage channelized receiver originally is replaced by the multichannel channelized receiver, so that the multiplexing efficiency of chip hardware resources can be improved on the premise of ensuring the receiving performance.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a logic block diagram of a prior art two-stage channelized receiver of the present invention;
fig. 2 is a prior art implementation structure of a first stage channelized receiver according to the present invention;
FIG. 3 is an output data structure of a per-phase filter bank structure of a prior art first stage channelized receiver of the present invention;
FIG. 4 is a diagram of the output data structure of a symbol multiplier in a prior art first stage channelized receiver of the present invention;
fig. 5 is a logic block diagram of a first-stage channelized receiver and a multi-channel channelized receiver according to an embodiment of the present invention;
fig. 6 is an implementation structure of a multi-channel channelized receiver according to an embodiment of the present invention;
fig. 7 is an output data structure of a symbol multiplier of a multichannel channelized receiver according to an embodiment of the present invention;
fig. 8 is an output data structure of each phase filter bank structure of a multichannel channelized receiver according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a multi-channel fir filter of a multi-channel channelized receiver according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
Referring to fig. 1 to 4, a structure of a conventional channelized receiver is briefly described in order to understand the technical scheme of the present invention;
fig. 1 is a logic block diagram of a two-stage channelized receiver commonly known in the art, which includes a first-stage channelized receiver (assuming that the number of channels of the first-stage channelized receiver is M, and M is an exponential power of 2) and M second-stage channelized receivers (assuming that the number of channels of each second-stage channelized receiver is N).
Fig. 2 shows an implementation structure of a first-stage channelized receiver, which has M-phase filter bank structures, each of which is identical, and has phase numbers from 0 th phase, 1 st phase to M-1 st phase from top to bottom, each of which includes a sign multiplier, a filter, a phase weighting multiplier, and an input and an output occupying an M-point DFT module, where M is an exponential power of 2, n is mM + p, p is 0,1,2, …, and M-1.
Fig. 3 is an output data structure of each phase filter bank structure of the first stage channelized receiver. All data structures of the invention are logical structures and are independent of the specific implementation. In fig. 3, the symbol subscripts denote the time series of the output channels and the superscripts denote the channel numbers. For the existing single-channel channelized receiver, the output channel number and phase number are equal. The output of each phase, time series m, increases by 1 for each sample, and the channel number remains unchanged.
Fig. 4 is an output data structure of a symbol multiplier in a first stage channelized receiver in which each sample symbol in each phase is changed once.
Referring to fig. 5 to fig. 9, an embodiment of the present invention provides a multichannel channelized receiver, where the embodiment takes a two-stage channelized receiver design as an example, the multichannel channelized receiver is a second-stage channelized receiver, the number of channels is N, the number of channels of a first-stage channelized receiver is M, and the total number of channels is M × N.
The multichannel channelized receiver comprises N-phase filter bank structures, each phase filter bank structure comprises a symbol multiplier, a multichannel fir filter and a phase weighting multiplier, and one input and one output of a DFT module are occupied by the multichannel fir filter and the phase weighting multiplier.
The multichannel channelized receiver receives data of M channels output by the first-stage channelized receiver, and the data of M channels needs to be recombined and distributed to an N-phase filter bank structure, as shown in fig. 6 and 7, where subscripts of the data indicate time series and superscripts indicate channel numbers.
The data of each channel alternately appears, and the alternation process takes M sampling points as a period, wherein the data entering the phase 0 structure is as follows:
the data entered into phase 1 structure is:
and analogizing the data entering the phase 2 structure to the data entering the phase N-1 structure, wherein the data entering the phase N-1 structure is as follows:
the result of the output data of the sign multiplier is shown in fig. 7, changing sign every M samples.
The output data of the symbol multiplier enters a multi-channel fir filter, and the multi-channel fir filter needs to be processed for matching the output data of the symbol multiplier:
(1) and processing the coefficients of the multi-channel fir filter:
let the order of the prototype low-pass filter be KtMulti-channel per phase fir filter hx(m) has an order of Kp. Because of the order K of the prototype low-pass filtertThe division by the number of channels N may be non-integer, so that the coefficients of the prototype low-pass filter need to be tail-zeroed first, so that the order of the prototype low-pass filter divided by the number of channels N becomes an integer. The order K of the final prototype low-pass filter after tail zero padding is as follows:
wherein ceil () is a ceiling function.
(2) And calculating hardware resources:
let the clock rate of chip (e.g. FPGA) operation be fpThe number of processing clocks available per sample point fnIs composed of
Wherein, fsRepresenting the input data rate, f, of the first-stage channelized receiver0Representing the output data rate of each channel of the first stage channelized receiver, and fix () is a floor function. Since the order of each phase filter is KpCalculating K thereforepThe coefficient of the filter must be at fnCompleted in one clock cycle, then, each phase filter hx(m) the number of DSPs (multiply-accumulator) required is Ndsp：
According to NdspEach phase is filtered by hxK of (m)pDivision of the coefficients of a filter into NdspGroups, the number of coefficients of each group being Kg：
If K isp<KgNdspThen represents KpUnable to remove NdspAt this time, K needs to be updated by reverse pushingpAnd the value of K until the following equation is satisfied:
Kp＝KgNdsp (7)
K＝KpN (8)
k filter coefficients are at KtThe result of zero-filling after the coefficients of the prototype filter, i.e. K-K filling after the prototype filtertAnd 0.
As shown in fig. 9, the structure of the multi-channel fir filter of the present embodiment includes an input delay line, a multiplexer, a multiplier-accumulator, a filter coefficient memory, an output delay line, a gate switch, an output adder, and the like. Wherein the input data of the input delay line is from the output data of the symbol multiplier, and the number of taps (output nodes) of the delay line is
(N in FIG. 9)dsp2) delay depth of each tap is NdspM, coefficient h of multi-channel fir filterx(m) division into NdspAnd 2 sets, respectively, stored in the filter coefficient memories. Data of tap output respectively and NdspThe set of filter coefficients performs a multiply-accumulate operation. The delay depth of the output delay line is G × M +1, wherein G is 0,1,2, …, Ndsp-1. I.e., the first set of output delay lines have a delay depth of 1 and the second set is M +1, as shown in fig. 9.
As in FIG. 5 for
The data with the time sequence m of 0, N,2N, …, kN, … enter an N-1 phase multi-channel fir filter hN-1(k) The preparation method comprises the following steps of (1) performing; data with the time sequence m of 1, N +1,2N +1, …, kN +1, … enter an N-2 phase multi-channel fir filter hN-2(k) Performing the following steps; by analogy, the data with the final time sequence m of N-1, N-1+ N, N-1+2N, …, N-1+ kN, … enter a 0 th-phase multi-channel fir filter h0(k) In (1).Each time point k of the multichannel channelized receiver output data corresponds to a group of M x N sampling points. The N-point DFT outputs data of N channels at each time, the channel numbers are 0-N-1, N-2N-1, … and MN-N-MN-1 in sequence, and the steps are repeated in a circulating mode.
Compared with the existing method, the embodiment realizes the scheme of replacing the original M second-stage channelized receivers by one multichannel channelized receiver, so that the resource usage amount is reduced by M times at most, the data continuity is ensured, the performance is not reduced, and the resource efficiency ratio is very high.
As shown in table 1 below, comparative data is provided for this example versus the prior art scheme:
TABLE 1
From table 1, with the same receiver parameters, only 64 DSPs are needed to implement a multichannel channelized receiver, whereas 2048 DSPs are needed using the existing scheme.
An embodiment of the present invention provides an application system of a multichannel channelized receiver, where the system has more than two stages of channelized receivers, and a subsequent stage of channelized receiver has at least one multichannel channelized receiver therein, and the multichannel channelized receiver is configured to receive output data of M output channels of a previous stage of channelized receiver, and if the multichannel channelized receiver has an N-phase filter bank structure, each filter bank structure outputs M output data, and the multichannel channelized receiver finally outputs data of M × N channels.
It should be noted that the application system of the multichannel channelized receiver provided in this embodiment is based on the same inventive concept as the multichannel channelized receiver provided in the foregoing embodiment. Based on the above embodiments, the multichannel channelized receiver can be applied to a receiving structure of a channelized receiver implemented in multiple stages, such as 3-stage and 4-stage, and can improve the multiplexing efficiency of hardware resources without reducing the performance.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (4)
1. A multichannel channelized receiver, wherein the multichannel channelized receiver receives output data of M output channels in a previous stage channelized receiver, and if the multichannel channelized receiver has an N-phase filter bank structure, each phase filter bank structure outputs data of M channels, and the multichannel channelized receiver finally outputs data of M × N channels, wherein each phase filter bank structure includes a symbol multiplier, a fir filter, a phase weighting multiplier, and a DFT module; the sign of every M sampling points in the output data of the sign multiplier changes once; the tap number of the input delay line of the fir filter is Kp/NdspDelay depth of each tap is NdspM, the depth of the output delay line is G M +1, wherein G is 0,1,2dsp-1，KpIs the order of the fir filter, NdspThe number of DSPs required for the fir filter.
2. The multichannel channelized receiver of claim 1 wherein the multichannel channelized receiver alternately inputs the received data into the N-phase filter bank structure with a period of M samples.
3. A system for use in a multichannel channelized receiver, comprising: the multichannel channelized receiver is provided with more than two stages of channelized receivers, a multichannel channelized receiver is arranged in a next stage of channelized receiver, the multichannel channelized receiver is used for receiving output data of M output channels of a previous stage of channelized receiver, the multichannel channelized receiver is provided with an N-phase filter bank structure, each phase of filter bank structure outputs the output data of the M channels, and the multichannel channelized receiver finally outputs data of M channels, wherein each phase of filter bank structure comprises a symbol multiplier, a fir filter, a phase weighting multiplier and a DFT module; the sign of every M sampling points in the output data of the sign multiplier changes once; the tap number of the input delay line of the fir filter is Kp/NdspDelay depth of each tap is NdspM, the depth of the output delay line is G × M +1, where G is 0,1,2dsp-1，KpIs the order of the fir filter, NdspThe number of DSPs required for the fir filter.
4. A system for use in a multichannel channelized receiver according to claim 3 characterized by: the number of the multichannel channelized receivers is one or more.
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