CN103684698A

CN103684698A - Method and device for processing data signal

Info

Publication number: CN103684698A
Application number: CN201310747048.4A
Authority: CN
Inventors: 黄帅; 王焕东; 陈新科
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2013-12-30
Filing date: 2013-12-30
Publication date: 2014-03-26
Anticipated expiration: 2033-12-30
Also published as: CN103684698B

Abstract

The invention discloses a method and a device for processing data signals. The method comprises acquiring a first data signal and a second clock signal, wherein the first data signal corresponds to the second clock signal. The clock cycle of the first data signal is same with the clock cycle of the second clock signal. If the location of the phase difference between the first clock signal and the second clock signal is in a first preset section, the rising edge of the second clock signal is used for collecting the first data signal. If the location is in a second preset section, the falling edge of the second clock signal is used for collecting the first data signal. A second data signal can be acquired according to the data obtained from the first data signal, wherein the second data signal corresponds to the second clock signal. Accordingly, the technical problem of the prior art that the timing margin of data signals in transmission paths of clock domain crossing cannot be controlled is solved.

Description

The processing method of data-signal and device

Technical field

The present invention relates to electronic circuit field, in particular to a kind of processing method and device of data-signal.

Background technology

In the scheme of the cross clock domain transmission of existing data-signal, conventionally can use the hopping edge of a clock signal to go to gather the data-signal corresponding with another clock signal, to obtain the data-signal corresponding with last clock signal.Yet in this scheme, the sequential nargin of data-signal on the transmission path of cross clock domain transmission is uncontrollable and uncertain, its sequential nargin can be larger under a kind of situation, also can be less under another kind of situation, and when sequential nargin hour, because the duration of the value after the data-signal renewal as acquisition target is shorter, its data mode is relatively also unstable, therefore the data that collect are also inaccurate, thereby have affected the reliability of the cross clock domain transmission of data-signal.In other words, existing scheme cannot guarantee to meet the requirement to sequential nargin, and its reason can be summed up as the problem of the sequential nargin of uncontrollable data-signal on the transmission path of cross clock domain transmission in prior art.

For above-mentioned problem, effective solution is not yet proposed at present.

Summary of the invention

The embodiment of the present invention provides a kind of processing method and device of data-signal, at least to solve the technical problem of the sequential nargin of uncontrollable data-signal on the transmission path of cross clock domain transmission in prior art.

According to the embodiment of the present invention aspect, a kind of processing method of data-signal is provided, comprise: obtain the first data-signal and second clock signal, wherein, above-mentioned the first data-signal is corresponding with the first clock signal, and the clock cycle of above-mentioned the first clock signal is identical with the clock cycle of above-mentioned second clock signal; If above-mentioned the first clock signal is positioned at the first pre-set interval with respect to the phase difference of above-mentioned second clock signal, use the rising edge of above-mentioned second clock signal to gather above-mentioned the first data-signal; If above-mentioned phase difference is positioned at the second pre-set interval, use the trailing edge of above-mentioned second clock signal to gather above-mentioned the first data-signal; According to gathering the resulting data-signal of above-mentioned the first data-signal, obtain the second data-signal, wherein, above-mentioned the second data-signal is corresponding with above-mentioned second clock signal.

According to the embodiment of the present invention on the other hand, a kind of processing unit of data-signal is also provided, comprise: acquiring unit, be used for obtaining the first data-signal and second clock signal, wherein, above-mentioned the first data-signal is corresponding with the first clock signal, and the clock cycle of above-mentioned the first clock signal is identical with the clock cycle of above-mentioned second clock signal; Selected cell, for when above-mentioned the first clock signal is positioned at the first pre-set interval with respect to the phase difference of above-mentioned second clock signal, use the rising edge of above-mentioned second clock signal to gather above-mentioned the first data-signal, when above-mentioned phase difference is positioned at the second pre-set interval, use the trailing edge of above-mentioned second clock signal to gather above-mentioned the first data-signal; Processing unit, for obtaining the second data-signal according to gathering the resulting data-signal of above-mentioned the first data-signal, wherein, above-mentioned the second data-signal is corresponding with above-mentioned second clock signal.

In embodiments of the present invention, adopted according to the phase difference between the first clock signal and second clock signal in the mode of using between the rising edge of second clock signal or trailing edge selecting between gathering with the first data-signal corresponding to the first clock signal, corresponding with second clock signal to obtain, and meet the second clock signal to the requirement of sequential nargin, wherein, to the control of sequential nargin, can in conjunction with the first pre-set interval and the second pre-set interval, realize by above-mentioned selection mechanism, and then solved the technical problem of the sequential nargin of uncontrollable data-signal on the transmission path of cross clock domain transmission in prior art.Further, can be by rationally arranging of the first pre-set interval and the second pre-set interval being met to the designing requirement to the cross clock domain transmission of data-signal, and improve the reliability of the cross clock domain transmission of data-signal.

Accompanying drawing explanation

Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:

Fig. 1 is according to the schematic diagram of the processing method of a kind of data-signal of the embodiment of the present invention;

Fig. 2 is according to the schematic diagram of the cross clock domain transmission of a kind of data-signal of prior art;

Fig. 3 is according to the schematic diagram of the cross clock domain transmission of the another kind of data-signal of prior art;

Fig. 4 is according to the schematic diagram of the cross clock domain transmission of a kind of data-signal of the embodiment of the present invention;

Fig. 5 is according to the schematic diagram of the cross clock domain transmission of the another kind of data-signal of the embodiment of the present invention;

Fig. 6 is according to the schematic diagram of the processing unit of a kind of data-signal of the embodiment of the present invention;

Fig. 7 is according to the schematic diagram of the processing unit of the another kind of data-signal of the embodiment of the present invention.

Embodiment

Hereinafter with reference to accompanying drawing, also describe the present invention in detail in conjunction with the embodiments.It should be noted that, in the situation that not conflicting, embodiment and the feature in embodiment in the application can combine mutually.

Embodiment 1

According to the embodiment of the present invention, a kind of processing method of data-signal is provided, as shown in Figure 1, this processing method comprises:

S102: obtain the first data-signal and second clock signal, wherein, the first data-signal is corresponding with the first clock signal, and the clock cycle of the first clock signal is identical with the clock cycle of second clock signal;

S104: if the first clock signal is positioned at the first pre-set interval with respect to the phase difference of second clock signal, use the rising edge of second clock signal to gather the first data-signal; If this phase difference is positioned at the second pre-set interval, use the trailing edge of second clock signal to gather the first data-signal;

S106: obtain the second data-signal according to gathering the resulting data-signal of the first data-signal, wherein, the second data-signal is corresponding with second clock signal.

Will be clear that, one of technical solution of the present invention technical problem to be solved is to provide a kind of method that data-signal is processed, to realize the transmission to the cross clock domain of this data-signal, also be, the data-signal corresponding with clock signal is converted to the data-signal corresponding with another clock signal, and the content of these two data-signals is identical, wherein, for ease of statement, above-mentioned " clock signal " is designated as to the first clock signal, above-mentioned " another clock signal " is designated as to second clock signal, and this data-signal corresponding with the first clock signal is designated as to the first data-signal, to be designated as the second data-signal in this data-signal corresponding to second clock signal.

In embodiments of the present invention, the first data-signal conventionally can show as the two with corresponding relation between the first clock signal and mutually align, also be, the renewal frequency of the first data-signal is consistent with the clock frequency of the first clock signal, and the two phase place is identical, for example, in Fig. 2, the first data-signal as shown in the 2nd row is corresponding with the first clock signal as shown in the 1st row.Yet the present invention is not construed as limiting this, for example, in some embodiments of the invention, corresponding relation between the first data-signal and the first clock signal also can show as certain the definite phase relation between homogenous frequency signal, quadrature or anti-phase etc., under this scene, although the first data-signal and the first clock signal also do not line up, yet because the phase relation between the two is definite and known, therefore still can by the first inaccurate clock signal know the sequential of the first data-signal by inference, thereby the first data-signal still can be considered as in the clock zone of the first clock signal.

Similarly, in embodiments of the present invention, the second data-signal also can show as similar to the corresponding relation between the first clock signal to above-mentioned the first data-signal to the corresponding relation between second clock signal, yet it should be noted that must be in full accord between these two corresponding relations, for example, in embodiments of the present invention, the first data-signal can align with the first clock signal, and the second data-signal can with second clock signal inversion, the present invention is not construed as limiting this.In addition, in embodiments of the present invention, second clock signal can be identical with the clock cycle of the first clock signal.

Based on above description, realization proposed by the invention also can be expressed as the problems referred to above of the cross clock domain transmission of data-signal: first data-signal corresponding with the first clock signal is converted to second data-signal corresponding with second clock signal, wherein, the first data-signal is identical with the content of the second data-signal, yet sequential has different, correspond respectively to the first clock signal and second clock signal.

For addressing this problem, in existing scheme, conventionally can use the hopping edge of second clock signal to remove to gather the first data-signal, to obtain the second data-signal, for example, in Fig. 2, first data-signal of the rising edge collection that can use the second clock signal as shown in the 3rd row as shown in the 2nd row, and can will collect, data-signal as shown in the 4th row is as the second data-signal, wherein, as can be seen from Figure 2, the first data-signal is corresponding with the first clock signal, the second data-signal is corresponding with second clock signal, thereby realize the transmission of the cross clock domain of data-signal.

Easily find out, in Fig. 2, the first data-signal as shown in the 2nd row is to the sequential nargin t on the transmission path of the second data-signal as shown in the 4th row ₁be greater than clock cycle T/2 half, wherein T represents the clock cycle of the first clock signal, that is to say, when the rising edge of use second clock signal gathers the first data-signal, the duration that the first data-signal is updated to this state of numerical value a has surpassed T/2, thereby this data mode is more easily recovered in the disturbances such as burr produce and is transitioned into comparatively stable state from being upgraded by numerical value comparatively speaking, and then the data that the rising edge that uses second clock signal collects are also comparatively accurate, this transmission of cross clock domain for data-signal is favourable.

Yet in fact, for above-mentioned existing scheme, the sequential nargin of data-signal on the transmission path of cross clock domain transmission is uncertain, under a scene, example situation as shown in Figure 2, its sequential nargin is larger, under another scene, example situation as shown in Figure 3, its sequential nargin t ₂relatively little, at least be less than the clock cycle half, while using the rising edge of second clock signal to gather the first data-signal under this scene, the duration that is updated to numerical value a due to the first data-signal is shorter, therefore its data mode may be also unstable, the data that collect thus are also inaccurate, thereby have affected the reliability of the cross clock domain transmission of data-signal.In other words, the rising edge of use second clock signal gathers the first data-signal cannot guarantee to meet the requirement to above-mentioned sequential nargin to generate the mode of the second data-signal, correspondingly, the trailing edge of use second clock signal gathers the first data-signal and also has similar problem to generate the mode of the second data-signal, and its reason can be summed up as the problem of the sequential nargin of uncontrollable data-signal on the transmission path of cross clock domain transmission in prior art.

For addressing this problem, in embodiments of the present invention, can utilize second clock signals collecting the first data-signal to generate the mode of the second data-signal along holding, and in step S102, obtain this first data-signal and this second clock signal, yet the prior art of being different from, the processing method providing according to the embodiment of the present invention, in step S104, can select using between the rising edge of second clock signal or trailing edge according to the phase relation between the first clock signal and second clock signal, wherein, if the first clock signal is positioned at the first pre-set interval with respect to the phase difference of second clock signal, can use the rising edge of second clock signal to gather the first data-signal, if phase difference is positioned at the second pre-set interval, can use the trailing edge of second clock signal to gather the first data-signal.In other words, in embodiments of the present invention, not use statically the rising edge of second clock signal or trailing edge to gather the first data-signal, but can for different situations, select one of rising edge and trailing edge to gather in relative dynamic ground, thereby realize the control of the sequential nargin on the transmission path across clock transfer to data-signal, and then reach the requirement to this sequential nargin.

It should be noted that, above-mentioned " dynamically " selection is not limited to select in real time, in embodiments of the present invention, the cycle of selecting between " rising edge collection " and " trailing edge collection " can, for a shorter time cycle, can be also a longer time cycle, in addition, the mechanism of this selection can also intercouple with other mechanism, for example judgment mechanism, and wherein, the result that this selection also can produce according to judgment mechanism triggers, Deng, the present invention is not construed as limiting this.In addition, as optional execution mode, above-mentioned selection mechanism both can be passed through hardware logic, for example logical circuit is realized, and can be encapsulated in further in physical interface to improve integrated level and processing speed, and reduce the processing pressure of processor, it also can pass through software logic, such as the programming of the programmable platforms such as MCU, FPGA or PLC is realized, the present invention is not construed as limiting this.

Below in conjunction with Fig. 4 and Fig. 5, the operation principle of the scheme of the embodiment of the present invention is explained in detail.In embodiments of the present invention, above-mentioned the first pre-set interval can be set to (T/2, T), above-mentioned the second pre-set interval can be set to (0, T/2).It should be noted that, in this application, the first clock signal represents that with respect to the phase difference of second clock signal the first clock signal is with respect to the lead of second clock signal, for example, if the first clock signal shifts to an earlier date 1/4 clock cycle with respect to second clock signal, the first clock signal is 1/4 clock cycle with respect to the phase difference of second clock signal.

As shown in Figure 4, under a scene of the embodiment of the present invention, the first clock signal can be clock signal as shown in the 1st row, and the first data-signal can be the data-signal as shown in the 2nd row, and second clock signal can be the clock signal as shown in the 3rd row.Under above-mentioned scene, the first clock signal is greater than the clock cycle half with respect to the phase difference of second clock signal, also be positioned at the first pre-set interval (T/2, T) in, thereby according to step S104, rising edge that can choice for use second clock signal gathers the first data-signal, and obtains data-signal as shown in the 4th row as the second data-signal.Easily find out, under above-mentioned scene, the first data-signal is corresponding with the first clock signal, the second data-signal is corresponding with second clock signal, and the data content of the second data-signal is consistent with the first data-signal, also realized the cross clock domain transmission of the first data-signal, on the other hand, sequential nargin on the transmission path of this cross clock domain transmission equals above-mentioned phase difference, and above-mentioned phase difference is positioned at the first pre-set interval, be greater than the clock cycle half, therefore this sequential nargin is greater than the clock cycle half, also be, in embodiments of the present invention, to the control of sequential nargin, can partly by the first pre-set interval, be realized, thereby can by the reasonable setting of the first pre-set interval to meet the requirement to this sequential nargin, and then reach image data exactly, and the effect of the reliability of the cross clock domain transmission of raising data-signal.

As a comparison, under above-mentioned scene, if select the trailing edge of second clock signal to gather the first data-signal, the data-signal obtaining can be the data-signal being represented by oblique line as Fig. 4 the 5th row, easily find out, this data-signal collecting is less than the clock cycle half with respect to the sequential nargin of the first data-signal, and does not meet the requirement to above-mentioned sequential nargin corresponding with the first pre-set interval, and then may cause the lower problem of reliability of the cross clock domain transmission of data-signal.

As shown in Figure 5, under another scene of the embodiment of the present invention, the first clock signal can be clock signal as shown in the 1st row, and the first data-signal can be the data-signal as shown in the 2nd row, and second clock signal can be the clock signal as shown in the 3rd row.Under above-mentioned scene, the first clock signal is less than the clock cycle half with respect to the phase difference of second clock signal, also be positioned at the second pre-set interval (0, T/2) in, thereby according to step S104, trailing edge that can choice for use second clock signal gathers the first data-signal, and obtains data-signal as shown in the 5th row as the second data-signal.Easily find out, under above-mentioned scene, on the basis of cross clock domain transmission of realizing the first data-signal, sequential nargin on the transmission path of this cross clock domain transmission equals above-mentioned phase difference and adds the clock cycle half, and above-mentioned phase difference is positioned at the second pre-set interval, be less than the clock cycle half, therefore this sequential nargin is greater than the clock cycle half, also be, in embodiments of the present invention, to the control of sequential nargin, can partly by the second pre-set interval, be realized, thereby can by the reasonable setting of the second pre-set interval to meet the requirement to this sequential nargin, and then reach image data exactly, and the effect of the reliability of the cross clock domain transmission of raising data-signal.

As a comparison, under above-mentioned scene, if select the rising edge of second clock signal to gather the first data-signal, the data-signal obtaining can be the data-signal being represented by oblique line as Fig. 5 the 4th row, easily find out, this data-signal collecting is less than the clock cycle half with respect to the sequential nargin of the first data-signal, and does not meet the requirement to above-mentioned sequential nargin corresponding with the second pre-set interval, and then may cause the lower problem of reliability of the cross clock domain transmission of data-signal.

By above-described embodiment, the operation principle of the scheme of the embodiment of the present invention is set forth.It should be noted that, in embodiments of the present invention, for the first pre-set interval, the sequential nargin that it limits is the first pre-set interval itself conventionally, and for the second pre-set interval, partial section in the second pre-set interval is set to be positioned at (0, T/2) time, the sequential nargin being limited by this partial section adds the clock cycle half for this partial section, partial section in the second pre-set interval is set to be positioned at (T/2, T) time, the sequential nargin being limited by this partial section deducts the clock cycle by practical manifestation half for this partial section.That is to say, if the sequential nargin that requires the cross clock domain of data-signal to transmit on transmission path is larger, the first pre-set interval can be arranged in (T/2, T), and the second pre-set interval is arranged on to (0, T/2) in, otherwise the two can be exchanged, the first pre-set interval is arranged on (0, T/2) in, and the second pre-set interval is arranged in (T/2, T).For concrete setting and the application thereof of the first pre-set interval and the second pre-set interval, the present invention is not limited in any way.

Certainly, above-mentioned conclusion is mainly to align with the first clock signal based on the first data-signal, and the corresponding relation of the second data-signal and second clock signal alignment is derived, in some other embodiment of the present invention, other forms of expression for this corresponding relation, can be in conjunction with the definite phase relation between the definite phase relation between the first data-signal and the first clock signal and the second data-signal and second clock signal, draw the scope of the sequential nargin being limited by the first pre-set interval and the second pre-set interval respectively after twice skew corresponding with these two phase relations, the present invention does not do tired stating at this.

What need to further illustrate is, the present invention is not limited in any way the purposes of the source of the first data-signal and purposes and the second data-signal, wherein, the corresponding relation of the first data-signal and the first clock signal can derive from the obtain manner of the first data-signal conventionally, for example, in some embodiments of the invention, the first data-signal can be rising edge or the resulting data-signal of the corresponding data of trailing edge collection that uses the first clock signal, and this collection can be for once, also can be for repeatedly.Yet this does not also mean that the present invention has been formed to restriction, in embodiments of the present invention, obtain before the first data-signal and can also comprise other processing modes to the preprocessing process of this data-signal, such as thering are the delay disposal of definite time delay or anti-phase processing etc.In addition, the present invention is not limited in any way the data content of the first data-signal and the second data-signal, for example, in some embodiments of the invention, this first data-signal can represent the memory address in memory, the second data-signal both can represent memory address, also can represent the represented memory address of data-signal obtaining according to gathering the first data-signal, the storage data of reading from memory, wherein, the memory address being represented by the first data-signal can be corresponding with the first clock signal in sequential, and the memory address being represented by the second data-signal or storage data can be corresponding with second clock signal in sequential, under this scene, can input by the write address using the first data-signal as memory, using another data-signal as this memory, write data inputs, and the address of reading that the second data-signal can be this memory is inputted, or the data-signal that collection the first data-signal is obtained is as the read data output of reading resulting this memory of address input of this memory, thereby can transmit by the cross clock domain of the first data-signal to realize the transmission of the cross clock domain of above-mentioned " another data-signal ".This execution mode is particularly useful for to the less demanding of the delay of the cross clock domain transmission of this " another data-signal " but to its accuracy and the higher application scenarios of reliability requirement, yet the present invention is to this and be not construed as limiting.

Also it should be noted that, in embodiments of the present invention, above-mentioned the first data-signal can be both serial data signal, also can be parallel data signal, wherein, for serial data signal, its data width both can be 1, also can be multidigit, its concrete processing mode can be described in above-described embodiment, for parallel data signal, if its multichannel data signal is synchronous transmission, can adopt the processing mode that is similar to multidigit serial data signal to process, if its multichannel data signal is asynchronous, its each road signal can be processed respectively as the first data-signal.

On basis described above, the processing method of the data-signal providing according to the embodiment of the present invention, in step S106, can obtain the second data-signal according to gathering the resulting data-signal of the first data-signal, in other words, in embodiments of the present invention, after the first data-signal being gathered by step S104, both can be as shown in the previous embodiment, using the data that collect directly as the second data-signal, also can need to carry out follow-up other feasible processing to gathering the data-signal that the first data-signal obtains according to concrete design, for example postpone, anti-phase, again gather, deposit a bat or many bats etc., and the data-signal obtaining after processing is as the second data-signal, yet should be understood that, in above-mentioned processing procedure, all should work as the processing belonging in the clock zone of second clock signal, also be, the second data-signal obtaining still should be corresponding with second clock signal.

For example, alternatively, in embodiments of the present invention, step S106 can comprise:

S1: carry out N following operation: use rising edge or the trailing edge of second clock signal again to gather the front data-signal once collecting, wherein, before the initial value of the data-signal that once collects for gathering the resulting data-signal of the first data-signal, N is more than or equal to 1;

S2: using the data-signal collecting after N operation as the second data-signal.

Under above-mentioned scene, can be after the first data-signal being gathered by step S104, in step S1, to gathering the resulting data-signal of the first data-signal, again gather, and the operation that should " again gather " can repeat N time, N is more than or equal to 1, wherein, it should be noted that, in embodiments of the present invention, N operation is not limited to be " rising edge that uses second clock signal " or " using the trailing edge of second clock signal ", for example, in one embodiment, certain once-through operation in N operation can be used rising edge collection, the next operation of this operation can be used trailing edge collection, the present invention is not construed as limiting this.

Be to be understood that, in embodiments of the present invention, utilize that the hopping edge of second clock signal carries out the N time resulting data-signal of acquisition operations again, also the second data-signal will the clock zone in second clock signal in, generally speaking, for comprising, described in step S104, above-mentioned " front once gather " of the acquisition operations of the first data-signal used to the situation of the rising edge of second clock signal, for the collection again of carrying out after this front once collection, if still use the rising edge of second clock signal, be equivalent to the front data-signal once collecting to postpone a clock cycle, deposit in other words a bat, if change the trailing edge that uses second clock signal into, be equivalent to the front data-signal once collecting to postpone the clock cycle half, deposit in other words half bat, accordingly, for the front situation that once gathers the trailing edge that has used second clock signal, also can obtain similar effect.Wherein, no matter deposit the situation that half bat, is clapped or clapped more, sequential nargin in again gathering has the clock cycle at least half, therefore can avoid the accuracy that causes due to the sequential nargin deficiency of data-signal on transmission path and the problem of reliability decrease.

Particularly, in embodiments of the present invention, step S106 can comprise:

S3: if above-mentioned phase difference is positioned at the first pre-set interval, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the first data-signal, and using the data-signal again collecting as the second data-signal; And/or,

S4: if above-mentioned phase difference is positioned at the second pre-set interval, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the first data-signal, and using the data-signal again collecting as the second data-signal.

In embodiments of the present invention, step S3 or step S4 can be combined with step S104, to obtain the second data-signal that keeps the second data-signal align with the rising edge of second clock signal or maintenance to align with the trailing edge of second clock signal.For example, in one embodiment, can be using step S3 as step S106, under this scene, if above-mentioned phase difference is positioned at the first pre-set interval, can first use the rising edge of second clock signal to gather the first data-signal by step S104, then by step S3, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the first data-signal, to be met the requirement to sequential nargin, and the second data-signal aliging with the trailing edge of second clock signal, if above-mentioned phase difference is positioned at the second pre-set interval, can use the trailing edge of second clock signal to gather the first data-signal by step S104, and be met the requirement to sequential nargin, and the second data-signal aliging with the trailing edge of second clock signal, the second data-signal that adopts aforesaid way to obtain can guarantee to align with the trailing edge of second clock signal, and with above-mentioned phase difference, to be positioned at the first pre-set interval or the second pre-set interval irrelevant, thereby can be conveniently to the use of this second data-signal and subsequent treatment.Similarly, in embodiments of the present invention, can also be using step S4 as step S106, and be met the requirement of sequential nargin and the second data-signal of aliging with the rising edge of second clock signal, the present invention does not do tired stating at this.

Further, consider dual-magnification technique transfer of data DDR(Double Data Rate) demand to rising edge data and trailing edge data simultaneously, in embodiments of the present invention, the first data-signal can comprise the 3rd data-signal and the 4th data-signal, the second data-signal can comprise the 5th data-signal and the 6th data-signal, wherein, step S106 can comprise:

S5: if phase difference is positioned at the first pre-set interval, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the 3rd data-signal, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will again gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal; If phase difference is positioned at the second pre-set interval, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal; Or,

S6: if phase difference is positioned at the first pre-set interval, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal; If phase difference is positioned at the second pre-set interval, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the 3rd data-signal, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will again gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal.

In embodiments of the present invention, the 3rd data-signal and the 4th data-signal as the first data-signal are all corresponding with the first clock signal, and in step S104, the selectivity collection of the first data-signal is also applicable to the collection to the 3rd data-signal and the 4th data-signal, and then can obtains the 5th data-signal and the 6th data-signal as the second data-signal according to the data-signal collecting.

As a kind of optional mode, can be using step S5 as step S106,, when above-mentioned phase difference is positioned at the first pre-set interval, above-mentioned gatherer process can show as:

The 3rd data-signal---rising edge (S104)---trailing edge (S5)---the 5th data-signal;

The 4th data-signal---rising edge (S104)---rising edge (S5)---the 6th data-signal;

When above-mentioned phase difference is positioned at the second pre-set interval, above-mentioned gatherer process can show as:

The 3rd data-signal---trailing edge (S104)---the 5th data-signal;

The 4th data-signal---trailing edge (S104)---rising edge (S5)---the 6th data-signal.

Easily find out, feature as this execution mode, first, by resulting the 5th data-signal of the processing of the 3rd data-signal is alignd with the trailing edge of second clock signal, by resulting the 6th data-signal of the processing of the 4th data-signal is alignd with the rising edge of second clock signal, secondly, the 5th data-signal with respect to the 6th data-signal in advance half clock cycle, half clap in advance in other words.On this basis, in embodiments of the present invention, can utilize These characteristics further the 5th data-signal and the 6th data-signal to be processed, to obtain the data-signal of the sequential requirement that meets DDR, for example, alternatively, after step S5, above-mentioned processing method can also comprise:

S7: be 1 o'clock at second clock signal, output the 5th data-signal, is 0 o'clock at second clock signal, output the 6th data-signal; Or,

S8: be 0 o'clock at second clock signal, output the 5th data-signal, is 1 o'clock at second clock signal, output the 6th data-signal.

Wherein, because the 5th data-signal aligns with the trailing edge of second clock signal, the 6th data-signal aligns with the rising edge of second clock signal, and the 5th data-signal shifts to an earlier date half clock cycle with respect to the 6th data-signal, therefore by step S7 or step S8, can obtain respectively and take the rising edge of second clock signal or trailing edge as initial, the data that the 5th data-signal represents within a clock cycle are front, the data that the 6th data-signal represents after double audio data signal, thereby reached the object of carrying the entrained data of two paths of data signal by a circuit-switched data signal, also realized the data transmission mechanism of DDR.

Preferably, in embodiments of the present invention, can adopt the frequency multiplication mode described in step S7, wherein, because the 5th data-signal aligns with the trailing edge of second clock signal, therefore when second clock signal becomes 1 from 0, while also welcoming rising edge, the 5th data-signal has continued the clock cycle half after renewal, therefore the 5th data-signal of exporting when second clock signal is 1 will be comparatively stable, accordingly, because the 6th data-signal aligns with the rising edge of second clock signal, therefore when second clock signal becomes 0 from 1, while also welcoming trailing edge, the 6th data-signal has continued the clock cycle half after renewal, therefore the 6th data-signal of exporting when second clock signal is 0 also will be comparatively stable.

As the optional mode of another kind, can be using step S6 as step S106,, when above-mentioned phase difference is positioned at the first pre-set interval, above-mentioned gatherer process can show as:

The 3rd data-signal---rising edge (S104)---the 5th data-signal;

The 4th data-signal---rising edge (S104)---trailing edge (S6)---the 6th data-signal;

The 3rd data-signal---trailing edge (S104)---rising edge (S6)---the 5th data-signal;

The 4th data-signal---trailing edge (S104)---trailing edge (S6)---the 6th data-signal.

Easily find out, the acquisition strategies that this execution mode and above-mentioned a kind of optional execution mode are taked is symmetrical, feature as this execution mode, first, by resulting the 5th data-signal of the processing of the 3rd data-signal is alignd with the rising edge of second clock signal, by resulting the 6th data-signal of the processing of the 4th data-signal is alignd with the trailing edge of second clock signal, secondly, the 5th data-signal with respect to the 6th data-signal in advance half clock cycle, half clap in advance in other words.Similarly, on this basis, if carry out further the operation described in above-mentioned steps S7 or step S8, can obtain equally take the rising edge of second clock signal or trailing edge as data initial, that the 5th data-signal represents within a clock cycle data front, that the 6th data-signal represents after double audio data signal, and realize the data transmission mechanism that DDR is corresponding.

Preferably, in embodiments of the present invention, can adopt the frequency multiplication mode described in step S8, wherein, because the 5th data-signal aligns with the rising edge of second clock signal, therefore when second clock signal becomes 0 from 1, while also welcoming trailing edge, the 5th data-signal has continued the clock cycle half after renewal, therefore the 5th data-signal of exporting when second clock signal is 0 will be comparatively stable, accordingly, because the 6th data-signal aligns with the trailing edge of second clock signal, therefore when second clock signal becomes 1 from 0, while also welcoming rising edge, the 6th data-signal has continued the clock cycle half after renewal, therefore the 6th data-signal of exporting when second clock signal is 1 also will be comparatively stable.

By above-described embodiment the present invention, provided two kinds of optional embodiments, yet should be appreciated that above-described embodiment, only for the understanding to technical solution of the present invention, should not be considered as limitation of the invention.In embodiments of the present invention, can also there be other feasible execution modes, at this, do not tire out and state one by one, should be appreciated that these execution modes all should be considered as within protection scope of the present invention.

On basis described above, more specifically, in embodiments of the present invention, above-mentioned the first clock signal can be the system clock of Memory Controller Hub, above-mentioned second clock signal can be the data clock of writing of Memory Controller Hub, above-mentioned the first data-signal can be the data to be transmitted of Memory Controller Hub, above-mentioned the second data-signal can be the write data of Memory Controller Hub to memory chip transmission, wherein, this writes data clock can be identical with the clock cycle of the internal memory clock of memory chip, and write and between data clock and internal memory clock, can meet default sequential requirement.

Under this scene, the processing method of the data-signal providing in conjunction with the embodiment of the present invention, can realize data to be transmitted effective transmission to memory chip by Memory Controller Hub, wherein, this data to be transmitted can be obtained or be generated by Memory Controller Hub, the data-signal corresponding with system clock, and can be the data-signal corresponding with writing data clock through the resulting data of writing of above-mentioned processing operation, so that internal memory is to writing reception and the identification of data.Wherein, although write data clock, also can obtain or generate by Memory Controller Hub, yet this be write and between data clock and internal memory clock, should meet default sequential requirement.The adjusting operation that this is write to data clock will provide in subsequent embodiment.

Generally speaking, in embodiments of the present invention, above-mentioned default sequential requires conventionally can show as: according to the data of writing of writing data clock generation, when arriving memory chip, with respect to internal memory clock, shift to an earlier date K clock cycle, K is the arbitrary value between 0 to 1.This requirement is conventionally relevant to DDR agreement, for example, existing DDR agreement regulation writes data to while reaching memory chip, the hopping edge of internal memory clock should be positioned at this that obtained by memory chip and write the middle part of data, this writes data to while reaching memory chip and should shift to an earlier date about 1/4 or 3/4 clock cycle with respect to internal memory clock in other words, thereby K can be set to 1/4 or 3/4, yet the present invention is not construed as limiting this, in some other embodiment of the present invention, for different internal storage data host-host protocols, the occurrence of K also can be set to other numerical value between 0 to 1.

Further alternatively, in embodiments of the present invention, before step S102, above-mentioned processing method can also comprise:

S10: before meeting and requiring corresponding termination executive condition with default sequential, repeat M time and operate below:

S11, adjust and to write data clock or with respect to the 3rd clock signal of writing K the clock cycle of data clock hysteresis forward or backward, and to memory chip transmission with after adjustment, write the 7th data-signal corresponding to the 3rd clock signal after data clock or adjustment;

The 8th data-signal that S12, reception memory chip return according to the 7th data-signal, and judge whether to meet termination executive condition according to the 8th data-signal receiving; Wherein, M is more than or equal to 1.

By step S11 and the formed circulation of S12, be may be summarized to be: adjust---conveying---process of feedback, wherein, whether the 8th data-signal that memory chip is fed back according to the 7th data-signal to its conveying can carry conventionally with " meet and stop executive condition " " is write between data clock and internal memory clock and whether meets and preset sequential requirement " corresponding information in other words, whether therefore by the identification judgement to the 8th data-signal, can judge circulation stops, and can be by the resulting data clock of writing after above-mentioned M operation, or as the cross clock domain that carries out data-signal, transmit definite second clock signal before according to the determined data clock of writing of the 3rd clock signal obtaining after M operation, using the basis of selecting according to phase difference as in step S104.It should be noted that; above-mentioned circulation can also have other equivalent variations; for example; a circulation roughly the same also may be summarized to be: carry---feedback---process of adjusting according to feedback; the division that the present invention once circulates in other words to the single operation of M operation is also not construed as limiting, and based on each embodiment described above, all should be considered as within protection scope of the present invention.

Generally speaking, in embodiments of the present invention, what the termination executive condition of above-mentioned M operation can require corresponding to default sequential reaches, for example, in one embodiment, the 7th data-signal can be set to the pulse signal aliging with rising edge or the trailing edge of the 3rd clock signal, the 8th data-signal can represent that memory chip is used the resulting data-signal of pulse signal acquisition internal memory clock, wherein, if the 7th data-signal aligns with the rising edge of the 3rd clock signal, stop executive condition and can be: the 8th data-signal of reception becomes 1 from 0; If the 7th data-signal aligns with the trailing edge of the 3rd clock signal, end executive condition and can be: the 8th data-signal of reception becomes 0 from 1.

Wherein, because the 3rd clock signal is with respect to writing K the clock cycle of data clock hysteresis, therefore if require, according to writing the data of writing that data clock generates, when arriving memory chip, with respect to internal memory clock, shift to an earlier date K clock cycle, should require the 7th data-signal that generates according to the 3rd clock signal when arrival memory chip and internal memory clock alignment.On the other hand, the 7th data-signal receiving according to it when memory chip gathers resulting the 8th data-signal of internal memory clock when 0 becomes 1, can be considered as having captured as the pulse signal of the 7th data-signal the rising edge of the 8th data-signal, when the 8th data-signal is when 1 becomes 0, can be considered as the trailing edge that this pulse signal has captured the 8th data-signal.Therefore, if the 7th data-signal aligns with the rising edge of the 3rd clock signal, require corresponding termination executive condition can be set to just capture when the 7th data-signal arrives memory chip the rising edge of internal memory clock with default sequential, also the 8th data-signal becomes 1 from 0, if the 7th data-signal aligns with the trailing edge of the 3rd clock signal, require corresponding termination executive condition can be set to just capture when the 7th data-signal arrives memory chip the trailing edge of internal memory clock with default sequential, also the 8th data-signal becomes 0 from 1.

Especially, for DDR3, in some embodiments of the invention, the write leveling function that can utilize DDR3 internal memory to provide, under this scene, can first DDR3 internal memory be placed in to write leveling pattern, and using write data strobe signal (writing DQS) as the 3rd clock signal, and then carry out above-mentioned M operation.

Further, in embodiments of the present invention, therefore owing to can reflect the phase shift of writing data clock as second clock signal to writing the adjustment of data clock and/or the 3rd clock signal in step S11, also can draw conduct selection the first clock signal of foundation and the phase difference of second clock signal in step S104 according to adjustment operate for above-mentioned M time.Wherein, alternatively,

Before carrying out and operating for M time, above-mentioned processing method can also comprise: S13, using the clock signal of aliging with system clock as the initial value of writing data clock or the 3rd clock signal;

When carrying out M operation, in step S11, adjust forward or backward and write data clock and/or the 3rd clock signal can comprise: S14, postpone to write data clock or a 3rd clock signal 1/L clock cycle, as writing data clock or the 3rd clock signal after adjusting, L is positive integer; And,

After carrying out and operating for M time, above-mentioned processing method can also comprise: if S15 is using the clock signal of aliging with system clock as writing data clock, according to following formula, obtain phase difference: the * T of Δ=(M/L); If S16, using the clock signal of aliging with system clock as the 3rd clock signal, obtains phase difference according to following formula: the * T of Δ=(M/L-K); Wherein, Δ represents phase difference, and T represents the clock cycle.

Under above-mentioned scene, the value of L is larger, less to writing the adjustment amount of data clock or the 3rd clock signal in single operation, the calibration that this is write to data clock or the 3rd clock signal is approximately accurate, the sequential of writing between data clock and internal memory clock is more preset sequential requirement for approaching, on the other hand, the phase difference drawing is accordingly more also accurately, thereby the processing method of above-mentioned data-signal is also got over as accurate the control of the sequential nargin on the transmission path of its cross clock domain transmission.

The invention provides a kind of preferred embodiment and come further the present invention to be made an explanation, but it should be noted that the preferred embodiment, just in order better to describe the present invention, does not form the present invention is limited improperly.

Embodiment 2

According to the embodiment of the present invention, also provide a kind of for implementing the processing unit of data-signal of the processing method of above-mentioned data-signal, as shown in Figure 6, this processing unit comprises:

1) acquiring unit 602, and for obtaining the first data-signal and second clock signal, wherein, the first data-signal is corresponding with the first clock signal, and the clock cycle of the first clock signal is identical with the clock cycle of second clock signal;

2) selected cell 604, for when the first clock signal is positioned at the first pre-set interval with respect to the phase difference of second clock signal, use the rising edge of second clock signal to gather the first data-signal, when phase difference is positioned at the second pre-set interval, use the trailing edge of second clock signal to gather the first data-signal;

3) processing unit 606, and for obtaining the second data-signal according to gathering the resulting data-signal of the first data-signal, wherein, the second data-signal is corresponding with second clock signal.

Will be clear that, one of technical solution of the present invention technical problem to be solved is to provide a kind of device that data-signal is processed, to realize the transmission to the cross clock domain of this data-signal, also be, the data-signal corresponding with clock signal is converted to the data-signal corresponding with another clock signal, and the content of these two data-signals is identical, wherein, for ease of statement, above-mentioned " clock signal " is designated as to the first clock signal, above-mentioned " another clock signal " is designated as to second clock signal, and this data-signal corresponding with the first clock signal is designated as to the first data-signal, to be designated as the second data-signal in this data-signal corresponding to second clock signal.

For addressing this problem, in embodiments of the present invention, can utilize second clock signals collecting the first data-signal to generate the mode of the second data-signal along holding, and in acquiring unit 602, obtain this first data-signal and this second clock signal, yet the prior art of being different from, the processing unit providing according to the embodiment of the present invention, in selected cell 604, can select using between the rising edge of second clock signal or trailing edge according to the phase relation between the first clock signal and second clock signal, wherein, if the first clock signal is positioned at the first pre-set interval with respect to the phase difference of second clock signal, can use the rising edge of second clock signal to gather the first data-signal, if phase difference is positioned at the second pre-set interval, can use the trailing edge of second clock signal to gather the first data-signal.In other words, in embodiments of the present invention, not use statically the rising edge of second clock signal or trailing edge to gather the first data-signal, but can for different situations, select one of rising edge and trailing edge to gather in relative dynamic ground, thereby realize the control of the sequential nargin on the transmission path across clock transfer to data-signal, and then reach the requirement to this sequential nargin.

As shown in Figure 4, under a scene of the embodiment of the present invention, the first clock signal can be clock signal as shown in the 1st row, and the first data-signal can be the data-signal as shown in the 2nd row, and second clock signal can be the clock signal as shown in the 3rd row.Under above-mentioned scene, the first clock signal is greater than the clock cycle half with respect to the phase difference of second clock signal, also be positioned at the first pre-set interval (T/2, T) in, thereby according to selected cell 604, rising edge that can choice for use second clock signal gathers the first data-signal, and obtains data-signal as shown in the 4th row as the second data-signal.Easily find out, under above-mentioned scene, the first data-signal is corresponding with the first clock signal, the second data-signal is corresponding with second clock signal, and the data content of the second data-signal is consistent with the first data-signal, also realized the cross clock domain transmission of the first data-signal, on the other hand, sequential nargin on the transmission path of this cross clock domain transmission equals above-mentioned phase difference, and above-mentioned phase difference is positioned at the first pre-set interval, be greater than the clock cycle half, therefore this sequential nargin is greater than the clock cycle half, also be, in embodiments of the present invention, to the control of sequential nargin, can partly by the first pre-set interval, be realized, thereby can by the reasonable setting of the first pre-set interval to meet the requirement to this sequential nargin, and then reach image data exactly, and the effect of the reliability of the cross clock domain transmission of raising data-signal.

As shown in Figure 5, under another scene of the embodiment of the present invention, the first clock signal can be clock signal as shown in the 1st row, and the first data-signal can be the data-signal as shown in the 2nd row, and second clock signal can be the clock signal as shown in the 3rd row.Under above-mentioned scene, the first clock signal is less than the clock cycle half with respect to the phase difference of second clock signal, also be positioned at the second pre-set interval (0, T/2) in, thereby according to selected cell 604, trailing edge that can choice for use second clock signal gathers the first data-signal, and obtains data-signal as shown in the 5th row as the second data-signal.Easily find out, under above-mentioned scene, on the basis of cross clock domain transmission of realizing the first data-signal, sequential nargin on the transmission path of this cross clock domain transmission equals above-mentioned phase difference and adds the clock cycle half, and above-mentioned phase difference is positioned at the second pre-set interval, be less than the clock cycle half, therefore this sequential nargin is greater than the clock cycle half, also be, in embodiments of the present invention, to the control of sequential nargin, can partly by the second pre-set interval, be realized, thereby can by the reasonable setting of the second pre-set interval to meet the requirement to this sequential nargin, and then reach image data exactly, and the effect of the reliability of the cross clock domain transmission of raising data-signal.

On basis described above, the processing unit of the data-signal providing according to the embodiment of the present invention, in processing unit 606, can obtain the second data-signal according to gathering the resulting data-signal of the first data-signal, in other words, in embodiments of the present invention, after gathering by 604 pairs of the first data-signals of selected cell, both can be as shown in the previous embodiment, using the data that collect directly as the second data-signal, also can need to carry out follow-up other feasible processing to gathering the data-signal that the first data-signal obtains according to concrete design, for example postpone, anti-phase, again gather, deposit a bat or many bats etc., and the data-signal obtaining after processing is as the second data-signal, yet should be understood that, in above-mentioned processing procedure, all should work as the processing belonging in the clock zone of second clock signal, also be, the second data-signal obtaining still should be corresponding with second clock signal.

For example, alternatively, in embodiments of the present invention, processing unit 606 can comprise:

1) Executive Module, be used for carrying out N following operation: use rising edge or the trailing edge of second clock signal again to gather the front data-signal once collecting, wherein, before the initial value of the data-signal that once collects for gathering the resulting data-signal of the first data-signal, N is more than or equal to 1;

2) output module, for using the data-signal that collects after N operation as the second data-signal.

Under above-mentioned scene, can be after gathering by 604 pairs of the first data-signals of selected cell, in Executive Module, to gathering the resulting data-signal of the first data-signal, again gather, and the operation that should " again gather " can repeat N time, N is more than or equal to 1, wherein, it should be noted that, in embodiments of the present invention, N operation is not limited to be " rising edge that uses second clock signal " or " using the trailing edge of second clock signal ", for example, in one embodiment, certain once-through operation in N operation can be used rising edge collection, the next operation of this operation can be used trailing edge collection, the present invention is not construed as limiting this.

Be to be understood that, in embodiments of the present invention, utilize that the hopping edge of second clock signal carries out the N time resulting data-signal of acquisition operations again, also the second data-signal will the clock zone in second clock signal in, generally speaking, for comprising, described in selected cell 604, above-mentioned " front once gather " of the acquisition operations of the first data-signal used to the situation of the rising edge of second clock signal, for the collection again of carrying out after this front once collection, if still use the rising edge of second clock signal, be equivalent to the front data-signal once collecting to postpone a clock cycle, deposit in other words a bat, if change the trailing edge that uses second clock signal into, be equivalent to the front data-signal once collecting to postpone the clock cycle half, deposit in other words half bat, accordingly, for the front situation that once gathers the trailing edge that has used second clock signal, also can obtain similar effect.Wherein, no matter deposit the situation that half bat, is clapped or clapped more, sequential nargin in again gathering has the clock cycle at least half, therefore can avoid the accuracy that causes due to the sequential nargin deficiency of data-signal on transmission path and the problem of reliability decrease.

Particularly, in embodiments of the present invention, processing unit 606 can comprise:

1) the first processing module, for when phase difference is positioned at the first pre-set interval, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the first data-signal, and using the data-signal again collecting as the second data-signal; And/or,

2) the second processing module, for when phase difference is positioned at the second pre-set interval, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the first data-signal, and using the data-signal again collecting as the second data-signal.

In embodiments of the present invention, can be by the first processing module or the second processing module and selected cell 604 combinations, to obtain the second data-signal that keeps the second data-signal of aliging with the rising edge of second clock signal or maintenance to align with the trailing edge of second clock signal.For example, in one embodiment, can be using the first processing module as processing unit 606, under this scene, if above-mentioned phase difference is positioned at the first pre-set interval, can first use the rising edge of second clock signal to gather the first data-signal by selected cell 604, then by the first processing module, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the first data-signal, to be met the requirement to sequential nargin, and the second data-signal aliging with the trailing edge of second clock signal, if above-mentioned phase difference is positioned at the second pre-set interval, can use the trailing edge of second clock signal to gather the first data-signal by selected cell 604, and be met the requirement to sequential nargin, and the second data-signal aliging with the trailing edge of second clock signal, the second data-signal that adopts aforesaid way to obtain can guarantee to align with the trailing edge of second clock signal, and with above-mentioned phase difference, to be positioned at the first pre-set interval or the second pre-set interval irrelevant, thereby can be conveniently to the use of this second data-signal and subsequent treatment.Similarly, in embodiments of the present invention, can also be using the second processing module as processing unit 606, and be met the requirement of sequential nargin and the second data-signal of aliging with the rising edge of second clock signal, the present invention does not do tired stating at this.

Further, consider dual-magnification technique transfer of data DDR(Double Data Rate) demand to rising edge data and trailing edge data simultaneously, in embodiments of the present invention, the first data-signal can comprise the 3rd data-signal and the 4th data-signal, the second data-signal can comprise the 5th data-signal and the 6th data-signal, wherein, processing unit 606 can comprise:

1) the 3rd processing module, for when phase difference is positioned at the first pre-set interval, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the 3rd data-signal, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will again gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal; When phase difference is positioned at the second pre-set interval, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal; Or,

2) the 4th processing module, for when phase difference is positioned at the first pre-set interval, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal; When phase difference is positioned at the second pre-set interval, use the rising edge of second clock signal again to gather gathering the resulting data-signal of the 3rd data-signal, use the trailing edge of second clock signal again to gather gathering the resulting data-signal of the 4th data-signal, and will again gather the resulting data-signal of the 3rd data-signal as the 5th data-signal, will again gather the resulting data-signal of the 4th data-signal as the 6th data-signal.

In embodiments of the present invention, the 3rd data-signal and the 4th data-signal as the first data-signal are all corresponding with the first clock signal, and in selected cell 604, the selectivity collection of the first data-signal is also applicable to the collection to the 3rd data-signal and the 4th data-signal, and then can obtains the 5th data-signal and the 6th data-signal as the second data-signal according to the data-signal collecting.

As a kind of optional mode, can be using the 3rd processing module as processing unit 606,, when above-mentioned phase difference is positioned at the first pre-set interval, above-mentioned gatherer process can show as:

The 3rd data-signal---rising edge (selected cell)---trailing edge (the 3rd processing module)---the 5th data-signal;

The 4th data-signal---rising edge (selected cell)---rising edge (the 3rd processing module)---the 6th data-signal;

The 3rd data-signal---trailing edge (selected cell)---the 5th data-signal;

The 4th data-signal---trailing edge (selected cell)---rising edge (the 3rd processing module)---the 6th data-signal.

Easily find out, feature as this execution mode, first, by resulting the 5th data-signal of the processing of the 3rd data-signal is alignd with the trailing edge of second clock signal, by resulting the 6th data-signal of the processing of the 4th data-signal is alignd with the rising edge of second clock signal, secondly, the 5th data-signal with respect to the 6th data-signal in advance half clock cycle, half clap in advance in other words.On this basis, in embodiments of the present invention, can utilize These characteristics further the 5th data-signal and the 6th data-signal to be processed, to obtain the data-signal of the sequential requirement that meets DDR, for example, alternatively, with the 3rd processing module coupling ground, above-mentioned processing unit can also comprise:

1) the first output unit, for being 1 o'clock at second clock signal, output the 5th data-signal, is 0 o'clock at second clock signal, output the 6th data-signal; Or,

2) the second output unit, for being 0 o'clock at second clock signal, output the 5th data-signal, is 1 o'clock at second clock signal, output the 6th data-signal.

Wherein, because the 5th data-signal aligns with the trailing edge of second clock signal, the 6th data-signal aligns with the rising edge of second clock signal, and the 5th data-signal shifts to an earlier date half clock cycle with respect to the 6th data-signal, therefore by the first output unit or the second output unit, can obtain respectively and take the rising edge of second clock signal or trailing edge as initial, the data that the 5th data-signal represents within a clock cycle are front, the data that the 6th data-signal represents after double audio data signal, thereby reached the object of carrying the entrained data of two paths of data signal by a circuit-switched data signal, also realized the data transmission mechanism of DDR.

Preferably, in embodiments of the present invention, can adopt the frequency multiplication mode described in the first output unit, wherein, because the 5th data-signal aligns with the trailing edge of second clock signal, therefore when second clock signal becomes 1 from 0, while also welcoming rising edge, the 5th data-signal has continued the clock cycle half after renewal, therefore the 5th data-signal of exporting when second clock signal is 1 will be comparatively stable, accordingly, because the 6th data-signal aligns with the rising edge of second clock signal, therefore when second clock signal becomes 0 from 1, while also welcoming trailing edge, the 6th data-signal has continued the clock cycle half after renewal, therefore the 6th data-signal of exporting when second clock signal is 0 also will be comparatively stable.

As the optional mode of another kind, can be using the 4th processing module as processing unit 606,, when above-mentioned phase difference is positioned at the first pre-set interval, above-mentioned gatherer process can show as:

The 3rd data-signal---rising edge (selected cell)---the 5th data-signal;

The 4th data-signal---rising edge (selected cell)---trailing edge (the 4th processing module)---the 6th data-signal;

The 3rd data-signal---trailing edge (selected cell)---rising edge (the 4th processing module)---the 5th data-signal;

The 4th data-signal---trailing edge (selected cell)---trailing edge (the 4th processing module)---the 6th data-signal.

Easily find out, the acquisition strategies that this execution mode and above-mentioned a kind of optional execution mode are taked is symmetrical, feature as this execution mode, first, by resulting the 5th data-signal of the processing of the 3rd data-signal is alignd with the rising edge of second clock signal, by resulting the 6th data-signal of the processing of the 4th data-signal is alignd with the trailing edge of second clock signal, secondly, the 5th data-signal with respect to the 6th data-signal in advance half clock cycle, half clap in advance in other words.Similarly, on this basis, if carry out further the operation described in above-mentioned the first output unit or the second output unit, can obtain equally take the rising edge of second clock signal or trailing edge as data initial, that the 5th data-signal represents within a clock cycle data front, that the 6th data-signal represents after double audio data signal, and realize the data transmission mechanism that DDR is corresponding.

Preferably, in embodiments of the present invention, can adopt the frequency multiplication mode described in the second output unit, wherein, because the 5th data-signal aligns with the rising edge of second clock signal, therefore when second clock signal becomes 0 from 1, while also welcoming trailing edge, the 5th data-signal has continued the clock cycle half after renewal, therefore the 5th data-signal of exporting when second clock signal is 0 will be comparatively stable, accordingly, because the 6th data-signal aligns with the trailing edge of second clock signal, therefore when second clock signal becomes 1 from 0, while also welcoming rising edge, the 6th data-signal has continued the clock cycle half after renewal, therefore the 6th data-signal of exporting when second clock signal is 1 also will be comparatively stable.

Under this scene, the processing unit of the data-signal providing in conjunction with the embodiment of the present invention, can realize data to be transmitted effective transmission to memory chip by Memory Controller Hub, wherein, this data to be transmitted can be obtained or be generated by Memory Controller Hub, the data-signal corresponding with system clock, and can be the data-signal corresponding with writing data clock through the resulting data of writing of above-mentioned processing operation, so that internal memory is to writing reception and the identification of data.Wherein, although write data clock, also can obtain or generate by Memory Controller Hub, yet this be write and between data clock and internal memory clock, should meet default sequential requirement.The adjusting operation that this is write to data clock will provide in subsequent embodiment.

Further alternatively, in embodiments of the present invention, before acquiring unit 602, above-mentioned processing unit can also comprise:

1) adjustment unit, for before meeting and requiring corresponding termination executive condition with default sequential, repeat M following operation: adjust forward or backward and write data clock or with respect to the 3rd clock signal of writing K the clock cycle of data clock hysteresis, and to memory chip transmission with after adjustment, write the 7th data-signal corresponding to the 3rd clock signal after data clock or adjustment; Receive the 8th data-signal that memory chip returns according to the 7th data-signal, and judge whether to meet termination executive condition according to the 8th data-signal receiving; Wherein, M is more than or equal to 1.

In adjustment unit, a formed circulation may be summarized to be: adjust---conveying---process of feedback, wherein, whether the 8th data-signal that memory chip is fed back according to the 7th data-signal to its conveying can carry conventionally with " meet and stop executive condition " " is write between data clock and internal memory clock and whether meets and preset sequential requirement " corresponding information in other words, whether therefore by the identification judgement to the 8th data-signal, can judge circulation stops, and can be by the resulting data clock of writing after above-mentioned M operation, or as the cross clock domain that carries out data-signal, transmit definite second clock signal before according to the determined data clock of writing of the 3rd clock signal obtaining after M operation, using the basis of selecting according to phase difference as in selected cell 604.It should be noted that; above-mentioned circulation can also have other equivalent variations; for example; a circulation roughly the same also may be summarized to be: carry---feedback---process of adjusting according to feedback; the division that the present invention once circulates in other words to the single operation of M operation is also not construed as limiting, and based on each embodiment described above, all should be considered as within protection scope of the present invention.

Further, in embodiments of the present invention, therefore owing to can reflect the phase shift of writing data clock as second clock signal to writing the adjustment of data clock and/or the 3rd clock signal in adjustment unit, also can draw conduct selection the first clock signal of foundation and the phase difference of second clock signal in selected cell 604 according to adjustment operate for above-mentioned M time.Wherein, alternatively,

Processing unit can also comprise: initialization unit, for using the clock signal of aliging with system clock as the initial value of writing data clock or the 3rd clock signal;

Adjustment unit can comprise: Postponement module, and for postponing to write data clock or a 3rd clock signal 1/L clock cycle, as writing data clock or the 3rd clock signal after adjustment, L is positive integer;

Processing unit can also comprise: computing module, for using the clock signal of aliging with system clock when writing data clock, according to following formula, obtain phase difference: the * T of Δ=(M/L); When using the clock signal of aliging with system clock as the 3rd clock signal, according to following formula, obtain phase difference: the * T of Δ=(M/L-K); Wherein, Δ represents phase difference, and T represents the clock cycle.

Under above-mentioned scene, the value of L is larger, less to writing the adjustment amount of data clock or the 3rd clock signal in single operation, the calibration that this is write to data clock or the 3rd clock signal is approximately accurate, the sequential of writing between data clock and internal memory clock is more preset sequential requirement for approaching, on the other hand, the phase difference drawing is accordingly more also accurately, thereby the processing unit of above-mentioned data-signal is also got over as accurate the control of the sequential nargin on the transmission path of its cross clock domain transmission.

Embodiment 3

According to the embodiment of the present invention, a kind of processing unit of the data-signal of realizing by hardware logic is also provided, as shown in Figure 7, this device can comprise:

1) register REG1, REG2, REG3, REG4, REG5, REG6 and REG7;

2) selector MUX1, MUX2 and MUX3;

Wherein, the annexation between each device can, with reference to figure 7, not repeat at this one by one.

As shown in Figure 7, in embodiments of the present invention, the input of the clock of REG1 and REG2 can be clock signal clk1, and wherein, clk1 can be used as the first clock signal as described in example 2 above.The data input of REG1 can be data-signal dq1, data output can be data-signal dq3, and dq3 can be considered as dq1 and gather resulting data-signal through clk1, thereby dq3 is synchronizeed with clk1, wherein, dq3 can be used as the 3rd data-signal as described in example 2 above.Similarly, the input of the data of REG2 can be data-signal dq2, and data output can be data-signal dq4, dq4 can be considered as dq2 and gather resulting data-signal through clk1, thereby dq4 is synchronizeed with clk2, wherein, dq4 can be used as the 4th data-signal as described in example 2 above.

By REG1 and/or REG2, can realize obtaining the data-signal with the first clock signal synchronization, and the obtaining second clock signal of the required execution of acquiring unit as described in example 2 above, can by a wiring, bring in realization simply, for example in Fig. 7, left side identifies the terminals that have clk2, input for clock signal clk2, wherein, clk2 can be used as second clock signal as described in example 2 above.

Further, in embodiments of the present invention, the selectivity acquisition operations of the required execution of selected cell can realize by REG3, REG4, REG5 and REG6 and selector MUX1 and MUX2 as described in Example 2.

As shown in Figure 7, the input of the clock of REG3, REG4, REG5 and REG6 can be clock signal clk2, and wherein, clk2 can be used as second clock signal as described in example 2 above.The data input of REG3 and REG6 can be dq3, the data input of REG4 and REG5 can be dq4, thereby REG3, REG4, REG5 and REG6 all can play the effect that gathers the data-signal dq3 of the clock zone that is positioned at clk1 or the data-signal of dq4 is positioned at clk2 clock zone with acquisition, have also realized the cross clock domain transmission of data-signal.

Particularly, as shown in Figure 7, the clock input of REG3 and REG4 is directly clk2, also use the rising edge of clk2 to gather, the clock input of REG5 and REG6 is separately by an inverter input clk2, also use the trailing edge of clk2 to gather, as for concrete, use the rising edge of clk2 or which in trailing edge gathers, can complete by selector MUX1 and MUX2, wherein, the low level input of MUX1 and MUX2 can the corresponding acquisition mode that uses clk2 rising edge, high level input can the corresponding acquisition mode that uses clk2 trailing edge, control inputs can be for inputting the signal of telecommunication pm corresponding to the phase difference between clk1 and clk2, wherein, this phase difference is positioned at the (T/2 of conduct the first pre-set interval as described in example 2 above, T) time, pm can be low level, and then can gather with the rising edge of clk2 the data-signal corresponding with clk1, this phase difference is positioned at (0 of conduct the second pre-set interval as described in example 2 above, T/2) time, pm can be high level, and then can gather with the trailing edge of clk2 the data-signal corresponding with clk1.

By above-mentioned optionally acquisition mode, can guarantee data-signal dq1 and the dq2 sequential nargin on cross clock domain transmission path, and then improve the accuracy of transfer of data, its concrete principle has a detailed description in embodiment 2, and the present invention does not do tired stating at this.

Further, as shown in Figure 7, passing through REG3, REG4 or REG5 are to being positioned at after the data-signal of the clock zone of clk1 gathers, can also again gather gathering resulting data-signal, wherein, when above-mentioned phase difference is positioned at the first pre-set interval, pm is low level, can pass through REG6, use the trailing edge of clk2 again to gather gather the resulting data-signal of dq3 by REG3, to obtain the dq5 of the 5th data-signal as described in example 2 above, and pass through REG7, use the rising edge of clk2 again to gather gather the resulting data-signal of dq4 by REG4, to obtain the 6th data-signal dq6 as described in example 2 above.Certainly, for processing unit as described in example 2 above, it also can directly export the data-signal that clk2 collects first, example as shown in Figure 7, when above-mentioned phase difference is positioned at the second pre-set interval, pm is high level, and dq3 is by directly by REG6, obtain described the 5th data-signal dq5 in the second data-signal as described in example 2 above via after once the gathering of the trailing edge of clk2, and the present invention is not construed as limiting this.

By circuit as shown in Figure 7, the present invention has in fact provided the hardware implementation mode of the 3rd processing module as described in example 2 above, and the 4th processing module is equivalent to the symmetrical execution mode of the 3rd processing module, and the present invention does not do tired stating at this.Wherein, as a kind of optimal design; in embodiments of the present invention; REG6 is used separately as a part for selected cell and processing unit as described in Example 2 under different situations; thereby saved at least one register; when reducing the wastage, improved the processing speed of processing unit, it should be noted that this type of all should be considered as within protection scope of the present invention the equivalence of the embodiment of the present invention or modification.

It should be noted that, in embodiments of the present invention, no matter be by the formed hardware logic electric circuit of REG1, REG3, MUX1 and REG6, or by the formed hardware logic electric circuit of REG2, REG4, REG5, MUX2 and REG7, it all can be considered as a kind of embodiment of processing unit as described in Example 2 separately, wherein, dq3 can be guaranteed respectively to the sequential nargin on dq4 cross clock domain transmission path separately to dq5 and dq2.Yet consider the double-speed transmission requirement of DDR, can also be further by dq3 dq1 in other words, and dq4 in other words the represented data of dq2 combine, as a circuit-switched data, export, particularly, as shown in Figure 7, can realize the merging to dq4 and dq5 by selector MUX3, wherein, the high level input of MUX3 can be the data output of REG6, the low level input of MUX3 can be the data output of REG7, control inputs can be clk2, thereby when clk2 is high level, MUX3 in other words processing unit can export dq5, when clk2 is low level, MUX3 in other words processing unit can export dq6, this has just met the requirement of DDR to transfer of data, and provided a kind of feasible hardware implementation mode of the first output unit as described in example 2 above, and the second output unit and the first output unit are symmetrical, the present invention does not do tired stating at this.

Further, in embodiments of the present invention, processing unit as shown in Figure 7 can be used as a part for the physics PHY module of Memory Controller Hub, because this processing unit is simple in structure and time delay is less, therefore with respect to existing or by software logic, realize there is the Memory Controller Hub of realizing identical function, adopt the processing speed of the Memory Controller Hub of the PHY module that comprises this processing unit will obtain significant lifting.Particularly, clk1 can be system clock, clk2 can be internal memory clock, dq1 can be a circuit-switched data of DDR transfer of data, dq2 can be its another circuit-switched data, and the output of MUX3 can be to write data to the internal memory of internal memory transmission, wherein, this is write data and is combined by the data content of dq1 and dq2, its message transmission rate is the twice of system clock frequency, and the processing unit providing by the embodiment of the present invention, can guarantee that the sequential nargin on cross clock domain transmission path is more than or equal to the clock cycle half, and then improve the accuracy of transfer of data.

It should be noted that, above-described embodiment is only for the understanding to technical solution of the present invention, and should not be considered as the present invention to form any unnecessary restriction, for example, in processing unit as shown in Figure 7, can also on transmission path, add more register, to reach, data-signal be carried out to a bat or the object of depositing of clapping more, similarly execution mode does not affect the enforcement of technical solution of the present invention and the realization of technique effect thereof, and the present invention is not limited in any way this yet.Should be understood that, similarly to expansion of the present invention and extension, all should be considered as within protection scope of the present invention.

As can be seen from the above description, the present invention has realized following technique effect:

1) adopted according to the phase difference between the first clock signal and second clock signal in the mode of using between the rising edge of second clock signal or trailing edge selecting between gathering with the first data-signal corresponding to the first clock signal, to obtain corresponding with second clock signal and to meet the second clock signal to the requirement of sequential nargin, thereby realized the control of the sequential nargin on the transmission path of cross clock domain transmission to data-signal;

2) by can meet the designing requirement to the cross clock domain transmission of data-signal to rationally arranging of the first pre-set interval and the second pre-set interval, and improve the reliability of the cross clock domain transmission of data-signal.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. a processing method for data-signal, is characterized in that, comprising:

Obtain the first data-signal and second clock signal, wherein, described the first data-signal is corresponding with the first clock signal, and the clock cycle of described the first clock signal is identical with the clock cycle of described second clock signal;

If described the first clock signal is positioned at the first pre-set interval with respect to the phase difference of described second clock signal, use the rising edge of described second clock signal to gather described the first data-signal; If described phase difference is positioned at the second pre-set interval, use the trailing edge of described second clock signal to gather described the first data-signal;

According to gathering the resulting data-signal of described the first data-signal, obtain the second data-signal, wherein, described the second data-signal is corresponding with described second clock signal.

2. processing method according to claim 1, is characterized in that, describedly according to gathering the resulting data-signal of described the first data-signal, obtains the second data-signal and comprises:

Carry out N following operation: use the rising edge of described second clock signal or trailing edge again to gather the front data-signal once collecting, wherein, the initial value of the data-signal once collecting before described is for gathering the resulting data-signal of described the first data-signal, and N is more than or equal to 1;

Using the data-signal collecting after described N operation as described the second data-signal.

3. processing method according to claim 1, is characterized in that, describedly according to gathering the resulting data-signal of described the first data-signal, obtains the second data-signal and comprises:

If described phase difference is positioned at described the first pre-set interval, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the first data-signal, and using the data-signal again collecting as described the second data-signal; And/or,

If described phase difference is positioned at described the second pre-set interval, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the first data-signal, and using the data-signal again collecting as described the second data-signal.

4. processing method according to claim 1, it is characterized in that, described the first data-signal comprises the 3rd data-signal and the 4th data-signal, described the second data-signal comprises the 5th data-signal and the 6th data-signal, wherein, describedly according to gathering the resulting data-signal of described the first data-signal, obtain the second data-signal and comprise:

If described phase difference is positioned at described the first pre-set interval, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the 3rd data-signal, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will again gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal; If described phase difference is positioned at described the second pre-set interval, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal; Or,

If described phase difference is positioned at described the first pre-set interval, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal; If described phase difference is positioned at described the second pre-set interval, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the 3rd data-signal, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will again gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal.

5. processing method according to claim 4, is characterized in that, described, according to gathering after the resulting data-signal of described the first data-signal obtains the second data-signal, also comprises:

At described second clock signal, being 1 o'clock, exporting described the 5th data-signal, is 0 o'clock at described second clock signal, exports described the 6th data-signal; Or, at described second clock signal, be 0 o'clock, export described the 5th data-signal, at described second clock signal, be 1 o'clock, export described the 6th data-signal.

6. processing method according to claim 1, is characterized in that, described the first pre-set interval is (T/2, T), described the second pre-set interval be (0, T/2).

7. according to the processing method described in any one in claim 1 to 5, it is characterized in that, the system clock that described the first clock signal is Memory Controller Hub, described second clock signal is described Memory Controller Hub writes data clock, the data to be transmitted that described the first data-signal is described Memory Controller Hub, described the second data-signal is that described Memory Controller Hub is to the data of writing of memory chip transmission, wherein, write data clock is identical with the clock cycle of the internal memory clock of described memory chip, and between write data clock and described internal memory clock, meet default sequential requirement.

8. processing method according to claim 7, it is characterized in that, described default sequential requires the write data for generating according to write data clock with respect to described internal memory clock, to shift to an earlier date K clock cycle when arriving described memory chip, K is the arbitrary value between 0 to 1, wherein, described obtain the first data-signal and second clock signal before, described processing method also comprises:

Before meeting and requiring corresponding termination executive condition with described default sequential, repeat M following operation: adjust forward or backward write data clock or with respect to the 3rd clock signal of K clock cycle of write data clock hysteresis, and to described memory chip transmission seven data-signal corresponding with write data clock after adjustment or described the 3rd clock signal after adjustment; Receive the 8th data-signal that described memory chip returns according to described the 7th data-signal, and judge whether to meet described termination executive condition according to described the 8th data-signal receiving; Wherein, M is more than or equal to 1.

9. processing method according to claim 8, it is characterized in that, the pulse signal of described the 7th data-signal for aliging with rising edge or the trailing edge of described the 3rd clock signal, described the 8th data-signal is that described memory chip is used the resulting data-signal of internal memory clock described in described pulse signal acquisition, wherein

If described the 7th data-signal aligns with the rising edge of described the 3rd clock signal, described termination executive condition is: described the 8th data-signal of reception becomes 1 from 0;

If described the 7th data-signal aligns with the trailing edge of described the 3rd clock signal, described termination executive condition is: described the 8th data-signal of reception becomes 0 from 1.

10. processing method according to claim 8, is characterized in that,

Before carrying out described operation for M time, described processing method also comprises: using the clock signal of aliging with described system clock as write data clock or the initial value of described the 3rd clock signal;

When carrying out described M operation, describedly adjust forward or backward write data clock and/or described the 3rd clock signal comprises: postpone write data clock or described a 3rd clock signal 1/L clock cycle, as write data clock or described the 3rd clock signal after adjusting, L is positive integer;

After carrying out described operation for M time, described processing method also comprises: if using the clock signal of aliging with described system clock as write data clock, obtain described phase difference according to following formula: the * T of Δ=(M/L); If using the clock signal of aliging with described system clock as described the 3rd clock signal, obtain described phase difference according to following formula: the * T of Δ=(M/L-K); Wherein, Δ represents described phase difference, and T represents the described clock cycle.

The processing unit of 11. 1 kinds of data-signals, is characterized in that, comprising:

Acquiring unit, for obtaining the first data-signal and second clock signal, wherein, described the first data-signal is corresponding with the first clock signal, and the clock cycle of described the first clock signal is identical with the clock cycle of described second clock signal;

Selected cell, for when described the first clock signal is positioned at the first pre-set interval with respect to the phase difference of described second clock signal, use the rising edge of described second clock signal to gather described the first data-signal, when described phase difference is positioned at the second pre-set interval, use the trailing edge of described second clock signal to gather described the first data-signal;

Processing unit, for obtaining the second data-signal according to gathering the resulting data-signal of described the first data-signal, wherein, described the second data-signal is corresponding with described second clock signal.

12. devices according to claim 11, is characterized in that, described processing unit comprises:

Executive Module, be used for carrying out N following operation: use the rising edge of described second clock signal or trailing edge again to gather the front data-signal once collecting, wherein, the initial value of the data-signal once collecting before described is for gathering the resulting data-signal of described the first data-signal, and N is more than or equal to 1;

Output module, for using the data-signal that collects after described N operation as described the second data-signal.

13. processing unit according to claim 11, is characterized in that, described processing unit comprises:

The first processing module, for when described phase difference is positioned at described the first pre-set interval, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the first data-signal, and using the data-signal again collecting as described the second data-signal; And/or,

The second processing module, for when described phase difference is positioned at described the second pre-set interval, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the first data-signal, and using the data-signal again collecting as described the second data-signal.

14. processing unit according to claim 11, it is characterized in that, described the first data-signal comprises the 3rd data-signal and the 4th data-signal, and described the second data-signal comprises the 5th data-signal and the 6th data-signal, wherein, described processing unit comprises:

The 3rd processing module, for when described phase difference is positioned at described the first pre-set interval, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the 3rd data-signal, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will again gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal; When described phase difference is positioned at described the second pre-set interval, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal; Or,

The 4th processing module, for when described phase difference is positioned at described the first pre-set interval, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal; When described phase difference is positioned at described the second pre-set interval, use the rising edge of described second clock signal again to gather gathering the resulting data-signal of described the 3rd data-signal, use the trailing edge of described second clock signal again to gather gathering the resulting data-signal of described the 4th data-signal, and will again gather the resulting data-signal of described the 3rd data-signal as described the 5th data-signal, will again gather the resulting data-signal of described the 4th data-signal as described the 6th data-signal.

15. processing unit according to claim 14, is characterized in that, also comprise:

The first output unit, for being at described second clock signal, exports described the 5th data-signal at 1 o'clock, at described second clock signal, is 0 o'clock, exports described the 6th data-signal; Or,

The second output unit, for being at described second clock signal, exports described the 5th data-signal at 0 o'clock, at described second clock signal, is 1 o'clock, exports described the 6th data-signal.

16. processing unit according to claim 11, is characterized in that, described the first pre-set interval is (T/2, T), described the second pre-set interval be (0, T/2).

17. according to claim 11 to the processing unit described in any one in 15, it is characterized in that, the system clock that described the first clock signal is Memory Controller Hub, described second clock signal is described Memory Controller Hub writes data clock, the data to be transmitted that described the first data-signal is described Memory Controller Hub, described the second data-signal is that described Memory Controller Hub is to the data of writing of memory chip transmission, wherein, write data clock is identical with the clock cycle of the internal memory clock of described memory chip, and between write data clock and described internal memory clock, meet default sequential requirement.

18. processing unit according to claim 17, it is characterized in that, described default sequential requires the write data for generating according to write data clock with respect to described internal memory clock, to shift to an earlier date K clock cycle when arriving described memory chip, K is the arbitrary value between 0 to 1, wherein, described obtain the first data-signal and second clock signal before, described processing unit also comprises:

Adjustment unit, for before meeting and requiring corresponding termination executive condition with described default sequential, repeat M following operation: adjust forward or backward write data clock or with respect to the 3rd clock signal of K clock cycle of write data clock hysteresis, and to described memory chip transmission seven data-signal corresponding with write data clock after adjustment or described the 3rd clock signal after adjustment; Receive the 8th data-signal that described memory chip returns according to described the 7th data-signal, and judge whether to meet described termination executive condition according to described the 8th data-signal receiving; Wherein, M is more than or equal to 1.

19. processing unit according to claim 18, it is characterized in that, the pulse signal of described the 7th data-signal for aliging with rising edge or the trailing edge of described the 3rd clock signal, described the 8th data-signal is that described memory chip is used the resulting data-signal of internal memory clock described in described pulse signal acquisition, wherein

20. processing unit according to claim 18, is characterized in that,

Described processing unit also comprises: initialization unit, for using the clock signal of aliging with described system clock as write data clock or the initial value of described the 3rd clock signal;

Described adjustment unit comprises: Postponement module, and for postponing write data clock or described a 3rd clock signal 1/L clock cycle, as write data clock or described the 3rd clock signal after adjusting, L is positive integer;

Described processing unit also comprises: computing module, for when using the clock signal of aliging with described system clock as write data clock, obtains described phase difference according to following formula: the * T of Δ=(M/L); When using the clock signal of aliging with described system clock as described the 3rd clock signal, according to following formula, obtain described phase difference: the * T of Δ=(M/L-K); Wherein, Δ represents described phase difference, and T represents the described clock cycle.