CN104821802A - Clock operation method and circuit - Google Patents
Clock operation method and circuit Download PDFInfo
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- CN104821802A CN104821802A CN201510058368.8A CN201510058368A CN104821802A CN 104821802 A CN104821802 A CN 104821802A CN 201510058368 A CN201510058368 A CN 201510058368A CN 104821802 A CN104821802 A CN 104821802A
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- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000003111 delayed effect Effects 0.000 claims abstract description 91
- 230000001360 synchronised effect Effects 0.000 claims description 70
- 239000004065 semiconductor Substances 0.000 claims description 20
- 230000005540 biological transmission Effects 0.000 claims description 17
- 238000004364 calculation method Methods 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 description 20
- 230000008929 regeneration Effects 0.000 description 14
- 238000011069 regeneration method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229940075591 dalay Drugs 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
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- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention provides a clock operation method and circuit. In the clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules.
Description
Technical field
The present invention relates to a kind of in lift-launch functional module and carry out communicating in the semiconductor chip of the control circuit controlling its work with functional module, generate the clock generation method to the clock of control circuit and functional module supply and clock forming circuit.
Background technology
Along with the miniaturization of the manufacturing process of semiconductor integrated circuit, semiconductor chip maximizes and multifunction gradually.Such as, in the method for designing of semiconductor integrated circuit being referred to as SOC (system on a chip) (SOC:System on chip), sometimes on a semiconductor die except carry realize more than 1 of predetermined function respectively functional module except, be also equipped with the control circuits such as the CPU (central processing unit) that carrying out with each functional module communicates controls its work.Further, the power consumption when frequency by lowering work clock when the inoperative of circuit suppresses standby.
If semiconductor chip maximizes, then the physical routing being transmitted in the work clock of each functional module from clock generating circuit, apart from elongated, even reaches several millimeters sometimes.Therefore, even if when control circuit is connected to identical work clock with each functional module, sometimes also to postpone respectively according to transmission range the supply of each functional module and its phase place from the work clock of phase deviation of work clock being supplied in control circuit, thus cannot correct communication be carried out between control circuit and each functional module.
In order to tackle this problem, following content is recorded: master clock signal is carried out frequency division and exports as the 1st sub-frequency clock signal in patent documentation 1 (Japanese Patent Publication 2005-38159 publication), and utilize master clock signal to carry out simultaneously match to export the 2nd sub-frequency clock signal to the 1st sub-frequency clock signal, reduce the clock skew of the 2nd sub-frequency clock signal with this, and supply the 2nd sub-frequency clock signal with the 1st sub-frequency clock signal same phase to the multiple logical circuits in semiconductor chip.
And, following content is recorded: generate the 2nd clock signal by the 1st clock signal is carried out frequency division in patent documentation 2 (Japanese Patent Publication 2007-189293 publication), and the cycle with the 2nd clock signal is generated by the 1st and the 2nd clock signal, and the 3rd clock signal that the change time point of logic level is identical with the time point of the 1st clock signal, suppress the skew caused by the chip internal deviation on the transmission path of the 1st clock signal and the 3rd clock signal thus, and improve timing closure.
In patent documentation 1,2, make frequency-dividing clock and its source clock synchronous and it kept again generate regeneration time clock, and be allocated in each functional module, the impact of variability on chip (OCV, on chipvariation: the deviation of the characteristic in same semiconductor chip) can be suppressed thus.But, when the frequency dividing ratio of frequency-dividing clock is variable, in patent documentation 1,2, the progression for the FF (trigger) generating regeneration time clock is fixed, and is therefore supplied in the phase deviation of the frequency-dividing clock of control circuit and each functional module and cannot carries out correct communication.
Fig. 7 is the circuit diagram of an example of the structure of the clock forming circuit represented in the past.Clock forming circuit 56 shown in this figure is in lift-launch functional module (A, B) 14,16 and carry out communicating in the semiconductor chip of the control circuit 12 controlling its work with each functional module 14,16, generate the delayed clock being supplied in control circuit 12 and functional module 14,16 respectively, and possess frequency dividing circuit 58 and clock synchronization circuit 60,62.
Source clock is carried out the frequency-dividing clock that m frequency division (m is the integer of more than 2) generates the 1/m frequency of the frequency with source clock by frequency dividing circuit 58.
Clock synchronization circuit 60 and source clock synchronous and generate the delayed clock A making frequency-dividing clock postpone 4 clocks, and generated delayed clock A is supplied in and that work functional module 14 synchronous with delayed clock A.
Clock synchronization circuit 62 and source clock synchronous and generate the delayed clock B making frequency-dividing clock postpone 2 clocks, and the generated clock B that delays is supplied in and that work functional module 16 synchronous with delayed clock B.
When there is no clock synchronization circuit 60,62, each functional module 14,16 will be supplied according to the variable division clock that transmission range postpones respectively.
4 clocks frequency-dividing clock being postponed by clock synchronization circuit 60,62 and the clock number of 2 clocks are, in order to make control circuit 12 and each functional module 14,16 synchronous with frequency-dividing clock and work, when there is no clock synchronization circuit 60,62, according to the transmission range of each frequency-dividing clock being transmitted in each functional module 14,16 from frequency dividing circuit 58, each variable division clock calculation being transmitted in each functional module 14,16 is gone out, need and source clock synchronous and make the clock number of variable division clock delay.
Clock synchronization circuit 60 possesses the FF (delay circuit) 64,66,68,70 of 4 grades that are connected in series accordingly with 4 clocks postponed.FF64,66,68, the clock input terminal of 70 inputs active clock, has frequency-dividing clock in the DATA IN terminal input of elementary FF64.From FF64,66,68, the data output terminal of 70 exports regeneration time clock 1 ~ 3 and delayed clock A respectively.
The rising synchronous of frequency-dividing clock and source clock and respectively postpone 1 clock by the FF64,66,68,70 of 4 grades.Its result, the delayed clock A of 4 clocks of source clock from clock synchronization circuit 60 output frequency division clock delay.
Similarly, clock synchronization circuit 62 and 2 clocks delayed possess the FF72,74 of 2 grades that are connected in series accordingly.FF72,74 clock input terminal input active clock, elementary FF72 DATA IN terminal input have frequency-dividing clock.From FF72,74 data output terminal export regeneration time clock 1 and delayed clock B respectively.
The rising synchronous of frequency-dividing clock and source clock and respectively postpone 1 clock by the FF72,74 of 2 grades.Its result, the delayed clock B of 2 clocks of source clock from clock synchronization circuit 62 output frequency division clock delay.
In clock forming circuit 56, by frequency dividing circuit 58, generate source clock by the frequency-dividing clock of m frequency division.
Then, by clock synchronization circuit 60, generate the delayed clock A that frequency-dividing clock postpones 4 clocks with the rising synchronous of source clock, and be supplied in functional module 14.Further, by clock synchronization circuit 62, generate the delayed clock B that frequency-dividing clock postpones 2 clocks with the rising synchronous of source clock, and be supplied in functional module 16.
Fig. 8 represents the sequential chart of frequency-dividing clock for an example of the work of the clock forming circuit shown in Fig. 7 during 2 frequency-dividing clock.
When frequency-dividing clock is 2 frequency-dividing clock, as illustrated in the timing diagram, the rising synchronous of frequency-dividing clock and source clock, the alternately change of high level and low level.Regeneration time clock 1 ~ 3 is similarly with the rising synchronous of source clock and level changes, respectively from 1 ~ 3 clock of frequency-dividing clock source of delay clock.The rising synchronous of delayed clock A, B and source clock and level changes, respectively from 4 clocks and 2 clocks of frequency-dividing clock source of delay clock.
Thus delayed clock A, B and frequency-dividing clock are synchronous and its phase place is also consistent, and control circuit 12 can correctly carry out communication to control its work with each functional module 14,16.
Fig. 9 represents the sequential chart of frequency-dividing clock for an example of the work of the clock forming circuit shown in Fig. 7 during 5 frequency-dividing clock.
When frequency-dividing clock is 5 frequency-dividing clock, as illustrated in the timing diagram, the rising synchronous of frequency-dividing clock and source clock, the alternately change of high level and low level.The high level of frequency-dividing clock is set to the pulse duration of 2 clocks of source clock, low level is set to the pulse duration of 3 clocks of source clock.Regeneration time clock 1 ~ 3 is similarly with the rising synchronous of source clock and level changes, respectively from 1 ~ 3 clock of frequency-dividing clock source of delay clock.The rising synchronous of delayed clock A, B and source clock and level changes, respectively from 4 clocks and 2 clocks of frequency-dividing clock source of delay clock.
Thus delayed clock A, B and frequency-dividing clock carry out synchronously, but its phase deviation, therefore control circuit 12 correctly cannot communicate with each functional module 14,16.
Clock synchronization circuit 60,62 structure of clock forming circuit 56 corresponds to the situation that frequency-dividing clock is fixed as 2 frequency-dividing clocks.Therefore, in the structure of clock forming circuit 56, if frequency-dividing clock becomes the frequency-dividing clock of other frequency dividing ratios from 2 frequency-dividing clocks, then the phase deviation of delayed clock A, B and frequency-dividing clock.Thus there is control circuit 12 correctly cannot communicate with each functional module 14,16, and the problem of its work uncontrollable.
Summary of the invention
The object of the invention is to the problem solving aforementioned prior art, even if when providing a kind of frequency dividing ratio at frequency-dividing clock to change, control circuit also correctly can carry out communicating controlling the clock forming circuit of its work with functional module.
To achieve these goals, the invention provides a kind of clock generation method, lift-launch more than 1 functional module and control described more than 1 functional module work control circuit semiconductor chip in, generate the delayed clock that each functional module to described control circuit and described more than 1 supplies, it is characterized in that, described clock generation method comprises:
According to frequency dividing ratio setting signal, generate the step of variable division clock source clock being carried out frequency division;
In order to make each functional module and the work of described variable division clock synchronous of described control circuit and described more than 1, when not making the clock synchronization circuit of described variable division clock delay, according to from generating the variable division circuit transmission of described variable division clock in the transmission range of described each variable division clock of the functional module of described more than 1, make the step of the clock number of described variable division clock delay to being transmitted in each variable division clock calculation of functional module of described more than 1 and described source clock synchronous;
Obtain the step as the maximum clock number of maximum clock number in the described clock number calculated;
Generate with described source clock synchronous the 1st delayed clock making maximum clock number described in described variable division clock delay, and described 1st delayed clock is supplied in step that is synchronous with described 1st delayed clock and the described control circuit worked;
Generate with described source clock synchronous the 2nd delayed clock making described variable division clock postpone more than 1 of described maximum clock number respectively, and each 2nd delayed clock of described more than 1 is supplied in step that is synchronous with each 2nd delayed clock of described more than 1 and each functional module of described more than 1 worked.
And, the invention provides a kind of clock forming circuit, lift-launch more than 1 functional module and control described more than 1 functional module work control circuit semiconductor chip in, generate the delayed clock that each functional module to described control circuit and described more than 1 supplies, it is characterized in that, described clock forming circuit comprises:
Variable division circuit, according to frequency dividing ratio setting signal, generates variable division clock source clock being carried out frequency division;
1st clock synchronization circuit, generate the 1st delayed clock of the maximum clock number that described variable division clock delay is preset with described source clock synchronous, and described 1st delayed clock is supplied in and that work described control circuit synchronous with described 1st delayed clock; And
2nd clock synchronization circuit of more than 1, the 2nd delayed clock making described variable division clock postpone more than 1 of described maximum clock number is respectively generated with described source clock synchronous, and each 2nd delayed clock of described more than 1 is supplied in and that the work each functional module of described more than 1 synchronous with the 2nd delayed clock of described more than 1
Described maximum clock number is, in order to make each functional module of described control circuit and described more than 1 and described variable division clock synchronous and work, when there is no the 2nd clock synchronization circuit of described 1st clock synchronization circuit and described more than 1, according to from described variable division circuit transmission in the transmission range of each described variable division clock of the functional module of described more than 1, the variable division clock calculation of the functional module being transmitted in described more than 1 is gone out, clock number maximum in the clock number of described variable division clock delay is made with described source clock synchronous.
In clock forming circuit of the present invention, generate the delayed clock of the clock number of the source clock that variable division clock delay is preset.Therefore, with the frequency dividing ratio of variable division clock independently, delayed clock is all the time by synchronously, and its phase place is consistent.Thus even if when the frequency dividing ratio of variable division clock changes, delayed clock also carries out synchronous all the time and its phase place is consistent, and therefore control circuit correctly can carry out communicating and controlling its work with each functional module all the time.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the 1st execution mode of the structure representing clock forming circuit of the present invention.
Fig. 2 is the flow chart of example when asking for maximum clock number.
Fig. 3 is the flow chart of an example of the work representing the clock forming circuit shown in Fig. 1.
Fig. 4 represents the sequential chart of variable division clock for an example of the work of the clock forming circuit shown in Fig. 1 during 2 frequency-dividing clock.
Fig. 5 represents the sequential chart of variable division clock for an example of the work of the clock forming circuit shown in Fig. 1 during 5 frequency-dividing clock.
Fig. 6 is the circuit diagram of the 2nd execution mode of the structure representing clock forming circuit of the present invention.
Fig. 7 is the circuit diagram of an example of the structure representing existing clock forming circuit.
Fig. 8 represents the sequential chart of frequency-dividing clock for an example of the work of the clock forming circuit shown in Fig. 7 during 2 frequency-dividing clock.
Fig. 9 represents the sequential chart of frequency-dividing clock for an example of the work of the clock forming circuit shown in Fig. 7 during 5 frequency-dividing clock.
Primary symbols explanation
10,34,56: clock forming circuit
12: control circuit
14,16: functional module
18: variable division circuit
20,22,24,36,38,60,62: clock synchronization circuit
26,28,30,32,40,42,44,46,48,52,54,64,66,68,70,72,74:FF (delay circuit)
50: multiplexer
58: frequency dividing circuit
Embodiment
Below, the suitable execution mode with reference to the accompanying drawings, is described in detail to clock forming circuit of the present invention.
Fig. 1 is the circuit diagram of the 1st execution mode of the structure representing clock forming circuit of the present invention.Clock forming circuit 10 shown in this figure is in lift-launch functional module (A, B) 14,16 and carry out communicating in the semiconductor chip of the control circuit 12 controlling its work with each functional module 14,16, generate the delayed clock being supplied in control circuit 12 and each functional module 14,16 respectively, and possess variable division circuit 18 and clock synchronization circuit 20,22,24.
Variable division circuit 18 according to frequency dividing ratio setting signal source clock carried out Fractional-N frequency (N be according to frequency dividing ratio setting signal determine more than 2 integer) generate the variable division clock of the 1/N frequency of the frequency with the frequency dividing ratio corresponding with frequency dividing ratio setting signal and source clock.
Frequency dividing ratio setting signal and source clock are such as from the outside of semiconductor chip or other functional modules input being equipped on semiconductor chip.
Then, clock synchronization circuit 20 and source clock synchronous and generate the delayed clock C of the maximum clock number that variable division clock delay is preset, and generated delayed clock C is supplied in and that work control circuit 12 synchronous with delayed clock C.
When there is no clock synchronization circuit 22,24, each functional module 14,16 is supplied to the variable division clock postponed respectively according to transmission range.
Maximum clock number is, in order to make control circuit 12 and each functional module 14,16 and the work of variable division clock synchronous, when there is no clock synchronization circuit 22,24, according to the transmission range of each variable division clock being transmitted in each functional module 14,16 from variable division circuit 18, that each variable division clock calculation being transmitted in each functional module 14,16 is gone out and source clock synchronous and make in the clock number of variable division clock delay, clock number more than maximum clock number.
In addition, by maximum clock number being set to the maximum clock number in the clock number making each variable division clock delay being transmitted in each functional module 14,16, the circuit scale of clock synchronization circuit 20,22,24 can be set to necessary Min..
Clock synchronization circuit 20 is the circuit when maximum clock number is 4 clocks, correspondingly, possesses the FF (delay circuit) 26,28,30,32 of 4 grades that are connected in series.FF26,28,30, the clock input terminal of 32 inputs active clock, has variable division clock in the DATA IN terminal input of elementary FF26.From FF26,28,30, the data output terminal of 32 exports regeneration time clock 1 ~ 3 and delayed clock C respectively.
The rising synchronous of variable division clock and source clock and respectively postpone 1 clock by the FF26,28,30,32 of 4 grades.Its result, exports the delayed clock C of 4 clocks of variable division clock delay source clock from clock synchronization circuit 20.
Similarly, clock synchronization circuit 22 and source clock synchronous and generate the delayed clock A making variable division clock delay maximum clock number, and generated delayed clock A is supplied in and that work functional module 14 synchronous with delayed clock A.
Clock synchronization circuit 24 and source clock synchronous and generate the delayed clock B making variable division clock delay maximum clock number, and generated delayed clock B is supplied in and that work functional module 16 synchronous with delayed clock B.
The structure of clock synchronization circuit 22,24 is identical with clock synchronization circuit 20, in the FF26 of 4 grades, 28,30,32, the FF26,28 of 2 of first half grades is arranged at the outside of functional module 14,16, the FF30,32 of 2 of latter half grades is arranged at the inside of functional module 14,16.Further, delayed clock A, B is supplied in internal circuit that is synchronous with delayed clock A, B and the functional module 14,16 worked respectively.So, each delay circuit forming clock synchronization circuit 22,24 not only can be arranged at the outside of each functional module 14,16, can also be arranged at its inside.
Then, with reference to the flow chart shown in figure 2 and Fig. 3, the work obtaining the clock forming circuit 10 shown in the method for maximum clock number and Fig. 1 is described.
When asking for maximum clock number, first, generated the variable division clock (the step S1 of Fig. 2) of source clock division according to frequency dividing ratio setting signal by variable division circuit 18.
As previously mentioned, when not having each clock synchronization circuit 22,24, the variable division clock according to each self-dalay of transmission range is supplied in each functional module 14,16 from variable division circuit 18.
Then, in order to make control circuit 12 and each functional module 14,16 respectively with the work of variable division clock synchronous, according to the transmission range of each variable division clock being transmitted in each functional module 14,16, to being transmitted in each variable division clock calculation of each functional module 14,16 and source clock synchronous and making the clock number (the step S2 of Fig. 2) of variable division clock delay.
Further, clock number and the maximum clock number (the step S3 of Fig. 2) of more than the maximum clock number in the clock number calculated is obtained.
Existing clock forming circuit 56 as shown in Figure 7, make the clock number of the variable division clock delay being transmitted in each functional module 14,16 be 4 clocks and 2 clocks time, such as maximum clock number is set to 4 clocks.Now, as shown in Figure 1, the progression forming the FF of each clock synchronization circuit 20,22,24 is 4 grades.
In clock forming circuit 10, by variable division circuit 18, source clock by frequency division, and generates the frequency dividing ratio variable division clock corresponding with frequency dividing ratio setting signal (the step S4 of Fig. 3) according to frequency dividing ratio setting signal.
Then, by clock synchronization circuit 20, generate the delayed clock C of 4 clocks of variable division clock delay source clock with the rising synchronous of source clock, and be supplied in control circuit 12 (the step S5 of Fig. 3).
Similarly, by clock synchronization circuit 22, generate the delayed clock A of variable division clock delay 4 clocks with the rising synchronous of source clock, and be supplied in functional module 14.Further, by clock synchronization circuit 24, generate the delayed clock B of variable division clock delay 4 clocks with the rising synchronous of source clock, and be supplied in functional module 16 (the step S6 of Fig. 3).
Fig. 4 represents the sequential chart of variable division clock for an example of the work of the clock forming circuit shown in Fig. 1 during 2 frequency-dividing clock.
When variable division clock is 2 frequency-dividing clock, as illustrated in the timing diagram, variable division clock and regeneration time clock 1 ~ 3 carry out work in the same manner as the frequency-dividing clock shown in Fig. 8 and regeneration time clock 1 ~ 3.Further, delayed clock A, B, C and source clock rising synchronous and level changes, respectively from 4 clocks of frequency-dividing clock source of delay clock.
Thus delayed clock A, B, C carry out synchronous and its phase place is also consistent, and therefore control circuit 12 can correctly carry out communication to control its work with each functional module 14,16.
Fig. 5 represents the sequential chart of variable division clock for an example of the work of the clock forming circuit shown in Fig. 1 during 5 frequency-dividing clock.
When variable division clock is 5 frequency-dividing clock, as illustrated in the timing diagram, variable division clock and regeneration time clock 1 ~ 3 carry out work in the same manner as the frequency-dividing clock shown in Fig. 9 and regeneration time clock 1 ~ 3.Further, delayed clock A, B, C and source clock rising synchronous and level changes, respectively from 4 clocks of frequency-dividing clock source of delay clock.
Thus delayed clock A, B, C carry out synchronous and its phase place is also consistent, and therefore control circuit 12 can correctly carry out communication to control its work with each functional module 14,16.
In clock forming circuit 10, generate delayed clock A, B, C of making 4 clocks of variable division clock delay source clock.Therefore, with the frequency dividing ratio of variable division clock independently, delayed clock A, B, C are all the time by synchronously, and its phase place is consistent.Thus even if the frequency dividing ratio of variable division clock changes, delayed clock A, B, C also carry out synchronously all the time, and phase place is consistent, and therefore control circuit 12 can correctly carry out communication to control its work with each functional module 14,16 all the time.
In addition, delayed clock A, B, C shown in Fig. 4 and Fig. 5 are from the upward drift scheduled time of source clock.This scheduled time represents, from delayed clock A, B, C time postponed because of transmission range to being supplied in the internal circuit of the functional module 14,16 corresponding respectively with it and control circuit 12 that the FF32 of the least significant end level of the clock synchronization circuit 20,22,24 shown in Fig. 1 exports.
Then, Fig. 6 is the circuit diagram of the 2nd execution mode of the structure representing clock forming circuit of the present invention.Clock forming circuit 34 shown in this figure possesses variable division circuit 18 and clock synchronization circuit 36,38.
Variable division circuit 18 is same as shown in Figure 1.
Clock synchronization circuit 36,38 has generated variable division clock delay delayed clock A, B of the clock number set by frequency dividing ratio setting signal respectively with source clock synchronous, and generated delayed clock A, B is supplied in respectively internal circuit that is synchronous with delayed clock A, B and the functional module 14,16 worked.
Clock synchronization circuit 36 possess 5 grades that are connected in series FF40,42,44,46,48, multiplexer 50 and the FF52,54 of 2 grades that is connected in series.FF40,42,44,46,48,52, the clock input terminal of 54 inputs active clock, has variable division clock in the DATA IN terminal input of elementary FF40.Regeneration time clock 1 ~ 4 respectively from FF42,44,46, the data output terminal of 48 exports, and is input into multiplexer 50.The output signal of multiplexer 50 is had, from the data output terminal output delay clock A of the FF54 of least significant end level in the DATA IN terminal input of FF52.
The rising synchronous of variable division clock and source clock and respectively postpone 1 clock by the FF40,42,44,46,48 of 5 grades.To export 1 regeneration time clock regeneration time clock 1 ~ 4 from multiplexer 50 according to not shown frequency dividing ratio setting signal.The output signal of multiplexer 50 further with the rising synchronous of source clock and respectively postpone 1 clock by the FF52,54 of 2 grades.Its result, exports the delayed clock A of the clock number that variable division clock delay is set by frequency dividing ratio setting signal from clock synchronization circuit 36.
For clock synchronization circuit 38, the FF52,54 of 2 grades that are connected in series in clock synchronization circuit 36 only becomes the FF54 of 1 grade, in addition, identical with the structure of clock synchronization circuit 36, and carries out work in the same manner as clock synchronization circuit 36.
Similarly, each delay circuit of formation clock synchronization circuit 36,38 and multiplexer not only can be arranged at the outside of each functional module 14,16, also can be arranged at its inside.
Then, the work of the clock forming circuit 34 shown in Fig. 6 is described.
In clock forming circuit 34, by variable division clock 18, source clock by frequency division, generates the variable division clock that frequency dividing ratio is corresponding with frequency dividing ratio setting signal according to frequency dividing ratio setting signal.
Then, by clock synchronization circuit 36, generate the delayed clock A of the clock number that variable division clock delay is set by frequency dividing ratio setting signal with the rising synchronous of source clock, and be supplied in functional module 14.Further, by clock synchronization circuit 38, generate the delayed clock B of the clock number that variable division clock delay is set by frequency dividing ratio setting signal with the rising synchronous of source clock, and be supplied in functional module 16.
In clock forming circuit 34, generate delayed clock A, B of being delayed the clock number set by frequency dividing ratio setting signal.Therefore, it is possible to obtain the effect identical with the situation of clock forming circuit 10.
In addition, in clock forming circuit 34, along with being increased by the frequency dividing ratio of the variable division clock of variable division circuit 18 frequency division, the size forming the sum of series multiplexer of the FF of clock synchronization circuit 36,38 becomes large, therefore tediously long circuit and increases.Thus although clock forming circuit 10,34 can realize identical function, the circuit structure of clock forming circuit 10 is simple compared with clock forming circuit 34, has this advantage of circuit scale that can reduce and realize needed for identical function.
In addition, the concrete circuit structure of variable division circuit, clock synchronization circuit, delay circuit, without any restriction, can adopt the circuit of the various structures that can realize identical function.Further, the quantity of functional module is not defined as 2 yet, can be more than 1 any.
Content of the present invention substantially as above.
Above, to invention has been detailed description, but the present invention is not limited to above-mentioned execution mode, certainly, can carry out various improvement and change without departing from the spirit and scope of the present invention.
Claims (9)
1. a clock generation method, lift-launch more than 1 functional module and control described more than 1 functional module work control circuit semiconductor chip in, generate the delayed clock supplied to each in the functional module of described control circuit and described more than 1, it is characterized in that, described clock generation method comprises:
According to frequency dividing ratio setting signal, generate the step of variable division clock source clock being carried out frequency division;
In order to make each and described variable division clock synchronous in the functional module of described control circuit and described more than 1 and work, when not making the clock synchronization circuit of described variable division clock delay, according to from generating the variable division circuit transmission of described variable division clock in the transmission range of each described variable division clock of the functional module of described more than 1, make the step of the clock number of described variable division clock delay to being transmitted in each variable division clock calculation of functional module of described more than 1 and described source clock synchronous;
Obtain the step as the maximum clock number of clock number more than maximum clock number in the described clock number calculated;
Generate with described source clock synchronous the 1st delayed clock making maximum clock number described in described variable division clock delay, and described 1st delayed clock is supplied in step that is synchronous with described 1st delayed clock and the described control circuit worked;
Generate with described source clock synchronous the 2nd delayed clock making described variable division clock postpone more than 1 of described maximum clock number respectively, and each in the 2nd delayed clock of described more than 1 is supplied in synchronous with each in the 2nd delayed clock of described more than 1 and in the functional module of described more than 1 worked the step of each.
2. clock generation method according to claim 1, is characterized in that,
Described frequency dividing ratio setting signal inputs from the outside of described semiconductor chip.
3. clock generation method according to claim 1, is characterized in that,
Described frequency dividing ratio setting signal is from other functional modules input being equipped on described semiconductor chip.
4. a clock forming circuit, lift-launch more than 1 functional module and control described more than 1 functional module work control circuit semiconductor chip in, generate the delayed clock supplied to each in the functional module of described control circuit and described more than 1, it is characterized in that, described clock forming circuit comprises:
Variable division circuit, according to frequency dividing ratio setting signal, generates variable division clock source clock being carried out frequency division;
1st clock synchronization circuit, generate the 1st delayed clock of the maximum clock number that described variable division clock delay is preset with described source clock synchronous, and described 1st delayed clock is supplied in and that work described control circuit synchronous with described 1st delayed clock;
2nd clock synchronization circuit of more than 1, the 2nd delayed clock making described variable division clock postpone more than 1 of described maximum clock number is respectively generated with described source clock synchronous, and each in the 2nd delayed clock of described more than 1 is supplied in and each in the functional module of described more than 1 that work synchronous with each in the 2nd delayed clock of described more than 1
Described maximum clock number is, in order to make each and described variable division clock synchronous in the functional module of described control circuit and described more than 1 and work, when there is no the 2nd clock synchronization circuit of described 1st clock synchronization circuit and described more than 1, according to from described variable division circuit transmission in the transmission range of each described variable division clock of the functional module of described more than 1, each variable division clock calculation of the functional module being transmitted in described more than 1 is gone out, the clock number of more than clock number maximum in the clock number of described variable division clock delay is made with described source clock synchronous.
5. clock forming circuit according to claim 4, is characterized in that,
Described frequency dividing ratio setting signal inputs from the outside of described semiconductor chip.
6. clock forming circuit according to claim 4, is characterized in that,
Described frequency dividing ratio setting signal is from other functional modules input being equipped on described semiconductor chip.
7. the clock forming circuit according to any one in claim 4 to 6, is characterized in that,
Described 1st clock synchronization circuit possesses the delay circuit of that be connected in series, corresponding with described maximum clock number progression, and by with described source clock synchronous and make described variable division clock respectively postpone 1 clock, thus generate described 1st delayed clock making maximum clock number described in described variable division clock delay.
8. the clock forming circuit according to any one in claim 4 to 6, is characterized in that,
2nd clock synchronization circuit of described more than 1 possesses the delay circuit of that be connected in series, corresponding with described maximum clock number progression respectively, and by with described source clock synchronous and make described variable division clock respectively postpone 1 clock, thus generate described 2nd delayed clock making maximum clock number described in described variable division clock delay.
9. clock forming circuit according to claim 8, is characterized in that,
In the delay circuit of the progression corresponding with described maximum clock number, at least 1 delay circuit is arranged at the outside of described functional module, and remaining delay circuit is arranged at the inside of described functional module.
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| JP2014020557A JP6242228B2 (en) | 2014-02-05 | 2014-02-05 | Clock generation method and clock generation circuit |
| JP2014-020557 | 2014-02-05 |
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| CN104821802A true CN104821802A (en) | 2015-08-05 |
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| JP6242228B2 (en) | 2017-12-06 |
| US20150222283A1 (en) | 2015-08-06 |
| US9553595B2 (en) | 2017-01-24 |
| CN104821802B (en) | 2018-11-27 |
| JP2015148889A (en) | 2015-08-20 |
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