CN112671403A - Clock frequency division system, method and equipment - Google Patents
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Abstract
The embodiment of the invention discloses a clock frequency division system, a clock frequency division method and clock frequency division equipment. Wherein, clock frequency division system includes: the system comprises an absolute global clock generation module, a prescaler module and at least one subsystem, wherein each subsystem comprises a clock frequency division module; the absolute global clock generating module is used for generating an absolute global clock and sending the absolute global clock to the presorting module; the presorting module is used for generating relative global clocks respectively corresponding to the subsystems according to the absolute global clock and transmitting the relative global clocks to the clock frequency dividing module in the matched subsystem; the clock frequency division module is used for generating at least one synchronous clock according to the relative global clock acquired from the pre-frequency division module; wherein the synchronous clock is used for providing to the electronic module at the current stage or the next stage of the subsystem. According to the technical scheme of the embodiment of the invention, a multi-level clock frequency division module is adopted to carry out layering and standardization processing on a complex SOC clock network structure.
Description
Technical Field
The embodiments of the present invention relate to electronic circuit design and communication technologies, and in particular, to a clock frequency division system, method, and device.
Background
The operating frequencies of the subsystems or modules included in the SOC (System On Chip) may be different from each other, and thus a clock circuit is required to perform frequency division. The SOC clock network generally obtains a fundamental frequency from the outside, then multiplies the fundamental frequency by a PLL (Phase Lock Loop) to a fundamental frequency and a system maximum frequency required by each subsystem, and finally performs frequency division by a frequency division circuit inside the subsystem to obtain other required frequency points.
With the continuous development of integrated circuits, the number of clocks related to an SOC clock network may be hundreds of thousands, and the distribution of frequency points also ranges from several MHz to several GHz.
Disclosure of Invention
The embodiment of the invention provides a clock frequency division system, a method and equipment, which adopt a multi-level clock frequency division module to carry out layering and standardization processing on a complex SOC clock network structure.
In a first aspect, an embodiment of the present invention provides a clock division system, where the system includes: the system comprises an absolute global clock generation module, a prescaler module and at least one subsystem, wherein each subsystem comprises a clock frequency division module; the absolute global clock generation module is connected with the prescaler module, and the prescaler module is respectively connected with the clock frequency division module in each subsystem;
the absolute global clock generating module is used for generating an absolute global clock and sending the absolute global clock to the presorting module;
the pre-frequency division module is used for generating relative global clocks corresponding to the subsystems respectively according to the absolute global clock and sending the relative global clocks to the clock frequency division module in the matched subsystem;
the clock frequency division module is used for generating at least one synchronous clock according to the relative global clock acquired from the pre-frequency division module;
wherein the synchronous clock is used for providing to the electronic module at the current stage or the next stage of the subsystem.
In a second aspect, an embodiment of the present invention further provides a clock dividing method, where the method includes:
the absolute global clock generation module generates an absolute global clock according to an external reference clock and sends the absolute global clock to the pre-frequency division module;
the pre-frequency division module generates relative global clocks corresponding to the subsystems respectively according to the absolute global clock and sends the relative global clocks to the clock frequency division module in the matched subsystem;
the clock frequency division module generates at least one synchronous clock according to the relative global clock acquired from the pre-frequency division module;
wherein the synchronous clock is used for providing to the electronic module at the current stage or the next stage of the subsystem.
In a third aspect, an embodiment of the present invention further provides an electronic device, including:
any embodiment of the invention provides a clock division system.
The technical proposal of the embodiment of the invention is that an absolute global clock generating module generates an absolute global clock according to an external reference clock and sends the absolute global clock to a pre-frequency dividing module, the pre-frequency dividing module generates relative global clocks respectively corresponding to each subsystem according to the absolute global clock, and each relative global clock is sent to a clock frequency division module in the matched subsystem, and finally the clock frequency division module generates at least one synchronous clock according to the relative global clock obtained from the presorting module, the system is used for providing the electronic module of the current stage or the next stage to a subsystem, solves the problems that the use of a dispersed frequency division circuit module or a single clock frequency division circuit module in the prior art easily causes disordered clock relation and complex clock constraint, and influences the comprehensive quality of a clock tree, and adopts a multi-level clock special module to carry out layering and normalized processing on a complex SOC clock network structure.
Drawings
Fig. 1a is a schematic structural diagram of a clock division system according to a first embodiment of the present invention;
FIG. 1b is a schematic diagram of a clock structure of a distributed frequency-dividing circuit module according to an embodiment of the present invention;
FIG. 1c is a schematic diagram of a clock structure of a single clock divider circuit module according to an embodiment of the present invention;
FIG. 1d is a schematic diagram of a hierarchical clock structure according to a first embodiment of the present invention;
FIG. 2 is a flow chart of a clock division method according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1a is a schematic structural diagram of a clock frequency division system in an embodiment of the present invention, and the technical solution of this embodiment is suitable for a situation where a complex SOC clock network is divided into functional modules.
The clock is a heartbeat and a pulse for a digital system, and the event triggers of the timing circuit are mostly concentrated on the clock edge. The design of the clock network realizes all the processes running through the chip design, and it is very critical to ensure the correct and efficient operation of the SOC clock network. For ease of understanding, the clock structure for the SOC in the prior art will be described first, and the clock structure commonly used in the prior art includes using discrete frequency-dividing circuit blocks and using a single clock-dividing circuit block.
The clock structure using the dispersed frequency division circuit modules is as shown in fig. 1b, the phase-locked loop directly sends the output clock to each clock module, and each clock module generates the functional clock required by the system.
The clock structure using a single clock frequency division circuit module is shown in fig. 1c, and a high-frequency clock generated by a phase-locked loop generates a functional clock required by a system through a clock frequency division circuit, and this mode has the same limitation as the clock structure of the dispersed frequency division circuit module when a complex system or too many submodules are encountered, and increases difficulty in subsequent related processes such as clock constraint, clock test, clock tree synthesis and the like due to lack of uniform synchronization relation definition of each functional clock.
A clock division system according to an embodiment of the present invention is described with reference to fig. 1 a:
the clock frequency division system comprises an absolute global clock generation module 1, a prescaler module 2 and at least one subsystem 3, wherein each subsystem 3 comprises a clock frequency division module 31; the absolute global clock generation module 1 is connected with the prescaler module 2, and the prescaler module 2 is respectively connected with the clock frequency dividing module 31 in each subsystem 3.
In the present embodiment, the clock frequency dividing system includes an absolute global clock generating module 1, a pre-frequency dividing module 2(pre _ clk _ div), and at least one subsystem 3 (for example, clk _ ssysA, clk _ ssysB, and clk _ ssysC shown in fig. 1 a), and each subsystem 3 includes a clock frequency dividing module 31. The specific connection relationship includes that the absolute global clock generation module 1 is connected with the prescaler module 2, and the prescaler module 2 is connected with the clock frequency dividing module 31 included in each subsystem 3. The absolute global clock generation module 1 can uniformly integrate an externally input reference clock signal to generate a high-frequency clock, so that a high-frequency device can normally work.
And the absolute global clock generating module 1 is used for generating an absolute global clock and sending the absolute global clock to the prescaler module 2.
In this embodiment, an external reference clock is input to an absolute global clock generation module 1 inside the system through a functional pin, the absolute global clock generation module 1 generates an absolute global clock required by the system according to the external reference clock, and sends the absolute global clock generated by the absolute global clock generation module 1 to a prescaler module 2.
Alternatively, the absolute global clock generation block 1 may be a Phase Locked Loop (PLL).
The prescaler module 2 is configured to generate relative global clocks corresponding to the subsystems 3, respectively, according to the absolute global clock, and issue the relative global clocks to the clock frequency divider module 31 in the matched subsystem 3;
in this embodiment, in order to avoid the problem of large power consumption caused by long-distance clock transmission, a presorting module 2 is introduced into the clock frequency dividing system, and after receiving the absolute global clock sent by the absolute global clock generating module 1, the presorting module 2 divides the frequency of the absolute global clock according to the clock frequency required by each subsystem 3, generates the relative global clocks corresponding to each subsystem 3, and sends each relative global clock to the clock frequency dividing module 31 in the matched subsystem 3. Wherein each clock divider module 31 may receive at least one relative global clock according to actual requirements.
Optionally, at least one relative global clock output by the prescaler module 2 is an asynchronous clock.
In order to ensure that the constraint of the clock division system in this embodiment is correct and simple, and some basic rules related to the clock constraint are observed during the structural design of the division system, in this alternative embodiment, a constraint rule is provided, where at least one of the relative global clocks output by the prescaler module 2 is an asynchronous clock, and each asynchronous clock is placed in a different clock group. Illustratively, the clocks generated by the prescaler module 2 are named as gmc _125M, dma _125M, SD0_96M, and SD1_96M, respectively, and are asynchronous.
Based on the above rules, the clock input ports of the subsystems 3 connected to the prescaler module 2 cannot have 2 relative global clocks that are synchronous at the same time, and if the clocks are 2 synchronous clocks, the clocks need to be combined to ensure that the clocks input to one subsystem 3 are asynchronous.
A clock frequency division module 31, configured to generate at least one synchronous clock according to the relative global clock obtained from the prescaler module 2;
wherein the synchronous clock is used to be supplied to the present or next stage electronic module of the subsystem 3.
In this embodiment, after receiving the relative global clocks sent by the prescaler module 2, the clock divider module 31 generates at least one synchronous clock according to each relative global clock, where the synchronous clock is used to be provided to the electronic module at the current stage or the next stage of the subsystem 3.
For example, the clock dividing module 31 receives 2 relative global clocks, i.e.,. gtmc _125M and. gtma _125M, sent by the presorting module 2, and the clock dividing module 31 may generate a plurality of synchronous clocks, i.e., 2 synchronous clocks, i.e.,. gtmc _125M and. gtmc _62.5M, according to the relative global clock,. gtmc _ 125M; it is also possible to generate a plurality of synchronous clocks, for example 2 synchronous clocks, namely × dma _125M and × dma _62.5M, from the relative global clocks, respectively, although the clocks generated from different relative global clocks are asynchronous clocks, for example, the clock divider module 31 is asynchronous clocks from the clocks generated from the relative global clocks × gmc _125M and × dma _125M, namely gmc _62.5M and × dma _62.5M, respectively. The above-mentioned synchronous clock generated by the clock divider module 31 is used to be supplied to the next stage of electronic modules connected to the subsystem 3 in order to provide the electronic modules with a clock matching their operating frequency.
Optionally, at least one synchronous clock generated by the clock frequency dividing module 31 in each subsystem 3 and each relative global clock generated by the prescaler module 2 are asynchronous clocks.
In this alternative embodiment, a basic rule related to clock constraints is provided, and each synchronous clock generated by the clock frequency dividing module 31 in each subsystem 3 and each relative global clock generated by the pre-frequency dividing module 2 are asynchronous clocks. Illustratively, the clock × gmc _125M generated by the prescaler module 2 is asynchronous with the clock × gmc _125M generated by the clock divider module 31 inside the subsystem 3.
Optionally, the clock in the clock frequency division system goes from the prescaler module 2 to the clock frequency division module 31 included in each subsystem 3, and the clock reverse feedback is not supported.
In this alternative embodiment, another basic rule related to clock constraint is provided, which specifies that the clock in the clock division system runs from the prescaler module 2 to the clock divider module 31 included in each subsystem 3, and does not support clock back-haul. If a synchronous path exists between the bottom layer electronic modules, the clock needs to be accessed from the absolute global clock generation module 1, and the clock generated by the subsystem 3 does not need to be returned.
Optionally, at least one output of the presorting module 2 has the same function as the input of the clock frequency dividing module 31 inside each subsystem 3;
when each subsystem 3 is used alone, the input of the clock division module 31 inside each subsystem 3 is defined as a creation clock;
when each subsystem 3 is in the clock frequency division system, the input of the clock frequency division module 31 in each subsystem 3 is omitted, and at least one output of the prescaler module 2 is defined as a created sub-clock;
creating a sub-clock is a stop point of the previous-stage logic of the system and is also used as a root node of the next-stage logic of the system.
Optionally, at least one output of the absolute global clock generation module 1 has the same function as at least one input of the prescaler module 2;
when the pre-frequency dividing module 2 is used alone, at least one input of the pre-frequency dividing module 2 is defined as creating a clock;
when the prescaler module 2 is in the clock frequency division system, at least one input of the prescaler module 2 is omitted, and at least one output of the absolute global clock generation module 1 is defined as a creation sub-clock;
creating a sub-clock is a stop point of the previous-stage logic of the system and is also used as a root node of the next-stage logic of the system.
In the above two alternative embodiments, there are provided rules for applying relevant Clock constraints and Clock tree synthesis based on the Clock structure shown in fig. 1d, specifically, 3-1-related clocks (representing the Clock named at the beginning of fig. 1d as 3-1, and the same applies to the following description of Clock names including the symbol), that is, the clocks generated by the Clock dividing module 31 included in each subsystem 3 are defined as creating a sub-Clock (Create _ Generate _ Clock) and do not need to be synchronized, and are root nodes (root points) of Clock tree synthesis for lower-level logic (for example, a subsystem next to a current subsystem) and stop points (stop pin points) for previous-level logic (for example, a current subsystem).
3-0-related clocks and 2-1-related clocks are functionally equivalent, where 3-0-is the input Clock of the Clock divider module 31, 2-1-is the Clock output by the prescaler module 2, when each subsystem 3 is used alone, the input (i.e., 3-0-) of the Clock divider module 31 inside each subsystem 3 is defined as a Create Clock (Create Clock), when each subsystem 3 is in the Clock divider system, the definition of the input (i.e., 3-0-) of the Clock divider module 31 may be omitted, and at least one output (i.e., 2-1-) of the prescaler module 2 is defined as a Create sub-Clock (Create _ Generate _ Clock) and synchronization is not required.
In a similar way to the above description, 2-0-related clocks and 1-1-related clocks are functionally equivalent, where 2-0-is the input Clock of the prescaler module 2, 1-1-is the output Clock of the absolute global Clock generator module 1, when the prescaler module 2 is used alone, at least one input (i.e., 2-0-) of the prescaler module 2 is defined as a Create Clock (Create Clock), when the prescaler module 2 is in the Clock divider system, the definition of the input (i.e., 2-0-) of the prescaler module 2 may be omitted, and at least one output (i.e., 1-1-) of the absolute global Clock generator module 1 is defined as a Create sub-Clock (Create _ Generate _ Clock) without synchronization.
In addition, the clocks output by each time are asynchronous, for example, the clocks output by 1-1-, 2-1-, and 3-1-are asynchronous clocks.
Example two
Fig. 2 is a flowchart of a clock frequency division method according to a second embodiment of the present invention, and the technical solution of this embodiment is suitable for a case where a complex SOC clock network is divided into functional modules, and the method can be executed by a clock frequency division system. A clock frequency division method provided by the second embodiment of the present invention is described below with reference to fig. 2, which includes the following steps:
and step 210, the absolute global clock generating module generates an absolute global clock according to the external reference clock and sends the absolute global clock to the pre-frequency dividing module.
In this embodiment, the external reference clock is input to the absolute global clock generation module inside the system through the functional pin, the absolute global clock generation module generates the absolute global clock required by the system according to the external reference clock, and the absolute global clock generated by the absolute global clock generation module is sent to the prescaler module.
And step 220, the pre-frequency division module generates relative global clocks corresponding to the subsystems according to the absolute global clock and sends the relative global clocks to the clock frequency division module in the matched subsystem.
In this embodiment, to avoid the problem of large power consumption caused by long-distance clock transmission, a presorting module is introduced into the clock frequency dividing system, and after receiving the absolute global clock sent by the absolute global clock generating module, the presorting module divides the frequency of the absolute global clock according to the clock frequency required by each subsystem, generates the relative global clocks corresponding to each subsystem, and sends each relative global clock to the clock frequency dividing module in the matched subsystem.
Optionally, at least one relative global clock output by the prescaler module is an asynchronous clock.
In this alternative embodiment, a constraint rule is provided, where at least one of the relative global clocks output by the prescaler module is an asynchronous clock. Illustratively, the clock names generated by the prescaler module are named as gmc _125M, dma _125M, SD0_96M and SD1_96M, the clocks are asynchronous, the clock input ports of the subsystems connected to the prescaler module cannot simultaneously have synchronous relative global clocks, and if the clocks are synchronous clocks, the clocks need to be combined to ensure that the clocks input to one subsystem are asynchronous.
wherein the synchronous clock is used for providing to the electronic module of the current stage or the next stage of the subsystem.
In this embodiment, after receiving the relative global clocks sent by the pre-dividing module, the clock dividing module generates at least one synchronous clock according to each relative global clock, where the synchronous clock is used to be provided to the electronic module at the current stage or the next stage of the subsystem, and the electronic module is the lowest unit in the clock dividing system.
Illustratively, the clock dividing module receives 2 relative global clocks, namely, gmc _125M and dma _125M, sent by the presorting module, and the clock dividing module may generate a plurality of synchronous clocks, for example, 2 synchronous clocks, namely, gmc _125M and gmc _62.5M, according to the relative global clock, namely, gmc _ 125M; it is also possible to generate a plurality of synchronized clocks, for example 2 synchronized clocks, namely dmax 125M and dmax 62.5M, from the relative global clock dmax 125M, the synchronized clocks generated by the clock divider module being intended to be supplied to the next electronic module connected to the subsystem in order to provide the electronic module with a clock matching its operating frequency.
The technical proposal of the embodiment of the invention is that an absolute global clock generating module generates an absolute global clock according to an external reference clock and sends the absolute global clock to a pre-frequency dividing module, the pre-frequency dividing module generates relative global clocks respectively corresponding to each subsystem according to the absolute global clock, and each relative global clock is sent to a clock frequency division module in the matched subsystem, and finally the clock frequency division module generates at least one synchronous clock according to the relative global clock obtained from the presorting module, the system is used for providing the electronic module of the current stage or the next stage to a subsystem, solves the problems that the use of a dispersed frequency division circuit module or a single clock frequency division circuit module in the prior art easily causes disordered clock relation and complex clock constraint, and influences the comprehensive quality of a clock tree, and adopts a multi-level clock special module to carry out layering and normalized processing on a complex SOC clock network structure.
EXAMPLE III
Fig. 3 is a schematic structural diagram of an electronic device in a third embodiment of the present invention, as shown in fig. 3, the electronic device includes a clock frequency division system 30 provided in any embodiment, the clock frequency division system 30 includes an absolute global clock generation module 1, a prescaler module 2, and at least one subsystem 3, and each subsystem 3 includes a clock frequency division module 31; the absolute global clock generation module 1 is connected with the prescaler module 2, and the prescaler module 2 is respectively connected with the clock frequency dividing module 31 in each subsystem 3.
Optionally, the electronic device further comprises a plurality of electronic modules 4, and a clock divider module 31 included in each subsystem 3 is connected to at least one of the electronic modules 4.
The absolute global clock generating module 1 is used for generating an absolute global clock and sending the absolute global clock to the pre-frequency dividing module 2;
the pre-frequency division module 2 is configured to generate relative global clocks corresponding to the subsystems 3 respectively according to the absolute global clock, and issue the relative global clocks to the clock frequency division module 31 in the matched subsystem 3;
the clock frequency division module 31 is configured to generate at least one synchronous clock according to the relative global clock obtained from the prescaler module 2;
wherein the synchronous clock is used to be provided to the next stage electronic module 4 of the subsystem 3.
The technical proposal of the embodiment of the invention is that an absolute global clock generating module generates an absolute global clock according to an external reference clock and sends the absolute global clock to a pre-frequency dividing module, the pre-frequency dividing module generates relative global clocks respectively corresponding to each subsystem according to the absolute global clock, and each relative global clock is sent to a clock frequency division module in the matched subsystem, and finally the clock frequency division module generates at least one synchronous clock according to the relative global clock obtained from the presorting module, the system is used for providing the electronic module of the current stage or the next stage to a subsystem, solves the problems that the use of a dispersed frequency division circuit module or a single clock frequency division circuit module in the prior art easily causes disordered clock relation and complex clock constraint, and influences the comprehensive quality of a clock tree, and adopts a multi-level clock special module to carry out layering and normalized processing on a complex SOC clock network structure.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A clock division system, comprising: the system comprises an absolute global clock generation module, a prescaler module and at least one subsystem, wherein each subsystem comprises a clock frequency division module; the absolute global clock generation module is connected with the prescaler module, and the prescaler module is respectively connected with the clock frequency division module in each subsystem;
the absolute global clock generating module is used for generating an absolute global clock and sending the absolute global clock to the presorting module;
the pre-frequency division module is used for generating relative global clocks corresponding to the subsystems respectively according to the absolute global clock and sending the relative global clocks to the clock frequency division module in the matched subsystem;
the clock frequency division module is used for generating at least one synchronous clock according to the relative global clock acquired from the pre-frequency division module;
wherein the synchronous clock is used for providing to the electronic module at the current stage or the next stage of the subsystem.
2. The system of claim 1, wherein the at least one relative global clock output by the pre-divide module is an asynchronous clock.
3. The system of claim 1, wherein at least one of the synchronous clocks generated by the clock divider module within each subsystem is asynchronous with respect to each of the relative global clocks generated by the prescaler module.
4. The system of claim 1, wherein the clock in the clock divider system is routed from the prescaler to the clock divider included in each subsystem, and does not support clock back-haul.
5. The system of claim 1, wherein at least one output of the pre-divide module is functionally identical to an input of a clock divide module internal to each subsystem;
when each subsystem is used independently, the input of the clock frequency division module in each subsystem is defined as a created clock;
when each subsystem is in the clock frequency division system, omitting the input of a clock frequency division module in each subsystem, and defining at least one output of the pre-frequency division module as a created sub-clock;
the created sub-clock is a stop point of the front-stage logic of the system and is also used as a root node of the rear-stage logic of the system.
6. The system of claim 1, wherein at least one output of the absolute global clock generation module is functionally identical to at least one input of a prescaler module;
when the pre-frequency dividing module is used independently, at least one input of the pre-frequency dividing module is defined as a created clock;
when the prescaler module is in the clock frequency division system, at least one input of the prescaler module is omitted, and at least one output of the absolute global clock generation module is defined as a creation sub-clock;
the created sub-clock is a stop point of the front-stage logic of the system and is also used as a root node of the rear-stage logic of the system.
7. A method of clock division, comprising:
the absolute global clock generation module generates an absolute global clock according to an external reference clock and sends the absolute global clock to the pre-frequency division module;
the pre-frequency division module generates relative global clocks corresponding to the subsystems respectively according to the absolute global clock and sends the relative global clocks to the clock frequency division module in the matched subsystem;
the clock frequency division module generates at least one synchronous clock according to the relative global clock acquired from the pre-frequency division module;
wherein the synchronous clock is used for providing to the electronic module at the current stage or the next stage of the subsystem.
8. The method of claim 7, wherein the at least one relative global clock output by the pre-divide module is an asynchronous clock.
9. An electronic device comprising a clock division system as claimed in any one of claims 1 to 6.
10. The electronic device of claim 9, further comprising: and the clock frequency division module in each subsystem is connected with at least one electronic module.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114546030A (en) * | 2022-02-15 | 2022-05-27 | 海光信息技术股份有限公司 | Chip clock design method, chip, device and related equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101610123A (en) * | 2009-07-10 | 2009-12-23 | 中兴通讯股份有限公司 | A kind of clock unit and its implementation |
| US20130278302A1 (en) * | 2012-04-20 | 2013-10-24 | Huawei Technologies Co., Ltd. | Clock signal generator |
| CN104821802A (en) * | 2014-02-05 | 2015-08-05 | 株式会社巨晶片 | Clock operation method and circuit |
| US20160072508A1 (en) * | 2014-09-04 | 2016-03-10 | Texas Instruments Deutschland Gmbh | Shared divide by n clock divider |
| US20160142066A1 (en) * | 2014-11-14 | 2016-05-19 | Cavium, Inc. | Frequency division clock alignment |
| US10871796B1 (en) * | 2019-08-06 | 2020-12-22 | Xilinx, Inc. | Global clock and a leaf clock divider |
-
2020
- 2020-12-30 CN CN202011615830.7A patent/CN112671403A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101610123A (en) * | 2009-07-10 | 2009-12-23 | 中兴通讯股份有限公司 | A kind of clock unit and its implementation |
| US20130278302A1 (en) * | 2012-04-20 | 2013-10-24 | Huawei Technologies Co., Ltd. | Clock signal generator |
| CN104821802A (en) * | 2014-02-05 | 2015-08-05 | 株式会社巨晶片 | Clock operation method and circuit |
| US20160072508A1 (en) * | 2014-09-04 | 2016-03-10 | Texas Instruments Deutschland Gmbh | Shared divide by n clock divider |
| US20160142066A1 (en) * | 2014-11-14 | 2016-05-19 | Cavium, Inc. | Frequency division clock alignment |
| US10871796B1 (en) * | 2019-08-06 | 2020-12-22 | Xilinx, Inc. | Global clock and a leaf clock divider |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114546030A (en) * | 2022-02-15 | 2022-05-27 | 海光信息技术股份有限公司 | Chip clock design method, chip, device and related equipment |
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