CN114546030A

CN114546030A - Chip clock design method, chip, device and related equipment

Info

Publication number: CN114546030A
Application number: CN202210138605.1A
Authority: CN
Inventors: 徐祥俊; 王明波; 王科
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2022-02-15
Filing date: 2022-02-15
Publication date: 2022-05-27

Abstract

The embodiment of the application provides a clock design method of a chip, the chip, a device and related equipment, wherein the method comprises the following steps: first clock generation logic designed to provide clocks to a plurality of functional modules of a chip, the first clock generation logic configured to generate a plurality of functional clocks of different frequencies in phase according to a clock frequency used by the plurality of functional modules; and designing a corresponding relation between the plurality of functional clocks and the plurality of functional modules, wherein one functional clock corresponds to at least one functional module using the frequency of the functional clock. The embodiment of the application can reduce the number of asynchronous clocks in the chip and reduce the negative influence of the asynchronous clocks on the performance, power consumption and area of the chip. Furthermore, the embodiment of the application can also guarantee the timing constraint correctness of the signals and realize the optimization of cross-clock signal processing.

Description

Chip clock design method, chip, device and related equipment

Technical Field

The embodiment of the application relates to the technical field of processors, in particular to a clock design method of a chip, the chip, a device and related equipment.

Background

With the development of integrated circuits and the improvement of processes, the integration level of chips is continuously improved, and large-scale chip design has become the mainstream. On a large-scale chip, a plurality of functional modules need to be integrated and communication between the functional modules needs to be realized, and a clock signal (clock for short) is used as a basis for working of the functional modules, so how to design a clock for the functional modules in the chip when the chip is designed becomes a technical problem that needs to be solved by technical personnel in the field.

Disclosure of Invention

In view of this, embodiments of the present application provide a chip clock design method, a chip, a device, and a related apparatus, so as to reduce the number of asynchronous clocks in the chip, reduce negative effects of the asynchronous clocks on performance, power consumption, and area of the chip, and provide a basis for guaranteeing timing constraint correctness of asynchronous signals.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions.

In a first aspect, an embodiment of the present application provides a method for designing a clock of a chip, including:

first clock generation logic designed to provide clocks to a plurality of functional modules of a chip, the first clock generation logic configured to generate a plurality of functional clocks of different frequencies in phase according to a clock frequency used by the plurality of functional modules;

and designing a corresponding relation between the plurality of functional clocks and the plurality of functional modules, wherein one functional clock corresponds to at least one functional module using the frequency of the functional clock.

In a second aspect, an embodiment of the present application provides a chip, including: a plurality of functional modules, and first clock generation logic;

the first clock generation logic is used for generating a plurality of function clocks with same phase and different frequencies according to the clock frequencies used by the plurality of function modules; and providing the functional clocks to corresponding functional modules, wherein one functional clock corresponds to at least one functional module using the frequency of the functional clock.

In a third aspect, an embodiment of the present application provides a clock designing apparatus, including:

a clock generation logic design unit for designing a first clock generation logic for providing a clock to a plurality of functional modules of a chip, the first clock generation logic being configured to generate a plurality of functional clocks of different frequencies in phase according to clock frequencies used by the plurality of functional modules;

and the relationship design unit is used for designing the corresponding relationship between the plurality of functional clocks and the plurality of functional modules, and one functional clock corresponds to at least one functional module using the frequency of the functional clock.

In a fourth aspect, an embodiment of the present application provides a computer device, including at least one memory and at least one processor, where the at least one memory stores one or more computer-executable instructions, and the at least one processor invokes the one or more computer-executable instructions to perform the clock design method for a chip as described in the first aspect.

In a fifth aspect, an embodiment of the present application provides a storage medium storing one or more computer-executable instructions, which when executed implement the clock design method of the chip according to the first aspect.

In a sixth aspect, an embodiment of the present application provides an electronic device, including the chip as described in the second aspect.

According to the clock design method of the chip, when the clock is designed for a plurality of functional modules with different clock frequencies in the chip, a first clock generation logic can be designed; based on the clock frequencies used by the plurality of functional modules, in the embodiment of the present application, the first clock generation logic may be designed to generate a plurality of functional clocks having the same phase and different frequencies, and a corresponding relationship between the plurality of functional clocks and the plurality of functional modules may be designed, so that one functional clock corresponds to a functional module using the frequency of the functional clock, and thus the functional clocks adapted to the clock frequencies of the functional modules are respectively configured to the functional modules, so as to design clocks for the plurality of functional modules using different clock frequencies. In this embodiment of the present application, because the plurality of functional clocks generated by the first clock generation logic are in-phase and at different frequencies, the plurality of functional clocks are synchronous clocks, that is, the plurality of synchronous clocks generated by the first clock generation logic in this embodiment of the present application can design clocks for a plurality of functional modules using different clock frequencies, so as to avoid designing asynchronous clocks for the plurality of functional modules, reduce the number of asynchronous clocks in a chip, and further reduce the negative impact of the asynchronous clocks on the performance, power consumption and area of the chip. Meanwhile, due to the fact that the number of the asynchronous clocks is reduced, the time sequence constraint workload of the asynchronous signals can be reduced, and a foundation is provided for guaranteeing the time sequence constraint correctness of the asynchronous signals.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a diagram of an example of a clock design for a chip.

FIG. 2A is a flow chart of a clock design method for a chip.

FIG. 2B is another flow chart of a clock design method for a chip.

FIG. 3A is a diagram of another exemplary clock design for a chip.

Fig. 3B is a diagram illustrating waveforms of clocks having the same phase and a frequency in a multiple relationship.

FIG. 3C is a diagram illustrating waveforms of clocks with different phases and frequencies.

FIG. 4A is a flow chart of a method of designing first clock generation logic.

Fig. 4B is a diagram illustrating a structure of the first clock generation logic.

Fig. 4C is a diagram showing another example of the structure of the first clock generation logic.

Fig. 4D is a diagram illustrating waveforms.

FIG. 5 is a diagram of another exemplary clock design for a chip.

FIG. 6A is a flow chart of a method of designing timing constraints.

FIG. 6B is a flow diagram of a method of designing cross-clock signal processing logic.

Fig. 7 is a block diagram of a clock design apparatus.

Fig. 8A is a diagram illustrating a chip structure.

Fig. 8B is another exemplary structure of the chip.

Fig. 8C is a diagram illustrating another exemplary structure of the chip.

Fig. 8D is a diagram illustrating another exemplary structure of a chip.

Fig. 9 is an exemplary diagram of a chip implementation.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The clock design of the chip is mainly divided into a synchronous timing design and an asynchronous timing design.

The synchronous time sequence design means that functional modules in a chip all use the same clock, that is, the chip has a globally uniform clock, and all flip-flops in the chip are uniformly updated at the same time on the rising edge (or the falling edge) of the clock, so as to realize logic operation and output. It should be noted that, the clock of the chip is provided by the clock generation logic, for example, a clock generation circuit (an implementation manner of the clock generation logic) generates and provides a clock signal for the functional module in the chip; the functional module of the chip may be a device that implements functions in the chip, such as a Central Processing Unit (CPU) core, a memory controller, an accelerator, and the like in the chip.

Asynchronous timing design refers to chip design using multiple different clocks. Each functional module in the chip generally has its own design requirement (for example, each functional module has its own performance requirement), and different design requirements may have different clock requirements, so that when there are multiple different clock requirements for multiple functional modules of the chip, multiple clocks need to be designed for the multiple functional modules in the chip based on an asynchronous timing design manner.

A plurality of clocks designed in a chip are mainly divided into synchronous clocks and asynchronous clocks, the plurality of clocks with fixed phase relation are generally synchronous clocks, and the plurality of clocks with unfixed phase relation are generally asynchronous clocks. The unfixed phase relationship between the clocks may be that the phase relationship between the clocks cannot be judged because the phase relationship between the clocks is not constrained; for example, clocks generated by different clock generation logic in a chip, and clocks generated by the same clock generation logic without phase relationship constraints, are generally asynchronous clocks. It should be noted that a complete clock cycle is 360 degrees in phase, and is referred to as 0 degrees in phase if a clock starts from a rising edge, 180 degrees in phase if a clock starts from a falling edge, and so on.

When designing a clock according to the clock requirements of functional modules, if a plurality of functional modules in a chip require different clock frequencies, a plurality of asynchronous clocks with corresponding quantity are designed for the plurality of functional modules in the chip at present so as to meet the clock frequency requirements of the plurality of functional modules; that is, according to the number of clocks with different frequencies required by a plurality of functional modules, a corresponding number of asynchronous clocks are designed in the chip. The sequential logic in the chip is synchronized by a clock, and the clock frequency refers to the frequency of the clock used by the sequential logic.

More specifically, when designing a clock for a functional module in a chip, the requirements of the functional module for the clock are mainly classified into the following three cases.

In the first case, a clock with a corresponding frequency needs to be designed for the functional module based on the performance requirement of the functional module, and the clock frequency of the functional module is adjusted according to the performance requirement of the functional module; for the first case, the clock of the functional module in the first case is mainly designed to be an asynchronous clock, for example, the clock between different functional modules in the first case is in an asynchronous clock relationship, and the clock of the functional module in the first case and the clock of the functional module in the second case and the clock of the functional module in the third case, which are described later, are in an asynchronous clock relationship.

In the second case, based on the hard requirements of protocols, standards or third-party IP (intellectual property), the functional module needs to design a clock with parameters such as specific frequency, duty ratio, etc.; at this time, since the functional module needs to comply with the hard requirements of the protocol, the standard, or the third IP, the functional module can only design the clock with a specific frequency according to the hard requirements; for the second situation, a clock may be designed for the functional module in the second situation according to the design manner of the asynchronous clock, for example, a clock having an asynchronous clock relationship with other functional modules is designed for the functional module in the second situation. It should be noted that, when the clocks of the two functional modules are asynchronous clocks, the two functional modules need to perform asynchronous processing on signals when interacting with each other.

In the third case, the functional module itself has no requirement for the clock, for example, the functional module itself has no requirement for the clock frequency; at this time, the performance requirement and the process condition of the whole chip can be considered, and a clock with a fixed frequency is selected to be used by the functional module in the third condition.

Fig. 1 schematically shows an exemplary clock design diagram of a chip according to the clock design of the above three cases, and as shown in fig. 1, the chip includes

functional blocks

110, 120, 130 and 140. The functional modules 110 and 120 correspond to the first case, and it is necessary to design clocks 111 and 121 with corresponding frequencies for the functional modules 110 and 120, respectively, based on the performance requirements of the functional modules 110 and 120, respectively, and the clocks 111 and 121 are asynchronous clocks. In response to the second case, the functional module 130 needs to design a clock 131 with a specific frequency for the functional module 130 based on the protocol, the standard or the hard requirement of the third IP, and the clock 131 and the clocks 111 and 121 are both in an asynchronous clock relationship. The functional module 140 corresponds to the third case, and if the functional module 140 has no requirement for the clock, the functional module 140 may be designed with a clock 141 with a fixed frequency based on the performance requirement and the process condition of the whole chip, and the clock 141 and the clocks 111, 121, and 131 are all asynchronous clocks.

As can be seen from the example of fig. 1, when the clock frequencies required by the plurality of functional modules in the chip are different, a plurality of asynchronous clocks with corresponding numbers are designed for the plurality of functional modules in the chip. However, in the background of increasing chip scale and more complicated integrated functions, the number of asynchronous clocks required by different functional modules in the chip will increase, which will result in a concomitant increase in the number of asynchronous clocks in the chip, and the increase in the number of asynchronous clocks will have a negative effect on the performance, power consumption and area of the chip.

Further, the increased number of asynchronous clocks will make the timing constraint correctness of the asynchronous signals difficult to guarantee. Asynchronous signals refer to signals transmitted between asynchronous clocks. At present, timing constraint of asynchronous signals in a chip is generally added by designers, and with the increase of the number of asynchronous clocks, the workload of the designers for adding the timing constraint to the asynchronous signals is also increased sharply, so that the possibility that the designers add wrong timing constraint to the asynchronous signals is increased, and the accuracy of the timing constraint of the asynchronous signals is further influenced.

It should be noted that the asynchronous timing design can be used in the case of signal transmission from one clock to another, and in the case of designing multiple clocks, timing constraints are required for signals crossing the clocks, and the timing constraint of the asynchronous signals described above is one of the timing constraints of the signals crossing the clocks.

It can be seen from the above description that, according to different clock frequencies required by a plurality of functional modules in a chip, a plurality of asynchronous clocks of corresponding number are designed for the plurality of functional modules in the chip, which will cause an increase in the number of asynchronous clocks in the chip and further cause a series of problems under the background that the chip scale is increased and the integration function is more complex.

The inventor of the present application has found through research that, for the three cases, although the clock frequencies required by the functional modules in each case are different, from the viewpoint of chip design, when a plurality of functional modules require different clock frequencies, synchronous clocks with the same phase and different frequencies are designed for the plurality of functional modules, so that the clocks of the plurality of functional modules are prevented from being designed as asynchronous clocks, and the effect of reducing the number of asynchronous clocks in a chip is achieved. For example, the clock of the functional module under the multiple conditions may be considered as a whole, and the clock of the functional module under the multiple conditions is designed to be the synchronous clock with the same phase and different frequencies, and the synchronous clock with the same phase and different frequencies is generated by the same clock generation logic, so that the clock of the functional module under the multiple conditions is prevented from being designed to be the asynchronous clock.

Based on the above thought, the embodiments of the present application provide an improved clock design scheme to reduce the number of asynchronous clocks in a chip, reduce negative effects of the asynchronous clocks on the performance, power consumption, and area of the chip, reduce the workload of timing constraint of asynchronous signals, and provide a basis for guaranteeing the correctness of the timing constraint of the asynchronous signals.

As an alternative implementation, fig. 2A illustrates an alternative flow chart of a clock design method for a chip. The method flow may be implemented by execution of design software, for example, by execution of the design software by a computer device (e.g., a host) used for chip design. Referring to fig. 2A, the method flow may include the following steps.

In step S210, a plurality of functional modules of the chip, which use different clock frequencies, are determined.

When designing a clock for a plurality of functional modules of a chip, embodiments of the present application may determine the plurality of functional modules for which the clock needs to be designed. For example, a CPU, a plurality of buses, a DDR PHY, etc. of a chip, which need to design a clock; herein, DDR is an abbreviation of Double Data Rate SDRAM and represents a Double Rate synchronous dynamic random access memory, and PHY is an abbreviation of Physical and represents a port Physical layer.

In some embodiments, a plurality of functional blocks using different clock frequencies may correspond to the functional blocks of the various cases described above. For example, the plurality of functional modules may include a functional module corresponding to the first case described above, and a functional module corresponding to the second case described above. For another example, the plurality of functional modules may include a functional module corresponding to the first case and a functional module corresponding to the third case. For another example, the plurality of functional modules may include a functional module corresponding to the first case, a functional module corresponding to the second case, and a functional module corresponding to the third case.

In other embodiments, the plurality of functional modules using different clock frequencies may also be only the functional module corresponding to the first case described above. For example, the plurality of functional modules are a plurality of functional modules in the first case, and each functional module uses a clock of a different frequency based on its own performance requirement.

In step S211, a first clock generation logic configured to provide clocks to the plurality of functional modules is designed, the first clock generation logic configured to generate a plurality of functional clocks having different frequencies in phase according to the clock frequencies used by the plurality of functional modules.

In step S212, a correspondence relationship between the plurality of functional clocks and the plurality of functional modules is designed, and one functional clock corresponds to at least one functional module using a frequency of the functional clock.

Different from a mode of designing an asynchronous clock for a plurality of functional modules using different clock frequencies, in the embodiment of the present application, a plurality of functional clocks having the same phase and different frequencies can be designed for the plurality of functional modules according to the clock frequencies respectively used by the plurality of functional modules (the plurality of functional clocks belong to a synchronous clock because the plurality of functional clocks have the same phase and different frequencies), and the functional clocks adapted to the clock frequencies of the functional modules are respectively configured for the functional modules to be used, so that the number of the asynchronous clocks in the chip is reduced.

Based on this, in the embodiment of the present application, the first clock generation logic may be uniformly designed for a plurality of functional modules using different clock frequencies, the plurality of functional clocks having the same phase and different frequencies are generated by designing the first clock generation logic, and the correspondence between the plurality of functional clocks and the plurality of functional modules is designed, so that one functional clock corresponds to the functional module using the frequency of the functional clock, and the functional clocks adapted to the clock frequency of each functional module are configured for each functional module to use. In some embodiments, the plurality of functional clocks corresponds to a number of clock frequencies used by the plurality of functional modules. According to the embodiment of the application, the clocks are designed for the functional modules through the functional clocks belonging to the synchronous clocks, so that the asynchronous clocks are prevented from being designed for the functional modules using different clock frequencies, and the effect of reducing the number of the asynchronous clocks in a chip is achieved.

In some embodiments, the functional blocks in the flow of fig. 2A that use different clock frequencies may correspond to the functional blocks in the various cases described above. As an alternative implementation, fig. 2B illustrates another alternative flow chart of a clock design method of a chip. Referring to fig. 2B, the method flow may include the following steps.

In step S220, determining a plurality of functional modules of the chip, where the plurality of functional modules use different clock frequencies, and the plurality of functional modules include a first functional module and a second functional module; the first functional module uses a clock with a frequency corresponding to the performance requirement of the first functional module, and the second functional module uses a clock with a specific frequency.

In the embodiment of the present application, for convenience of description, the functional module corresponding to the first case is referred to as a first functional module, that is, the first functional module determines the frequency of the clock based on its performance requirement, and the first functional module adjusts the frequency of the clock to be used according to the change of the performance requirement. As an optional implementation, the chip may have a plurality of first functional modules, and when the number of the first functional modules is multiple, the plurality of first functional modules may use clocks of the same frequency or clocks of different frequencies based on their respective performance requirements; for example, the performance requirement of each first functional module may correspond to a clock of the same frequency; for another example, the performance requirements of different first functional modules correspond to clocks with different frequencies, at this time, the plurality of first functional modules need to use a plurality of clocks with different frequencies, and the number of the plurality of clocks with different frequencies corresponds to the number of clock frequencies corresponding to the performance requirements of the plurality of first functional modules.

The second functional module is a functional module in which the clock in the embodiment of the present application uses a specific frequency. For example, the second functional module may be a functional module corresponding to the second case described above, and the second functional module uses a clock of a specific frequency based on a protocol, a standard, or a hard requirement of the third IP. For another example, the second functional module may also be a functional module corresponding to the third case, and in the case that the second functional module has no clock requirement, the second functional module may use a clock with a fixed frequency based on the performance requirement and the process condition of the whole chip, and the clock with the fixed frequency may also be regarded as a clock with a fixed specific frequency.

In step S221, a first clock generation logic is designed, and the first clock generation logic is configured to generate a plurality of functional clocks with different frequencies in phase according to the clock frequencies used by the first functional module and the second functional module.

In step S222, designing a functional clock adapted to the clock frequency of the first functional module, and corresponding to the first functional module; and designing a functional clock adapted to the specific frequency, and corresponding to the second functional module.

The embodiment of the application can configure the first clock generation logic for the first functional module and the second functional module in a unified manner, generate a plurality of functional clocks with the same phase and different frequencies by designing the first clock generation logic, and design the corresponding relationship between the functional clocks and the first functional module and the second functional module, so that the functional clocks respectively adapting to the clock frequencies of the first functional module and the second functional module are configured for the first functional module and the second functional module respectively, and the clocks are respectively designed for the first functional module and the second functional module by the plurality of functional clocks belonging to the synchronous clock, thereby realizing the effect of reducing the number of asynchronous clocks in a chip.

As an optional implementation, when designing a correspondence between a functional clock and a first functional module and a second functional module, the embodiment of the present application may configure the functional clock corresponding to the clock frequency used by the first functional module to the first functional module, and establish the correspondence between the functional clock and the first functional module; and configuring a functional clock corresponding to the clock frequency used by the second functional module to the second functional module, and establishing a corresponding relation between the functional clock and the second functional module. It should be noted that, during design, the frequency of each functional clock generated by the first clock generation logic may be adjusted based on the clock frequency required by the corresponding functional module, and in the embodiment of the present application, only the frequency of the functional clock corresponding to the functional module is ensured and can be adjusted to the frequency required by the functional module, so that the functional clock and the functional module may maintain a fixed correspondence relationship in the establishment of a possible correspondence relationship.

In this embodiment, the first clock generation logic may generate a plurality of function clocks with adaptive frequencies based on the clock frequencies respectively used by the first functional module and the second functional module, and the plurality of function clocks are in phase and have different frequencies; in some embodiments, the number of the plurality of functional clocks generated by the first clock generation logic may correspond to the number of clock frequencies used by the first functional module and the second functional module.

In some embodiments, since the first functional module corresponds to the functional module in the first case, when the number of the first functional modules is multiple, each first functional module needs to use a clock with a corresponding frequency based on its performance requirement; based on this, the embodiment of the application can adjust the frequency of the functional clock corresponding to each first functional module to the clock frequency required by each first functional module, and allocate the frequency to each first functional module respectively. As an alternative implementation, one functional clock generated by the first clock generation logic may be used for one or more first functional modules. For example, the clock frequencies used by the first functional modules may be the same or different; the one functional clock generated by the first clock generation logic may be used for a plurality of second functional modules having the same frequency when the frequencies of the clocks used by the plurality of second functional modules are the same. When the clock frequencies used by the plurality of first functional modules are different, the clock frequencies used by the respective first functional modules may be different from each other, or the clock frequencies used by some of the first functional modules may be the same, and the clock frequencies used by some of the first functional modules are different, at this time, the first clock generation logic may generate a plurality of functional clocks for the plurality of first functional modules, and one functional clock may be used for one or more first functional modules having the same clock frequency.

Since the second functional module uses the clock with the specific frequency, the embodiment of the present application may set the frequency of the functional clock corresponding to the second functional module to the specific frequency used by the second functional module, and configure the functional clock with the specific frequency to the second functional module.

In some embodiments, the clock design scheme provided by the embodiments of the present application is illustrated below with reference to examples. Based on the example of FIG. 1, FIG. 3A illustrates another exemplary clock design diagram for a chip; as shown in fig. 3A, the functional modules 110 and 120 are an example of a first functional module, which corresponds to the functional module of the first case; the function module 130 is an example of a second function module, which corresponds to the function module of the second case. When the functional modules 110 and 120 use clocks of different frequencies based on their performance requirements and the functional module 130 uses a clock of a specific frequency based on hard requirements, the embodiment of the present application may design the first clock generation logic 300 to generate a plurality of functional clocks 310, 320 and 330 of different frequencies in phase; wherein, the frequency of the functional clock 310 is the same as the clock frequency used by the functional module 110, the frequency of the functional clock 320 is the same as the clock frequency used by the functional module 120, and the frequency of the functional clock 330 is the same as the specific frequency used by the functional module 130; therefore, the embodiment of the present application may configure the functional clock 310 for the functional module 110, configure the functional clock 320 for the functional module 120, and configure the functional clock 330 for the functional module 130, so as to design clocks for the functional modules using the first case and the second case with different clock frequencies through a plurality of synchronous clocks, thereby reducing the number of asynchronous clocks in the chip.

In other possible examples, the first clock generation logic 300 shown in fig. 3A may also generate the functional clock for the functional module 140 illustrated in fig. 1, or the first clock generation logic 300 in fig. 3A may generate the functional clock for the functional module 130 instead of generating the functional clock for the functional module 140.

Therefore, the embodiment of the application can provide the synchronous clocks with the same phase and different frequencies for the functional modules under various conditions on the basis of comprehensively considering the clock frequencies of the functional modules under various conditions in the foregoing, so as to realize clock design for the functional modules under various conditions and reduce the number of asynchronous clocks designed in the chip.

In other possible implementations, the plurality of functional modules using different clock frequencies may also be a plurality of functional modules in the first case, such as the functional modules 110 and 120 shown in fig. 3A. The embodiment of the present application can also achieve the effect of reducing the number of asynchronous clocks by providing a plurality of functional clocks with the same phase and different frequencies for a plurality of functional modules in the first case.

According to the clock design method provided by the embodiment of the application, when clocks are designed for a first functional module and a second functional module in a chip, a first clock generation logic can be designed; based on the fact that the first functional module uses a clock with a frequency corresponding to the performance requirement of the first functional module and the second functional module uses a clock with a specific frequency, the first clock generation logic can be designed to generate a plurality of functional clocks with the same phase and different frequencies according to the clock frequencies used by the first functional module and the second functional module; and designing a corresponding relationship between the plurality of functional clocks and the first functional module and the second functional module, so that the functional clocks adapted to the clock frequencies of the first functional module and the second functional module are respectively configured to the first functional module and the second functional module, thereby realizing the design of the clocks for the first functional module and the second functional module using different clock frequencies. Because the plurality of functional clocks generated by the first clock generation logic are in-phase and different in frequency, and are synchronous clocks, the embodiment of the application can avoid designing asynchronous clocks for the first functional module and the second functional module which use different clock frequencies, can reduce the number of the asynchronous clocks in a chip, and further reduces the negative influence of the asynchronous clocks on the performance, the power consumption and the area of the chip. Meanwhile, the workload of adding time sequence constraint of the asynchronous signals is reduced, and a foundation is provided for guaranteeing the correctness of the time sequence constraint of the asynchronous signals.

In some embodiments, the frequencies of the plurality of functional clocks generated by the first clock generation logic may be in a multiple relationship (e.g., an integer multiple relationship), and in one example, fig. 3B illustrates an example graph of waveforms of two clocks a1 and a2 in phase and at frequencies in a multiple relationship, as may be referenced. In other embodiments, the frequencies of the plurality of functional clocks generated by the first clock generation logic may also be in a non-multiple relationship (e.g., a non-integer multiple relationship), and in one example, fig. 3C illustrates an example graph of waveforms of two clocks B1 and B2 that are in phase and have non-multiple frequencies, which may be referenced.

It should be noted that, in the embodiment of the present application, it is not limited whether frequencies of the functional clocks have a multiple relationship, but it is only required to ensure that the frequencies of the plurality of functional clocks generated by the first clock generation logic can be matched with the clock frequency used by the corresponding functional module.

In some further embodiments, the first clock generation logic may be further configured to generate a reference clock, where the frequency of the reference clock may be a common divisor of the frequencies of the plurality of functional clocks. As an optional implementation, in the embodiment of the present application, a reference clock may be provided for the first clock generation logic, and a reference clock and a plurality of functional clocks may be obtained by performing frequency amplification processing on the reference clock and performing frequency division processing on the high-frequency clock with amplified frequency for a plurality of times, respectively; wherein, the high frequency clock is subjected to a frequency division process, so as to obtain a clock (such as a reference clock or a functional clock) output by the first clock generation logic. Based on this idea, fig. 4A schematically illustrates a flowchart of an alternative method for designing the first clock generation logic according to an embodiment of the present application. Referring to fig. 4A, the method flow may include the following steps.

In step S410, a frequency amplification circuit is designed, which is configured to perform frequency amplification processing on the supplied reference clock to obtain a high-frequency clock.

In step S411, designing a plurality of frequency dividing circuits connected to the frequency amplifying circuit, the plurality of frequency dividing circuits being configured to perform frequency dividing processing on the high-frequency clock according to respective frequency dividing configurations to obtain a reference clock and a plurality of functional clocks; wherein one of the frequency dividing circuits outputs one clock based on its own frequency dividing configuration.

As an optional implementation, the frequency of the reference clock is a common divisor of the frequencies of the plurality of functional clocks, and the frequency of the reference clock is the same as the frequency of the reference clock.

Based on the idea of the method flow shown in fig. 4A, fig. 4B is a diagram schematically illustrating a structural example of a first clock generation logic, as shown in fig. 4B, a first clock generation logic takes a reference clock as an input, and simultaneously outputs a reference clock and a plurality of functional clocks with different phases and different frequencies, and the phase of the functional clocks is the same as that of the reference clock; a first clock generation logic may comprise: a frequency amplifying circuit 421 and a plurality of frequency dividing circuits 422.

The frequency amplification circuit is used for carrying out frequency amplification processing on the reference clock to obtain a high-frequency clock; as an alternative implementation, the frequency amplifying circuit may be configured with a frequency multiplication factor, and generate the high-frequency clock by performing frequency multiplication amplification on the reference clock by the frequency multiplication factor.

A frequency dividing circuit for dividing the high frequency clock once to obtain a clock (e.g., a reference clock or a functional clock) generated by the first clock generation logic; as an alternative implementation, each frequency dividing circuit may set a frequency dividing configuration (a frequency dividing multiple or a desired frequency after frequency division), so that one frequency dividing circuit may perform frequency dividing processing on the high-frequency clock in accordance with its own frequency dividing configuration to output one clock generated by the first clock generation logic.

In some embodiments, for a plurality of functional modules using different clock frequencies, a functional module using the same clock frequency may correspond to one frequency dividing circuit, and one frequency dividing circuit outputs one clock based on its own frequency dividing configuration and supplies it to the corresponding functional module.

As an alternative implementation, in the first clock generation logic, the reference clock may correspond to one frequency dividing circuit, and one functional clock may correspond to one frequency dividing circuit. In some embodiments in which the frequency dividing circuit implements frequency dividing processing, the embodiments of the present application may set a frequency dividing configuration (a desired frequency or a frequency dividing multiple corresponding to the reference clock) for the frequency dividing circuit corresponding to the reference clock, so as to divide the high-frequency clock to obtain the reference clock. For a frequency dividing circuit corresponding to any functional clock, in the embodiments of the present application, a frequency dividing configuration (a desired frequency or a frequency dividing multiple corresponding to the functional clock) may be set for the frequency dividing circuit, so as to perform frequency dividing processing on a high-frequency clock to obtain a corresponding functional clock.

In terms of frequency division configuration of the frequency division circuit, the embodiment of the present application may determine the frequency division configuration of the frequency division circuit corresponding to each functional clock according to the clock frequency required by the functional module corresponding to each functional clock (i.e., the expected frequency of each functional clock); the frequency of the reference clock, the frequency of the high-frequency clock and the frequency of the reference clock are determined in a mode that the frequency of the reference clock is a common divisor of the frequencies of the plurality of functional clocks on the basis of the determination of the frequency of each functional clock; determining the frequency of the high-frequency clock in a mode of taking the frequency of the high-frequency clock as a preset multiple of the frequency of the reference clock; the frequency of the reference clock is determined in such a manner that the frequency of the reference clock is the same as the frequency of the reference clock.

As an alternative implementation, the frequency of the reference clock may be a common divisor of the frequencies of the plurality of functional clocks, and the frequencies of the functional clocks and the frequencies of the reference clocks are in a multiple relationship, and then the embodiments of the present application may set a frequency division configuration for the frequency division circuit corresponding to each functional clock according to the common divisor of the frequencies of the plurality of functional clocks as the frequency of the reference clock, the frequency of each functional clock and the frequency of the reference clock are in a multiple relationship, and the expected frequency of each functional clock. Furthermore, besides the multiple functional clocks meet the same phase, the frequencies of the functional clocks can be in a multiple relation or a non-multiple relation; for example, among the plurality of functional clocks, frequencies of partial functional clocks are in a multiple relation, and frequencies of partial functional clocks are in a non-multiple relation.

Further, the frequency of the reference clock may be the same as the frequency of the reference clock, and the frequency of the high-frequency clock is a preset multiple of the frequency of the reference clock (the preset multiple corresponds to a multiple of the frequency amplification circuit configuration); in one example, the frequency of the high-frequency clock may be 35 times the frequency of the reference clock, the frequency amplification circuit may multiply and amplify the reference clock to the high-frequency clock by a preset multiple of 35 times, and the frequency division circuit corresponding to the reference clock may divide the frequency of the high-frequency clock by the division multiple of 35 times to obtain the reference clock.

It can be seen that the inputs of the plurality of frequency dividing circuits are the same (i.e., each frequency dividing circuit inputs the high frequency clock), but the frequency of the clock output from each frequency dividing circuit is different, and the reference clock and the plurality of functional clocks output from the plurality of frequency dividing circuits need to be kept in phase with the input high frequency clock. As an alternative implementation, the embodiments of the present application may utilize a Phase-Locked Loop (PLL) principle to ensure that the plurality of frequency division circuits output a reference clock and a plurality of functional clocks with the same Phase, where a PLL (Phase Locked Loop) is a negative feedback control system that uses a voltage generated by Phase synchronization to tune a voltage-controlled oscillator to generate a target frequency.

In a further alternative implementation, fig. 4C is a diagram illustrating another structure example of the first clock generation logic, and in conjunction with fig. 4B and fig. 4C, the frequency amplification circuit 421 shown in fig. 4B may be the phase-locked loop 431 shown in fig. 4C, and the frequency division circuit 422 shown in fig. 4B may be the digital frequency division unit 432 shown in fig. 4C. The specific functions of the phase-locked loop 431 and the digital frequency-dividing units 432 can be referred to the related descriptions, and are not described herein again. For the sake of understanding, the relationship between the intermediate high frequency clock generated by the first clock generation logic with respect to the input reference clock, the output reference clock, and the functional clock, fig. 4D illustrates the output reference clock and 3 functional clocks of the first clock generation logic, and the corresponding waveform examples are exemplarily shown for reference.

In some further embodiments, the second clock generation logic may be designed in the chip to generate a clock for a third functional module, which may be a functional module using a different specific frequency from the second functional module described above. Based on this, the clock generated by the second clock generation logic and the clock generated by the first clock generation logic (e.g., the reference clock and the functional clock) may be in an asynchronous clock relationship. In a possible example, the third functional module corresponds to the functional module of the second case, for example, the second functional module and the third functional module both need to use a clock with a specific frequency based on the hard requirement, respectively, but the specific frequency used by the clock of the third functional module is different from the specific frequency used by the clock of the second functional module.

As an alternative implementation, fig. 5 is a diagram illustrating another example of a clock design of a chip, and in conjunction with fig. 3A and fig. 5, the chip shown in fig. 5 further includes: second clock generation logic 510 and functional module 520; the functional module 520 and the functional module 130 are both functional modules corresponding to the second case, and need to use a clock with a specific frequency based on the protocol, the standard or the hard requirement of the third IP, respectively, and the specific frequency used by the clock of the functional module 520 is different from the specific frequency used by the clock of the functional module 130. In the case where the first clock generation logic provides the functional clock 330 to the functional module 130, the second clock generation logic 510 may generate the clock 511 according to the specific frequency required by the functional module 520; and clock 511 is in an asynchronous clock relationship with the clock generated by the first clock generation logic. Thus, the second clock generation logic 510 can configure the clock 511 to the functional module 520 to satisfy the specific frequency of the clock required by the functional module 520 under the hard requirement. In the example of fig. 5, clock 511 does not have a fixed phase relationship with functional clocks 310, 320, and 330, i.e., an asynchronous clock relationship.

It can be seen that, when the clock requirements of the chip are divided into the first case, the second case, and the third case described above, the embodiment of the present application may consider a plurality of functional modules using different clock frequencies under various circumstances, and the embodiment of the present application may generate a plurality of in-phase functional clocks (belonging to synchronous clocks) with different frequencies through the first clock generation logic to meet the clock frequency using requirements of the plurality of functional modules, thereby reducing the number of asynchronous clocks in the chip.

It should be further noted that, the timing constraint of the signal needs to be performed in the case of clock crossing, and the timing constraint of the signal across the clock is generally divided into two types, one is not to perform timing check, and the other is to perform additional constraint on transmission delay separately. When extra constraint is performed on transmission delay at present, a synchronizer or an asynchronous First-in First-out (FIFO) buffer can be used for performing clock-crossing signal processing; however, as the chip manufacturing process enters the deep submicron era, the transmission delay caused by the cross-clock of the signals processed by the synchronizer or the asynchronous FIFO buffer memory has greater and greater influence on the chip performance, thereby seriously restricting the improvement of the chip performance; meanwhile, the design of the synchronizer needs to occupy a large amount of logic resources, which may result in an increase in chip area and power consumption. Based on this, the embodiment of the application further performs timing constraint design and clock signal crossing processing design for the chip.

In an embodiment of the present application, the reference clock generated by the first clock generation logic and the plurality of functional clocks may be defined in a clock group, and the clocks in a clock group need to satisfy the synchronous timing requirement. In clock constraining the clocks in a clock group, FIG. 6A illustrates an alternative method flow diagram for designing timing constraints, which may include the following steps with reference to FIG. 6A.

In step S610, timing constraint is performed according to the frequency of the functional clock when the design signal is transmitted between the functional clock and the reference clock.

For the functional clock and the reference clock in one clock group, when a signal is transmitted between the functional clock and the reference clock (for example, a signal is transmitted from one functional clock to the reference clock, or a signal is transmitted from the reference clock to one functional clock), since the frequency of the functional clock is a multiple of the frequency of the reference clock, the embodiment of the present application may design the signal between the functional clock and the reference clock to be timing constrained according to the frequency of the functional clock.

In step S611, when the design signal is transmitted between two functional clocks having no multiple relationship in frequency, timing constraint is performed according to the greatest common divisor of clock periods of the two functional clocks.

For two functional clocks in a clock group, the frequencies of the two functional clocks may or may not have a multiple relationship because the functional clocks do not necessarily have a multiple relationship in frequency. For two functional clocks that do not have a multiple relationship in frequency, if a signal is transmitted between the two functional clocks (e.g., a signal is transmitted from one functional clock to the other functional clock), embodiments of the present application may design the signal to be timing constrained by the greatest common divisor of the clock periods of the two functional clocks.

In step S612, when the design signal is transmitted between two functional clocks having a multiple relationship in frequency, timing constraint is performed based on the clock period of the functional clock having a fast frequency and the deviation and jitter between the two functional clocks.

For two functional clocks with multiple frequency relationship, if a signal is transmitted between the two functional clocks, in some embodiments, the embodiment of the present application may add the clock period of the functional clock with the faster frequency to the deviation and jitter between the two functional clocks to design the timing constraint of the signal.

In further embodiments, clocks generated by different clock generation logic may be defined as asynchronous clocks (e.g., first clock generation logic and second clock generation logic are different clock generation logic, and different second clock generation logic is different clock generation logic); for signals between two asynchronous clocks, embodiments of the present application may be designed not to perform timing checks.

In some further embodiments, the embodiments of the present application may further design a signal cross-clock processing logic for the chip, that is, design a processing logic for the cross-clock signal. As an alternative implementation, fig. 6B illustrates an alternative method flow diagram for designing cross-clock signal processing logic, which may include the following steps with reference to fig. 6B.

In step S620, if two clocks are generated by different clock generation logic, signals across the two clocks are designed to be processed synchronously in an asynchronous sequential processing manner.

The two clocks being generated by different clock generation logic may be two clocks generated by first and second clock generation logic, respectively, or two different second clock generation logic, etc. The two clocks are generated by different clock generation logics, and are asynchronous clocks, and signals crossing the asynchronous clocks can be designed according to the embodiment of the application, and synchronous processing is carried out on the signals according to an asynchronous time sequence processing mode.

In step S621, if the two clocks are asynchronous clocks generated by the same clock generation logic, signals crossing the two clocks are designed, and synchronous processing is performed in an asynchronous timing processing manner.

Two clocks are generated by the same clock generation logic, but the phase relationship of the two clocks is not fixed (for example, the phase relationship of the two clocks is not constrained), so that the two clocks are asynchronous clocks.

That is, if two clocks are asynchronous clocks generated by different clock generation logic or asynchronous clocks generated by the same clock generation logic, signals crossing the two clocks are designed and signal synchronization processing is performed in an asynchronous timing processing manner.

In step S622, if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a multiple relationship, the signals crossing the two clocks are designed and processed according to the synchronous signals.

Two clocks are generated by the same clock generation logic, and the phases of the two clocks are the same, and the frequencies of the two clocks are in a multiple relation (for example, an integer multiple relation), so that the two clocks are synchronous clocks. In some embodiments, two clocks of the same phase and frequency are produced by the same clock generation logic, for example: the reference clock and the functional clock generated by the first clock generation logic, or the two functional clocks with frequencies in a multiple relation generated by the first clock generation logic.

In step S623, if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a non-multiple relationship, the signals crossing the two clocks are designed to perform asynchronous timing processing by fixing the relative position relationship of the read pointer and the write pointer of the FIFO buffer.

The two clocks are generated by the same clock generation logic, the phases of the two clocks are the same, and the frequencies of the two clocks are in a non-multiple relation (for example, not in an integer multiple relation), so that the two clocks are synchronous clocks. In some embodiments, based on the characteristics of in-phase and different frequencies of two synchronous clocks, the embodiments of the present application may perform asynchronous timing processing on signals crossing the two clocks by fixing the relative position relationship of the read pointer and the write pointer of the FIFO buffer.

According to the clock design scheme of the chip provided by the embodiment of the application, the plurality of functional modules using different clock frequencies are uniformly configured to be provided with clocks by the first clock generation logic by analyzing the clock requirements of the functional modules; a plurality of functional clocks with the same phase and different frequencies are generated through the first clock generation logic, and the clocks are designed for the plurality of functional modules, so that the number of asynchronous clocks designed in a chip can be reduced, the negative influence of the asynchronous clocks on the performance, power consumption and area of the chip is reduced, and the difficulty of time sequence analysis of the chip is reduced. Meanwhile, the time sequence constraint workload of the asynchronous signals is reduced, and a foundation is provided for guaranteeing the time sequence constraint correctness of the asynchronous signals. Furthermore, on the basis of providing a plurality of in-phase and different-frequency functional clocks for the first functional module and the second functional module, the embodiment of the application provides a corresponding time sequence constraint design for the chip, so that the time sequence constraint correctness of signals in the chip can be guaranteed; and the processing logic design of the cross-clock signal is optimized, so that the effects of reducing the system delay of the chip and reducing the logic units can be achieved.

The clock design apparatus of the chip provided in the embodiments of the present application is described below, and the clock design apparatus of the chip described below may be regarded as a software apparatus that is required to be provided by a computer device for chip design to implement the clock design method provided in the embodiments of the present application. Such as software means required to be provided by chip design software run by a computer device. The following description may be referred to in correspondence with the above description.

As an alternative implementation, fig. 7 exemplarily shows an alternative block diagram of a clock designing apparatus, which is applicable to a computer device for chip design, and referring to fig. 7, the apparatus may include:

a clock generation logic design unit 711 for designing a first clock generation logic for providing clocks to a plurality of functional modules of a chip, the first clock generation logic being configured to generate a plurality of functional clocks having different frequencies in phase according to clock frequencies used by the plurality of functional modules;

a relation designing unit 712, configured to design correspondence between the plurality of functional clocks and the plurality of functional modules, where one functional clock corresponds to at least one functional module using the frequency of the functional clock.

In some embodiments, the plurality of functional modules comprises: a first functional module and a second functional module; the first functional module uses a clock with a frequency corresponding to the performance requirement of the first functional module, and the second functional module uses a clock with a specific frequency.

In some embodiments, the first clock generation logic configured to generate a plurality of functional clocks of different frequencies in phase according to the clock frequencies used by the plurality of functional modules comprises: and generating a plurality of functional clocks with same phase and different frequencies according to the clock frequencies used by the first functional module and the second functional module.

In some embodiments, the relationship designing unit 712, configured to design correspondence between the plurality of functional clocks and the plurality of functional modules, includes: designing a functional clock adapted to the clock frequency of the first functional module, and corresponding to the first functional module; and designing a functional clock adapted to the specific frequency, and corresponding to the second functional module.

In some embodiments, the second functional module uses a clock of a particular frequency based on hard requirements, or the second functional module has no clock requirement; and when the second functional module has no clock requirement, the clock with fixed specific frequency is used based on the performance requirement and the process condition of the whole chip.

In some further embodiments, the clock generation logic design unit 711 is further configured to design a second clock generation logic, where the second clock generation logic is configured to generate a clock for the third functional module, and the clock is in an asynchronous clock relationship with the clock generated by the first clock generation logic; the third functional module uses a clock with a specific frequency based on hard requirements, and the specific frequency used by the clock of the third functional module is different from the specific frequency used by the clock of the second functional module.

In some further embodiments, the clock generation logic design unit 711 is further configured to design the first clock generation logic to generate a reference clock that is in phase with the plurality of functional clocks.

In some embodiments, the clock generation logic design unit 711, the first clock generation logic for designing to provide clocks for the plurality of functional modules, includes:

designing a frequency amplification circuit, wherein the frequency amplification circuit is configured to perform frequency amplification processing on a reference clock to obtain a high-frequency clock;

designing a plurality of frequency dividing circuits connected to a frequency amplifying circuit, the plurality of frequency dividing circuits being configured to divide a high-frequency clock in accordance with respective frequency dividing configurations to obtain the reference clock and the plurality of functional clocks, respectively; the functional modules using the same clock frequency in the plurality of functional modules correspond to one frequency dividing circuit, and one frequency dividing circuit outputs one clock based on the frequency dividing configuration of the frequency dividing circuit and provides the clock to the corresponding functional module.

In some embodiments, the common divisor of the frequencies of the plurality of functional clocks is the frequency of the reference clock, the frequency of the reference clock is the same as the frequency of the reference clock, and the frequency of the high-frequency clock is a preset multiple of the frequency of the reference clock; the frequency of the functional clock is in a multiple relation or in a non-multiple relation.

In some further embodiments, the clock designing apparatus provided in this embodiment of the present application is further configured to:

when the design signal is transmitted between the functional clock and the reference clock, carrying out time sequence constraint according to the frequency of the functional clock;

when a design signal is transmitted between two functional clocks with frequencies not having a multiple relation, carrying out time sequence constraint according to the greatest common divisor of clock periods of the two functional clocks;

when a design signal is transmitted between two functional clocks with multiple frequency, timing constraint is carried out based on the clock period of the functional clock with fast frequency and the deviation and the jitter between the two functional clocks.

In some further embodiments, the clock designing apparatus provided in the embodiments of the present application is further configured to:

if the two clocks are asynchronous clocks generated by different clock generation logics or asynchronous clocks generated by the same clock generation logic, designing signals crossing the two clocks, and performing signal synchronous processing according to an asynchronous time sequence processing mode;

if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a multiple relation, designing signals spanning the two clocks and processing according to the synchronous signals;

if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a non-multiple relation, signals crossing the two clocks are designed to carry out asynchronous time sequence processing by fixing the relative position relation of a read pointer and a write pointer of the FIFO buffer.

The embodiment of the present application further provides a computer device for chip design, and the computer device may implement the clock design method provided by the embodiment of the present application by setting the clock design apparatus. In some embodiments, the computer device may include: at least one memory storing one or more computer-executable instructions and at least one processor invoking the one or more computer-executable instructions to perform a clock design method as provided by embodiments of the present application.

Embodiments of the present application also provide a storage medium, which may store one or more computer-executable instructions that, when executed, implement a clock design method as provided by embodiments of the present application.

Based on the clock design scheme of the chip provided by the embodiment of the application, the embodiment of the application can provide a designed corresponding chip product. The Chip provided by the embodiment of the present application is, for example, a System-on-a-Chip (SOC) Chip or the like. The following description may be referred to in correspondence with the foregoing description.

As an alternative implementation, fig. 8A exemplarily shows a structural example of a chip provided in an embodiment of the present application, and as shown in fig. 8A, the chip provided in the embodiment of the present application may include: a plurality of functional modules 810, and first clock generation logic 820, wherein the plurality of functional modules 810 use different clock frequencies.

In this embodiment, the first clock generation logic 820 is configured to generate a plurality of functional clocks with different in-phase frequencies according to the clock frequencies used by the plurality of functional modules; and providing the functional clocks to corresponding functional modules, wherein one functional clock corresponds to at least one functional module using the frequency of the functional clock.

For the description of the first clock generation logic 820 and the plurality of functional modules 810, reference may be made to the description of the corresponding parts, and the description will not be expanded here.

As a further alternative implementation, fig. 8B exemplarily shows another exemplary structure of the chip provided in the embodiment of the present application, and in conjunction with fig. 8A and fig. 8B, the plurality of functional modules 810 may include: the number of the first functional module 811 may be one or more than one, and the description of the first functional module 811 and the second functional module may refer to the description of the corresponding parts, and will not be expanded herein.

In fig. 8B, the first clock generation logic 820 may be specifically configured to generate a plurality of functional clocks with different frequencies in phase according to the clock frequencies used by the first functional module and the second functional module; the function clock corresponding to the first function module is provided to the first function module, and the function clock corresponding to the second function module is provided to the second function module.

In some embodiments, the functional clock adapted to the clock frequency of the first functional module is designed to have a corresponding relationship with the first functional module; the functional clock which is adapted to the specific frequency of the second functional module is designed to have a corresponding relation with the second functional module.

As an alternative implementation, the operation example of the chip structure shown in fig. 8B may refer to the description of the related parts, and will not be expanded here.

In further embodiments, the first clock generation logic 820 may also be configured to generate a reference clock that is in phase with the plurality of functional clocks.

The manner in which the first clock generation logic 820 generates the reference clock and the plurality of functional clocks may be referred to in the corresponding portions of the description above and will not be further described herein. Alternative structures for the first clock generation logic 820 may be found in the corresponding portions of the description above and will not be further described herein.

In some further embodiments, fig. 8C is a diagram illustrating another exemplary structure of a chip provided in an embodiment of the present application, and in conjunction with fig. 8B and fig. 8C, the chip provided in an embodiment of the present application may further include: a second clock generation logic 830 and a third functional module 840; the description of the third functional module 840 refers to the description of the corresponding parts, and is not expanded herein.

In this embodiment, the second clock generation logic 830 is configured to generate a clock for the third functional module, where the clock is in an asynchronous clock relationship with the clock generated by the first clock generation logic.

In some further embodiments, fig. 8D is a diagram schematically illustrating another example of the structure of the chip provided in the embodiment of the present application, and in conjunction with fig. 8C and fig. 8D, the chip provided in the embodiment of the present application may further include: a plurality of cross-clock processing logic 850.

The clock crossing processing logic is positioned between clock crossing functional modules and is used for acquiring signals crossing two clocks; if the two clocks are asynchronous clocks generated by different clock generation logics or asynchronous clocks generated by the same clock generation logic, performing signal synchronous processing on the signals according to an asynchronous time sequence processing mode; if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a multiple relation, processing the signals according to synchronous signals; and if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a non-multiple relation, performing asynchronous time sequence processing on the signals by fixing the relative position relation of a read pointer and a write pointer of the FIFO cache.

In some further embodiments, the chip provided in the embodiments of the present application may further include timing constraint logic. The timing constraint logic is used for acquiring signals; if the signal is transmitted between the functional clock and the reference clock, performing timing constraint according to the frequency of the functional clock; if the signal is transmitted between the two functional clocks with the frequency not in a multiple relation, carrying out time sequence constraint according to the greatest common divisor of the clock periods of the two functional clocks; if a signal is transmitted between two functional clocks having a multiple relationship in frequency, timing constraint is performed based on the clock period of the functional clock having a fast frequency, and the deviation and jitter between the two functional clocks.

The related contents of the cross-clock signal processing and the related contents of the timing constraints can be referred to the description of the corresponding parts, and are not expanded herein. In some embodiments, cross-clock signal processing logic and timing constraint logic may alternatively be implemented.

In an implementation example of a chip, fig. 9 exemplarily shows a diagram of an implementation example of a chip provided in an embodiment of the present application, and in conjunction with fig. 9, functional modules in the chip (e.g., an SOC chip) may include a high-speed serial PHY, a DDR PHY, a CPU, a bus 1, a bus 2, and the like. The high-speed serial PHY and the DDR PHY respectively use clocks with specific frequencies based on the hard requirements of a standard protocol, namely the high-speed serial PHY and the DDR PHY correspond to the functional modules of the second condition, and the clocks with different specific frequencies are used under the respective hard requirements; the clock frequencies of the CPU, the bus 1 and the bus 2 are mainly determined based on their performance requirements, i.e. the CPU, the bus 1 and the bus 2 correspond to the functional modules of the first case, and different clock frequencies are used under their respective performance requirements.

Under the condition that the clock frequencies used by the functional modules in the first case and the second case are considered in an overall mode, the clock frequencies of the CPU, the bus 1 and the bus 2 only need to consider the performance requirements of the clock frequencies, and do not need to be fixed at a specific frequency, so that overall planning can be carried out when the DDR PHY requires to use the clock with the specific frequency; the clock frequency of the high-speed serial PHY can be independently programmed because the clock frequency of the high-speed serial PHY has the requirement of specific frequency and is different from that of the DDR PHY. That is to say, under the concept provided by the embodiment of the present application, in the functional modules shown in fig. 9, the CPU, the bus 1, and the bus 2 may be regarded as an example of a first functional module, the DDR PHY may be regarded as an example of a second functional module, and the high-speed serial PHY may be regarded as an example of a third functional module.

As shown in fig. 9, clock generation logic 910 (an example of a first clock generation logic) produces clocks 911, 912, 913, and 914 at different frequencies in phase and provides clock 911 for bus 1 use, clock 912 for CPU use, clock 913 for bus 2 use, and clock 914 for DDR PHY use; meanwhile, the clock generation logic module 910 provides reference clocks to the bus 1, CPU, bus 2 and DDR PHY, respectively, where the reference clocks are provided in the functional modules for use mainly by the reduced FIFO buffer for aligning the clock phases of the functional modules, in this example, the clocks 911, 912, 913 and 914 all satisfy the same phase relationship with the reference clocks.

Further, as shown in fig. 9, a clock generation logic 920 (an example of a second clock generation logic) is also provided in the chip, and the clock generation logic 920 may generate a clock 921 and provide the clock to the high-speed serial PHY for use. Clock 921 is in asynchronous clock relationship with clocks 911, 912, 913, and 914.

Further, as shown in fig. 9, a plurality of clock-crossing processing logics, namely clock-crossing processing logics 931, 932, 933, 934 and 935, are further disposed in the chip. The clock crossing processing logic 931 is configured to process signals of the clock crossing 921 and the clock 911, and the clock crossing processing logic 931 may perform clock crossing processing by using an asynchronous FIFO buffer because the clock 921 and the clock 911 are asynchronous clocks. As shown in fig. 9, since the clocks 911, 912, 913, and 914 are all in phase with the reference clock, the cross-clock processing logic 932, 933, 934, and 935 can adopt an in-phase simplified FIFO buffer design to perform cross-clock processing of signals.

Further, the cross-clock processing logic 932, 933, 934, and 935 may additionally consider the relative delay differences of the read clock, the write clock, and the reference clock of the FIFO buffer when performing timing checking during physical implementation. For example, when calculating the setup time of the FIFO write pointer, the above-mentioned cross-clock processing logic requires that the setup time margin is greater than the relative delay size of the write clock and the reference clock; when calculating the establishment time of the FIFO read pointer, the establishment time margin is required to be larger than the relative delay size of the read clock and the reference clock; when calculating the setup time of FIFO read data, the setup time margin is required to be greater than a certain value, which may be the relative delay magnitude of the read clock and the reference clock, plus the relative delay magnitude of the write clock and the reference clock.

The embodiment of the application also provides electronic equipment, such as server equipment or terminal equipment. The electronic device can comprise the chip provided by the embodiment of the application.

While various embodiments have been described above in connection with what are presently considered to be the embodiments of the disclosure, the various alternatives described in the various embodiments can be readily combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered to be the disclosed and disclosed embodiments of the disclosure.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and it is intended that the scope of the present disclosure be defined by the appended claims.

Claims

1. A clock design method of a chip is characterized by comprising the following steps:

2. The method of claim 1, wherein the plurality of functional modules comprises: a first functional module and a second functional module; the first functional module uses a clock with a frequency corresponding to the performance requirement of the first functional module, and the second functional module uses a clock with a specific frequency.

3. The method of claim 2, wherein the first clock generation logic configured to generate a plurality of functional clocks of different frequencies in phase according to the clock frequency used by the plurality of functional modules comprises: generating a plurality of functional clocks with same phase and different frequencies according to the clock frequencies used by the first functional module and the second functional module;

the designing of the correspondence between the plurality of functional clocks and the plurality of functional modules includes: designing a functional clock adapted to the clock frequency of the first functional module, and corresponding to the first functional module; and designing a functional clock adapted to the specific frequency, and corresponding to the second functional module.

4. The method of claim 2, wherein the second functional module uses a clock of a specific frequency based on hard requirements or the second functional module has no clock requirements; and when the second functional module has no clock requirement, the clock with fixed specific frequency is used based on the performance requirement and the process condition of the whole chip.

5. The method of claim 4, further comprising:

designing a second clock generation logic, wherein the second clock generation logic is used for generating a clock for the third functional module, and the clock generated by the first clock generation logic are in an asynchronous clock relationship; the third functional module uses a clock with a specific frequency based on hard requirements, and the specific frequency used by the clock of the third functional module is different from the specific frequency used by the clock of the second functional module.

6. The method of claim 1, further comprising: designing first clock generation logic to generate a reference clock that is in phase with the plurality of functional clocks.

7. The method of claim 6, wherein the first clock generation logic configured to clock the plurality of functional modules comprises:

8. The method of claim 7, wherein the common divisor of the frequencies of the plurality of functional clocks is the frequency of the reference clock, the frequency of the reference clock is the same as the frequency of the reference clock, and the frequency of the high-frequency clock is a preset multiple of the frequency of the reference clock; the frequency of the functional clock is in a multiple relation or in a non-multiple relation.

9. The method according to any one of claims 1-8, further comprising:

10. The method according to any one of claims 1-8, further comprising:

11. A chip, comprising: a plurality of functional modules, and first clock generation logic;

12. The chip of claim 11, wherein the plurality of functional modules comprises a first functional module and a second functional module; the first functional module uses a clock with a frequency corresponding to the performance requirement of the first functional module, and the second functional module uses a clock with a specific frequency.

13. The chip of claim 12, wherein the first clock generation logic to generate a plurality of functional clocks of different frequencies in phase based on the clock frequencies used by the plurality of functional modules comprises: generating a plurality of in-phase functional clocks with different frequencies according to the clock frequencies used by the first functional module and the second functional module;

the first clock generation logic configured to provide the functional clock to the corresponding functional module comprises: providing the functional clock corresponding to the first functional module, and providing the functional clock corresponding to the second functional module;

the functional clock which is adapted to the clock frequency of the first functional module is designed to have a corresponding relation with the first functional module; the functional clock which is adapted to the specific frequency of the second functional module is designed to have a corresponding relation with the second functional module.

14. The chip of claim 12, wherein the second functional module uses a clock of a specific frequency based on hard requirements or the second functional module has no clock requirements; and when the second functional module has no clock requirement, a clock with fixed specific frequency is used based on the performance requirement and the process condition of the whole chip.

15. The chip of claim 14, further comprising:

a second clock generation logic, the second clock generation logic configured to generate a clock for the third functional module, the clock being in an asynchronous clock relationship with the clock generated by the first clock generation logic; the third functional module uses a clock with a specific frequency based on hard requirements, and the specific frequency used by the clock of the third functional module is different from the specific frequency used by the clock of the second functional module.

16. The chip of claim 11, wherein the first clock generation logic is further configured to generate a reference clock that is in phase with the plurality of functional clocks.

17. The chip of claim 16, wherein the first clock generation logic comprises:

the frequency amplification circuit is used for carrying out frequency amplification processing on the reference clock to obtain a high-frequency clock;

the frequency amplifying circuit is used for amplifying a high-frequency clock to obtain a reference clock and a plurality of functional clocks; the functional modules using the same clock frequency in the plurality of functional modules correspond to one frequency dividing circuit, and one frequency dividing circuit outputs one clock based on the frequency dividing configuration of the frequency dividing circuit and provides the clock to the corresponding functional module.

18. The chip of claim 17, wherein a common divisor of the frequencies of the plurality of functional clocks is a frequency of the reference clock, the frequency of the reference clock is the same as the frequency of the reference clock, and the frequency of the high-frequency clock is a preset multiple of the frequency of the reference clock; the frequency of the functional clock is in a multiple relation or in a non-multiple relation.

19. The chip of any one of claims 11-18, further comprising: a plurality of cross-clock processing logic and/or timing constraint logic;

the clock crossing processing logic is positioned between the clock crossing functional modules and used for acquiring signals crossing two clocks; if the two clocks are asynchronous clocks generated by different clock generation logics or asynchronous clocks generated by the same clock generation logic, performing signal synchronous processing on the signals according to an asynchronous time sequence processing mode; if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a multiple relation, processing the signals according to synchronous signals; if the two clocks are synchronous clocks generated by the same clock generation logic and the frequencies of the two clocks are in a non-multiple relation, the signals are subjected to asynchronous time sequence processing by fixing the relative position relation of a read pointer and a write pointer of the FIFO cache;

the timing constraint logic is used for acquiring signals; if the signal is transmitted between the functional clock and the reference clock, performing timing constraint according to the frequency of the functional clock; if the signal is transmitted between the two functional clocks with the frequency not in a multiple relation, carrying out time sequence constraint according to the greatest common divisor of the clock periods of the two functional clocks; if a signal is transmitted between two functional clocks having a multiple relationship in frequency, timing constraint is performed based on the clock period of the functional clock having a fast frequency, and the deviation and jitter between the two functional clocks.

20. A clock design apparatus, comprising:

21. A computer device comprising at least one memory and at least one processor, the at least one memory storing one or more computer-executable instructions, the at least one processor invoking the one or more computer-executable instructions to perform the clock design method for the chip of any of claims 1-10.

22. A storage medium storing one or more computer-executable instructions that, when executed, implement a clock design method for a chip according to any one of claims 1-10.

23. An electronic device comprising a chip according to any of claims 11-19.