CN106886210A - Based on the priming system timing sequence testing device that sequence triggering is taken pictures - Google Patents

Based on the priming system timing sequence testing device that sequence triggering is taken pictures Download PDF

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Publication number
CN106886210A
CN106886210A CN201710005475.3A CN201710005475A CN106886210A CN 106886210 A CN106886210 A CN 106886210A CN 201710005475 A CN201710005475 A CN 201710005475A CN 106886210 A CN106886210 A CN 106886210A
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module
clk
port
timing
timer
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CN106886210B (en
Inventor
叶绍凯
张磊
李妍妍
朱榕
李慧
赵娜
李辉
何波
高飞
赵民
江思荣
段然
袁心成
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Beijing Aerospace Automatic Control Research Institute
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Beijing Aerospace Automatic Control Research Institute
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00—Testing or monitoring of control systems or parts thereof
    • G05B23/02—Electric testing or monitoring
    • G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
    • G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
    • G05B23/0221—Preprocessing measurements, e.g. data collection rate adjustment; Standardization of measurements; Time series or signal analysis, e.g. frequency analysis or wavelets; Trustworthiness of measurements; Indexes therefor; Measurements using easily measured parameters to estimate parameters difficult to measure; Virtual sensor creation; De-noising; Sensor fusion; Unconventional preprocessing inherently present in specific fault detection methods like PCA-based methods

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Disclose the priming system timing sequence testing device taken pictures based on sequence triggering.Taken pictures sampling module and the state change that compares control logic module parallel monitoring priming system time-ordered measurement port by port input filter module, port, if the current port state of time-ordered measurement port is different from last time port status, then latch the timers value of Timer module, by timers value and current port state write-in FIFO memory module, and the last time port status deposited in register module are updated with current port state；Compensation is filtered by the clock frequency of clock frequency division module adjustment time-ordered measurement port, by port input filter module, the certainty of measurement of priming system sequential time measurement device can be arbitrarily adjusted；By the timing bit wide for adjusting Timer module, it is possible to achieve timing length requirement expected from system.Priming system timing sequence testing device small volume of the invention, fast test, easily high precision, extension, can be directly integrated in airborne equipment.

Description

Initiating explosive device time sequence testing device based on sequence triggering photographing
Technical Field
The invention relates to missile and carrier rocket control system equipment design, in particular to an initiating explosive device time sequence testing device based on sequence trigger photographing.
Background
The background of the related art of the present invention will be described below, but the description does not necessarily constitute the prior art of the present invention.
The initiating explosive device is a miniaturized sensitive detonation energy source and is widely applied to military projects such as conventional weapon ammunition, strategic missile, nuclear weapon and aerospace system. The initiating explosive device is controlled to be ignited, and the power is controlled to be switched on and applied to the initiating explosive device loop through a relay switch or other switches. The initiating explosive device time sequence generally guides the control sequence of initiating explosive devices which need to be detonated in sequence in the launching and flying processes of a bomb weapon and a carrier rocket.
The initiating explosive device time sequence control has the effect of lifting the weight in a missile and carrier rocket system and influences the success or failure of flight, so that the initiating explosive device and a control circuit thereof need to be tested before the missile and carrier rocket launch in the test control and flight process, the former is used for quickly and accurately determining whether an initiating explosive device channel meets the launching requirement, and the latter is mainly used for flight data analysis.
The initiating explosive device control sequence is generally a switching value with a specific time sequence and a pulse width (e.g. 100ms, 200ms), and the main tested information is the start time, the end time and the sequence width of the sequence. In a general detection method, a switching value signal (generally, a square wave signal) is detected by a preprocessing circuit, and then the square wave signal is subjected to time information detection. The traditional detection mode is that signal preprocessing is firstly realized on a bullet (arrow), and then the bullet (arrow) is sent to ground test system equipment for testing. The ground test mode is as follows: the ground data transmission control module scans (gates one path of time sequence once) the popup preprocessing result, if a signal exists, the signal is gated and sent to the ground time measuring and frequency measuring module, and then the measurement of the starting time, the ending time and the width of the time sequence is completed.
The main defects of the traditional test method are as follows: the method has the advantages that the number of the bullet (arrow) and ground devices for realizing attachment of the test function is large, the size is large, and the system expansion is complex along with the increase of the number of the initiating explosive devices in the time sequence; the test parallelism is not high, only one path can be tested at one time through scanning and selecting tests, the test efficiency is low, and the real-time performance is not high; and thirdly, due to the fact that the test system is connected with an earth wire (arrow) and a ground wire, the test system is complex in structure, the frequency of periodic scanning sampling is not high, the test precision is not high, and the time is about 50 ms.
Disclosure of Invention
The invention aims to provide an initiating explosive device time sequence testing device based on sequence triggering photographing, which can be directly integrated in missile-borne equipment, has small volume, high testing speed and high precision, is easy to expand, and can effectively improve the testing performance of the time sequence of the initiating explosive device of a missile and a carrier rocket.
The invention relates to an initiating explosive device time sequence testing device based on sequence triggering photographing, which comprises: the device comprises a port input filtering module, a port photographing and sampling module, a comparison control logic module, a register module, a timer module, an FIFO write logic module, an FIFO memory module, a clock frequency division module and a read-write control module; wherein,
the read-write control module receives an operation instruction input from the outside; the clock frequency division module divides the input clock Clk _ In into at least two clocks according to an external operation instruction; the at least two clocks comprise Scan _ Clk and Sys _ Clk, the Scan _ Clk is output to the port input filtering module, and the Sys _ Clk is output to other modules except the port input filtering module of the initiating explosive device time sequence testing device;
the port input filtering module filters the time sequence of each time sequence measuring port and outputs the time sequence to the port photographing sampling module, and the port photographing sampling module acquires the current port state of the time sequence measuring port in parallel and sends the current port state to the comparison control logic module;
after receiving the current port state of the time sequence measuring port, the comparison control logic module inquires the last port state of the time sequence measuring port registered in the register module; if the current port state of the time sequence measuring port is different from the last port state, generating a latch signal, and sending the latch signal and the current port state of the time sequence measuring port to an FIFO write logic module;
after receiving the latch signal, the FIFO write logic module latches the timer value of the timer module, writes the timer value and the current port state into the FIFO memory module, and updates the last port state registered in the register module by using the current port state of the initiating explosive device time sequence measurement port.
Preferably, the clock frequency division module adopts counting frequency division; the clock phases of Clk _ In, Scan _ Clk, and Sys _ Clk are the same.
Preferably, the port input filtering module adopts a timing filtering method; if the current port state of the time sequence measurement port is different from the last port state, the control module starts a filtering counter based on Scan _ Clk:
the initial value of the filtering counter is 0; when the count value of the filter counter does not reach the filter set value, the port input filter module filters the port state change of the time sequence measurement port; and when the count value of the filtering counter reaches a filtering set value, the port input filtering module outputs the current port state of the time sequence measuring port.
Preferably, the timer module takes Sys _ Clk as a timer clock source; the timing bit width M of the timer module satisfies the following relation:
in the formula, L is a timing length and the unit is h; t isshortIs the timing period of Sys _ Clk, and the unit is mus;representing an ceiling function.
Preferably, the at least two clocks further comprise: syn _ Clk _ In, and the timing period of Syn _ Clk _ In is greater than the timing period of Sys _ Clk;
the timer module comprises two timers, wherein one timer takes Syn _ Clk _ In as a timer clock source and is used for high-order byte coarse timing, and the other timer takes Sys _ Clk as a timer clock source and is used for low-order byte fine timing;
the initial timing values of Syn _ Clk _ In and Sys _ Clk are 0; when the effective timing edge of the Syn _ Clk _ In does not arrive, the Sys _ Clk clock carries out low-order precise timing, when the effective timing edge of the Syn _ Clk _ In arrives, the low-order precise timing value is clear of 0, and the high-order rough timing value is added with 1.
Preferably, the timing bit width M of the timer module satisfies the following relationship:
M＝M1+M2
in the formula, L is a timing length and the unit is h; m1Timer bit width, M, for Syn _ Clk _ In2A timer bit width of Sys _ Clk; t islongThe period of Syn _ Clk _ In is given as s; t isshortIs the period of Sys _ Clk, in mus; delta1The timing allowance of Syn _ Clk _ In is s; delta2Is the timing margin of Sys _ Clk in mus;representing an ceiling function.
Preferably, the FIFO write logic module comprises: a bit width conversion unit and a FIFO write controller;
after receiving the latch signal, the bit width conversion unit latches the timer value of the timer module, splices the timer value corresponding to all the time sequence measurement ports and the current port state into y bytes according to the storage bit width of the FIFO memory module, and sends the y bytes to the FIFO write controller; y is a positive integer, and the bit width of each byte is equal to the storage bit width of the FIFO memory module; and the FIFO write controller writes the received y bytes into an FIFO memory module, and updates the last port state registered in the register module by using the current port state of the initiating explosive device time sequence measurement port.
Preferably, the bit width conversion unit is further configured to: when (N + M) is not an integral multiple of Q, high-order complement 0 is carried out before splicing, so that (N + M) is an integral multiple of Q; wherein, N is the time sequence path number, M is the timing bit width of the timer module, and Q is the storage bit width of the FIFO memory module.
Preferably, the FIFO write controller comprises a Moore type FIFO write state machine and an (N + M) bit shift buffer register.
According to the initiating explosive device time sequence testing device based on sequence triggering photographing, the state change of the initiating explosive device time sequence measuring port is monitored in parallel through the port input filtering module, the port photographing sampling module and the comparison control logic module, and if the current port state of the time sequence measuring port is the same as the last port state, port monitoring is continued; otherwise, latching the timer value of the timer module, writing the timer value and the current port state into the FIFO memory module, and updating the last port state registered in the register module by using the current port state of the initiating explosive device time sequence measurement port; the clock frequency of the time sequence measuring port is adjusted through the clock frequency division module, and the frequency is input into the filtering module through the port to carry out filtering compensation, so that the measuring precision of the initiating explosive device time sequence time measuring device can be adjusted at will; the expected timing length requirement of the system can be realized by adjusting the timing bit width of the timer module. The initiating explosive device time sequence testing device is small in size, fast in testing, high in precision and easy to expand, and can be directly integrated into the missile-borne equipment.
Drawings
The features and advantages of the present invention will become more readily appreciated from the detailed description section provided below with reference to the drawings, in which:
FIG. 1 is a schematic structural diagram of an initiating explosive device timing testing device according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of the state transitions of the FIFO write controller in the preferred embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The description of the exemplary embodiments is for purposes of illustration only and is not intended to limit the invention, its application, or uses.
As shown in fig. 1, the initiating explosive device timing sequence testing apparatus based on sequence triggered shooting of the present invention includes: the device comprises a port input filtering module, a port photographing and sampling module, a comparison control logic module, a register module, a timer module, an FIFO write logic module, an FIFO memory module, a clock frequency division module and a read-write control module; wherein,
the read-write control module receives an operation instruction input from the outside; the clock frequency division module divides the input clock Clk _ In into at least two clocks according to an external operation instruction; the at least two clocks comprise Scan _ Clk and Sys _ Clk, the Scan _ Clk is output to the port input filtering module, and the Sys _ Clk is output to other modules except the port input filtering module;
the port input filtering module filters the time sequence of each time sequence measuring port and outputs the time sequence to the port photographing sampling module, and the port photographing sampling module acquires the current port state of the time sequence measuring port in parallel and sends the current port state to the comparison control logic module;
after receiving the current port state of the timing measurement port, the comparison control logic module queries the last port state of the timing measurement port registered in the register module, such as P _ Data0 in fig. 1; if the current port state P _ Data1 of the time sequence measurement port is different from the last port state, generating a latch signal, and sending the latch signal and the current port state of the time sequence measurement port to an FIFO write logic module;
after receiving the latch signal, the FIFO write logic module latches a timer value of the timer module, such as T _ Data in fig. 1, writes the timer value and the current port state into the FIFO memory module, and updates the last port state registered in the register module with the current port state of the initiating explosive device timing measurement port.
The invention can monitor the state change of a plurality of initiating explosive device time sequence measuring ports in parallel, and the time sequence path number can be selected according to the total requirements of register resources, clock resources and combinational logic resources which need to be consumed. In order to improve the measurement stability and reliability of the initiating explosive device timing test device, when the timing path number is set, the initiating explosive device timing test device can be allowed to leave a certain data margin, for example, at least 20% of the data margin.
The clock frequency division module can adopt a counting frequency division mode. For example, a minus counter is adopted, and the upper computer rewrites the value of the counter through the read-write control module, so that the multi-path frequency division of the input clock Clk _ In is realized, and the clocks with the same phase and different frequencies used by each functional module In the initiating explosive device time sequence testing device are formed. The clock frequency of the time sequence measuring port is adjusted through the clock frequency division module, and the measuring precision of the initiating explosive device time sequence testing device can be adjusted and adjusted at will.
The higher the Sys _ Clk frequency, the higher the measurement accuracy, but the excessive frequency not only increases the resource consumption of the device, but also affects the stability of data reading. Therefore, a reliable crystal oscillator with low frequency can be selected as much as possible under the condition of meeting the requirements of system test precision and data reading speed: in the aspect of test precision: assuming that the Sys _ Clk clock period is T1, if the timing test accuracy is required to be not less than 0.5ms, the test data generation time (i.e., "timer module" clocks clock period T1, plus "timer module" time locking period (including comparison determination time before locking) (n × T1), plus write FIFO time (m × T1)) should be less than 0.5ms, i.e., T1+ n × T1+ m × T1 ═ 1+ n + m) × T1 is less than 0.5ms, in this example, n is 2, m is 20, so T1 is less than 0.5/23ms, i.e., the frequency is higher than 46 kHz; secondly, in terms of data access speed: if the writing time of the initiating explosive device test data (in this example, 2T 1 cycles are required for writing one byte into the FIFO) is slightly higher than the time for the system to read the data (i.e. read the FIFO data), and the time for the system to access the test data is 4us, then 2 × T1 is less than 4us, and then T1 is less than 2 us. And (6) integrating the first step and the second step, and reserving a certain margin, wherein 1MHz active crystal oscillator can be selected, namely T1 is 1 us.
The smaller the cycle of Scan _ Clk, the higher the test resolution of the initiating explosive device timing test apparatus, but the smaller the cycle, the higher the resource consumption of the apparatus, and the stability of data reading may also be reduced. The period of Scan _ Clk should be determined according to the timing test resolution requirement. For example, if the timing test resolution is required to be not less than 10us, the Scan _ Clk period should be less than 10 us.
The Clk _ In period should not be greater than min { Sys _ Clk period, Scan _ Clk period, other clock periods }, and considering requirements for reducing logic resource consumption, uniform type selection of components, device maturity, and the like, the Clk _ In period may be set to have the same clock periods as Clk _ In, Scan _ Clk, and Sys _ Clk, for example, all set to 1us, that is, an active crystal oscillator of 1MHz is selected as an external clock input of the programmable logic device.
In some embodiments, the port input filtering module employs a timed filtering method. If the current port state of the time sequence measurement port is different from the last port state, the control module starts a filtering counter based on Scan _ Clk: the initial value of the filtering counter is 0; when the count value of the filter counter does not reach the filter set value, the port input filter module filters the port state change of the time sequence measurement port; and when the count value of the filtering counter reaches a filtering set value, the port input filtering module outputs the current port state of the time sequence measuring port.
For example, the filtering counter has a bit width of 8, an initial value of 0, and a clock of Scan _ Clk (period T1), and [0, (2) can be implemented8-1)×T1]Filtering for a duration within the range, in this example, the selected filtering duration is 127us (corresponding to a count of 127)). In each sampling period of Scan _ Clk, an exclusive OR judgment method is adopted, and when the port state is found (and' last time: (are)Initial) port state "ratio, the same below) change, a filtering counter is started, when the counter value reaches 127, the port state change is confirmed, and the port state is output; if the counter value does not reach 127, the port state change disappears, the change is filtered out, and the original output state is maintained.
The timer module may only use Sys _ Clk as the timer clock source. The timing precision of the timer module can be adjusted at will by adjusting the timing period of the Sys _ Clk; by adjusting the timing bit width of the Sys _ Clk, the timing length requirement expected by the system can be achieved. The timing bit width M of the timer module satisfies the following relation:
in the formula, L is a timing length and the unit is h; t isshortIs the timing period of Sys _ Clk, and the unit is mus;representing an ceiling function.
In the present invention, the at least two clocks formed by the clock dividing module may further include: syn _ Clk _ In, and the timing period of Syn _ Clk _ In is greater than the timing period of Sys _ Clk. The timer module comprises two timers, wherein one timer uses Syn _ Clk _ In as a timer clock source for coarse timing of high-order bytes, and the other timer uses Sys _ Clk as a timer clock source for fine timing of low-order bytes. The initial timing values of Syn _ Clk _ In and Sys _ Clk are 0; when the effective timing edge of the Syn _ Clk _ In does not arrive, the Sys _ Clk clock carries out low-order precise timing, when the effective timing edge of the Syn _ Clk _ In arrives, the low-order precise timing value is clear of 0, and the high-order rough timing value is added with 1. The Syn _ Clk _ In is used for carrying out high-order byte coarse timing, the Sys _ Clk is used for carrying out low-order byte fine timing, and the timing precision of the timer module can be adjusted at will by adjusting the timing periods of the Syn _ Clk _ In and the Sys _ Clk; by adjusting the timing bit width of the Syn _ Clk _ In and the Sys _ Clk, the expected timing length requirement of the system can be realized. Preferably, the timing bit width M of the timer module satisfies the following relationship:
M＝M1+M2
in the formula, L is a timing length and the unit is h; m1Timer bit width, M, for Syn _ Clk _ In2A timer bit width of Sys _ Clk; t islongThe period of Syn _ Clk _ In is given as s; t isshortIs the period of Sys _ Clk, in mus; delta1The timing allowance of Syn _ Clk _ In is s; delta2Is the timing margin of Sys _ Clk in mus;representing an ceiling function.
In the preferred embodiment shown in fig. 1, the FIFO write logic block comprises: a bit width conversion unit and a FIFO write controller; after receiving the latch signal, the bit width conversion unit latches the timer value of the timer module, splices the timer values corresponding to all the time sequence measurement ports and the current port state into y bytes according to the storage bit width Q of the FIFO memory module, and sends the y bytes to the FIFO write controller; y is a positive integer, and the bit width of each byte is equal to the storage bit width Q of the FIFO memory module; and the FIFO write controller writes the received y bytes into the FIFO memory module and updates the last registered port state in the register module by using the current port state of the initiating explosive device time sequence measurement port.
For example, when N + M is 72 and the storage bit width is 8, the timer values corresponding to all timing measurement ports and every 8 bits of the current port state are taken as a group to be used as a Byte, the group is spliced into 9 bytes, each Byte is sequentially marked as Byte0, Byte1, … … and Byte8 from the lower bit to the upper bit, and the Byte is sent to the FIFO write controller after splicing is completed.
When (N + M) is not an integer multiple of Q, data concatenation cannot be performed as described above. Based on this, the bit-width conversion unit may be further configured to: when (N + M) is not an integral multiple of Q, high-order complement 0 is carried out before splicing, so that (N + M) is an integral multiple of Q; wherein, N is the time sequence path number, and M is the timing bit width of the timer module. For example, when N + M is 70 and the storage bit width is 8, the high order bits are supplemented with 2 bits "0", 72 bits are spliced, each 8 bits is a group as one Byte, 9 bytes can be formed, each Byte is sequentially marked as Byte0, Byte1, … … and Byte8 from the low order bit to the high order bit), and the spliced bytes are sent to the FIFO write controller.
The FIFO write controller may comprise a Moore type FIFO write state machine and an (N + M) bit shift buffer register. FIG. 2 is a state transition diagram of a FIFO write controller according to the preferred embodiment of the present invention, wherein the FIFO write controller comprises a Moore FIFO write state machine and a 72-bit shift buffer register. Moore FIFO write state machine, divided into 19 states, specified as follows:
ST0 — initial state after power-on reset (Rst _ In);
when the ready signal is inactive, indicating that the data is invalid, set (where Wr _ En is output half a clock cycle later than Lock, the same applies):
when the ready signal is active, set:
ST 1-set the following state (signals not listed remain the previous state, the same below):
ST 2-set the following status:
ST 3-set the following status:
ST 4-set the following status:
ST 5-set the following status:
ST 6-set the following status:
ST 7-set the following status:
ST 8-set the following status:
ST 9-set the following status:
ST 10-set the following status:
ST 11-set the following status:
ST 12-set the following status:
ST 13-set the following status:
ST 14-set the following status:
ST 15-set the following status:
ST 16-set the following status:
ST 17-set the following status:
serial number Signal name Signal state Remarks for note
1) Wr_En Invalidation FIFO write control signal
2) Scan_En Is effective Port shooting sampling enabling signal
3) next_state ST0 Next state
ST _ Other-the following state is set:
when the Lock signal is valid, the 72-bit shift buffer register locks the Data output by the bit width conversion unit, and the current port state Data "P _ Data 1" part in the locked Data is simultaneously sent out as the last port state for the comparison control logic module to inquire. When Shift _ En is active, Shift is performed: byte0 → Byte1 → Byte2 → Byte3 → Byte4 → Byte5 → Byte6 → Byte7 → Byte8 → Byte 0.
If the programmable device resources are sufficient, the IP of the general FIFO can be called in the initiating explosive device real-time sequence testing device or the FIFO memory can be designed according to the FIFO working principle. Of course, an external FIFO memory chip can also be adopted, the design is simple, and the requirement on the resources of the programmable device is low.
In the technology of the initiating explosive device timing testing device of the present invention, those skilled in the art can expand other logic according to actual requirements, as shown in fig. 1, which is not described in detail in the present invention.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the specific embodiments described and illustrated in detail herein, and that various changes may be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims (9)

1. Initiating explosive device time sequence testing arrangement based on sequence trigger is shot, its characterized in that includes: the device comprises a port input filtering module, a port photographing and sampling module, a comparison control logic module, a register module, a timer module, an FIFO write logic module, an FIFO memory module, a clock frequency division module and a read-write control module; wherein,
the read-write control module receives an operation instruction input from the outside; the clock frequency division module divides the input clock Clk _ In into at least two clocks according to an external operation instruction; the at least two clocks comprise Scan _ Clk and Sys _ Clk, the Scan _ Clk is output to the port input filtering module, and the Sys _ Clk is output to other modules except the port input filtering module of the initiating explosive device time sequence testing device;
the port input filtering module filters the time sequence of each time sequence measuring port and outputs the time sequence to the port photographing sampling module, and the port photographing sampling module acquires the current port state of the time sequence measuring port in parallel and sends the current port state to the comparison control logic module;
after receiving the current port state of the time sequence measuring port, the comparison control logic module inquires the last port state of the time sequence measuring port registered in the register module; if the current port state of the time sequence measuring port is different from the last port state, generating a latch signal, and sending the latch signal and the current port state of the time sequence measuring port to an FIFO write logic module;
after receiving the latch signal, the FIFO write logic module latches the timer value of the timer module, writes the timer value and the current port state into the FIFO memory module, and updates the last port state registered in the register module by using the current port state of the initiating explosive device time sequence measurement port.
2. The initiating explosive device timing test device as claimed in claim 1, wherein the clock frequency division module adopts counting frequency division; the clock phases of Clk _ In, Scan _ Clk, and Sys _ Clk are the same.
3. The initiating explosive device timing sequence testing device as claimed in claim 1, wherein the port input filtering module adopts a timing filtering method; if the current port state of the time sequence measurement port is different from the last port state, the control module starts a filtering counter based on Scan _ Clk:
the initial value of the filtering counter is 0; when the count value of the filter counter does not reach the filter set value, the port input filter module filters the port state change of the time sequence measurement port; and when the count value of the filtering counter reaches a filtering set value, the port input filtering module outputs the current port state of the time sequence measuring port.
4. The initiating explosive device timing testing device as claimed in claim 1, wherein the timer module uses Sys _ Clk as a timer clock source; the timing bit width M of the timer module satisfies the following relation:
2 E - 1 = L × 3600000000 T s h o r t + 1
in the formula, L is a timing length and the unit is h; t isshortIs the timing period of Sys _ Clk, and the unit is mus;representing an ceiling function.
5. The initiating explosive device timing testing apparatus according to claim 1, wherein the at least two clocks further comprise: syn _ Clk _ In, and the timing period of Syn _ Clk _ In is greater than the timing period of Sys _ Clk; the timer module comprises two timers, wherein one timer takes Syn _ Clk _ In as a timer clock source and is used for high-order byte coarse timing, and the other timer takes Sys _ Clk as a timer clock source and is used for low-order byte fine timing;
the initial timing values of Syn _ Clk _ In and Sys _ Clk are 0; when the effective timing edge of the Syn _ Clk _ In does not arrive, the Sys _ Clk clock carries out low-order precise timing, when the effective timing edge of the Syn _ Clk _ In arrives, the low-order precise timing value is clear of 0, and the high-order rough timing value is added with 1.
6. The initiating explosive device timing sequence testing device as claimed in claim 5, wherein the timing bit width M of the timer module satisfies the following relationship:
M 2 = [ log 2 ( T l o n g × 10 6 + Δ 1 T s h o r t ) ] , Δ 2 T l o n g × 10 6 ≥ 20 %
M 1 = [ log 2 ( L × 3600 + Δ 2 T l o n g ) ] , Δ 1 L × 3600 ≥ 20 %
M＝M1+M2
in the formula, L is a timing length and the unit is h; m1Timer bit width, M, for Syn _ Clk _ In2A timer bit width of Sys _ Clk; t islongThe period of Syn _ Clk _ In is given as s; t isshortIs the period of Sys _ Clk, in mus; delta1The timing allowance of Syn _ Clk _ In is s; delta2Is the timing margin of Sys _ Clk in mus;representing an ceiling function.
7. The initiating explosive device timing testing apparatus according to claim 1, wherein the FIFO write logic module comprises: a bit width conversion unit and a FIFO write controller;
after receiving the latch signal, the bit width conversion unit latches the timer value of the timer module, splices the timer value corresponding to all the time sequence measurement ports and the current port state into y bytes according to the storage bit width of the FIFO memory module, and sends the y bytes to the FIFO write controller; y is a positive integer, and the bit width of each byte is equal to the storage bit width of the FIFO memory module;
and the FIFO write controller writes the received y bytes into an FIFO memory module, and updates the last port state registered in the register module by using the current port state of the initiating explosive device time sequence measurement port.
8. The initiating explosive device timing testing apparatus according to claim 7, wherein the bit width conversion unit is further configured to:
when (N + M) is not an integral multiple of Q, high-order complement 0 is carried out before splicing, so that (N + M) is an integral multiple of Q; wherein, N is the time sequence path number, M is the timing bit width of the timer module, and Q is the storage bit width of the FIFO memory module.
9. The initiating explosive device timing testing apparatus of claim 7, wherein the FIFO write controller includes a Moore FIFO write state machine and an (N + M) bit shift buffer register.
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