CN106886210B - The priming system timing sequence testing device taken pictures is triggered based on sequence - Google Patents
The priming system timing sequence testing device taken pictures is triggered based on sequence Download PDFInfo
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- CN106886210B CN106886210B CN201710005475.3A CN201710005475A CN106886210B CN 106886210 B CN106886210 B CN 106886210B CN 201710005475 A CN201710005475 A CN 201710005475A CN 106886210 B CN106886210 B CN 106886210B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0221—Preprocessing measurements, e.g. data collection rate adjustment; Standardization of measurements; Time series or signal analysis, e.g. frequency analysis or wavelets; Trustworthiness of measurements; Indexes therefor; Measurements using easily measured parameters to estimate parameters difficult to measure; Virtual sensor creation; De-noising; Sensor fusion; Unconventional preprocessing inherently present in specific fault detection methods like PCA-based methods
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Abstract
It discloses and the priming system timing sequence testing device taken pictures is triggered based on sequence.It is taken pictures by port input filter module, port and sampling module and compares the state change of control logic module parallel monitoring priming system time-ordered measurement port, if the current port state of time-ordered measurement port is different from last time port status, then latch the timers value of Timer module, FIFO memory module is written into timers value and current port state, and updates the last time port status deposited in register module with current port state；The clock frequency of time-ordered measurement port is adjusted by clock frequency division module, compensation is filtered by port input filter module, can arbitrarily adjust the measurement accuracy of adjustment priming system timing time measurement device；By adjusting the timing bit wide of Timer module, timing length requirement expected from system may be implemented.Priming system timing sequence testing device of the invention is small in size, test is fast, precision is high, easily extension, can be directly integrated in airborne equipment.
Description
Technical field
The present invention relates to guided missiles and carrier space vehicle control system equipment to design, in particular to the fire taken pictures is triggered based on sequence
Work product timing sequence testing device.
Background technique
Background of related of the invention is illustrated below, but these explanations might not constitute it is of the invention existing
Technology.
Priming system is a kind of sensitive ignition energy of miniaturization, in conventional weapon ammunition, strategic missile, nuclear weapon and boat
It is widely applied in the military engineerings such as empty aerospace system.Priming system guiding detonating controlling generally passes through relay switch or other switch controls
Power supply processed is connected and is applied on priming system circuit.Priming system timing refers generally to missile armament, carrier rocket is emitting, flying
The control sequence for the priming system for needing successively to ignite in journey.
Priming system timing control possesses very important effect in guided missile and booster system, influences flight success or failure,
So needing to carry out priming system and its control circuit in testing and control and flight course before guided missile and carrier rocket are penetrated
Test, fast and accurately to determine whether priming system access meets launch requirements, the latter is mainly used for flying quality point for the former
Analysis.
Priming system control sequential is typically specific time order, pulsewidth (such as 100ms, 200ms) switching value, main
Tested information be timing at the beginning of, end time and temporal width.General detection mode is by pre-processing circuit
Detect on-off model (generally square-wave signal), after to square-wave signal carry out temporal information detection.Traditional detection mode is
First realize Signal Pretreatment on bullet (arrow), after send ground testing system equipment to be tested.The test mode on ground is: first passing through
Pre-processed results then select the signal if there is signal on ground number transmission control molding block scan (primary to gate timing all the way) bullet
It is logical to send to ground frequency measurement module when surveying, so at the beginning of completing timing, the measurement of end time and width.
The main deficiency of conventional test methodologies is: bullet (arrow) that (1) realization of test function is depended on, equipment is more and volume
Greatly, with the increase of priming system timing number, system extension is complicated；(2) test degree of parallelism is not high, by scanning, choosing test,
It can only once survey all the way, testing efficiency is low, real-time is not high；Due to test macro bullet (arrow), the connection of long line, constitute it is multiple
Miscellaneous, the frequency sampled by intermittent scanning is not high, and measuring accuracy is not high, about 50ms or so.
Summary of the invention
It is an object of the invention to propose to trigger the priming system timing sequence testing device taken pictures based on sequence, can be directly integrated
It is small in size, test is fast, precision is high, easily extension in airborne equipment, guided missile and carrier rocket priming system timing can be effectively improved
Test performance.
The present invention is based on sequences to trigger the priming system timing sequence testing device taken pictures, comprising: port input filter module, port
Take pictures sampling module, compare control logic module, register module, Timer module, FIFO and write logic module, FIFO memory
Module, clock frequency division module and Read-write Catrol module；Wherein,
Read-write Catrol module receives the operational order of extraneous input；Clock frequency division module will be defeated according to external operational order
Enter clock Clk_In and is divided at least two clocks；At least two clock includes Scan_Clk and Sys_Clk, Scan_Clk
Output to port input filter module, Sys_Clk export to priming system timing sequence testing device except port input filter module it
Other outer modules；
Port input filter module will take pictures sampling module output to port after the temporal filtering of each time-ordered measurement port,
Port sampling module of taking pictures obtains the current port state of the time-ordered measurement port parallel and is sent to and compares control logic mould
Block；
After comparing the current port state that control logic module receives the time-ordered measurement port, register module is inquired
The last time port status of the time-ordered measurement port of middle deposit；If current port state and the last time of the time-ordered measurement port
Port status is different, generates latch signal, and the latch signal and the current port state of the time-ordered measurement port are sent out
It send to FIFO and writes logic module；
FIFO writes after logic module receives the latch signal, latches the timers value of Timer module, will be described
FIFO memory module, and working as with priming system time-ordered measurement port is written in timers value and the current port state
Front port state updates the last time port status deposited in register module.
Preferably, clock frequency division module is using counting frequency dividing；The clock phase phase of Clk_In, Scan_Clk and Sys_Clk
Together.
Preferably, port input filter module uses timing filter method；If the present port shape of the time-ordered measurement port
State is different from last time port status, and control module starts the filtering counter based on Scan_Clk:
The initial value for filtering counter is 0；When the count value for filtering counter not up to filters setting value, port input
Filter module filters out the port status variation of the time-ordered measurement port；When the count value of filtering counter reaches filtering setting value
When, port input filter module exports the current port state of the time-ordered measurement port.
Preferably, Timer module is using Sys_Clk as timer clock source；The timing bit wide M of Timer module meets such as
Lower relationship:
In formula, L is timing length, unit h；TshortFor the time-count cycle of Sys_Clk, unit is μ s；Indicate upward
Bracket function.
Preferably, at least two clock further comprises: Syn_Clk_In, and the time-count cycle of Syn_Clk_In is big
The time-count cycle of Sys_Clk；
Timer module includes two timers, one of them is using Syn_Clk_In as timer clock source, for a high position
The thick timing of byte, another is used for the timing of low byte essence using Sys_Clk as timer clock source；
The initial clocking value of Syn_Clk_In and Sys_Clk is 0；When the effective timing of Syn_Clk_In is along not timed out, by
Sys_Clk clock carries out the timing of low level essence, and when the effective timing of Syn_Clk_In is along arrival, low byte essence clocking value clear 0 is high
The thick clocking value of bit byte adds 1.
Preferably, the timing bit wide M of Timer module meets following relationship:
M=M1+M2
In formula, L is timing length, unit h；M1For the timer bit wide of Syn_Clk_In, M2For the timing of Sys_Clk
Device bit wide；TlongFor the period of Syn_Clk_In, unit s；TshortFor the period of Sys_Clk, unit is μ s；Δ1For Syn_
The timing margins of Clk_In, unit s；Δ2For the timing margins of Sys_Clk, unit is μ s；Expression rounds up function.
Preferably, it includes: bit wide converter unit and FIFO writing controller that FIFO, which writes logic module,；
After bit wide converter unit receives the latch signal, the timers value of Timer module is latched, according to FIFO
The storage bit wide of memory module is by the corresponding timers value in all time-ordered measurement ports and the current port state
It is spliced into y byte, and the y byte is sent to FIFO writing controller；Wherein, y is positive integer, the bit wide of each byte
It is equal with the storage bit wide of FIFO memory module；FIFO memory is written in the received y byte by FIFO writing controller
Module, and the last time end deposited in register module is updated with the current port state of priming system time-ordered measurement port
Mouth state.
Preferably, bit wide converter unit is further used for: when (N+M) is not the integral multiple of Q, carrying out before a splice high-order
0 is mended, making (N+M) is the integral multiple of Q；Wherein, N is timing number, and M is the timing bit wide of Timer module, and Q is FIFO memory
The storage bit wide of module.
Preferably, FIFO writing controller includes that a Moore type FIFO write state machine and one (N+M) displacement bit buffering are posted
Storage.
The priming system timing sequence testing device taken pictures is triggered based on sequence according to the present invention, by port input filter module,
Port, which is taken pictures, sampling module and compares the state change of control logic module parallel monitoring priming system time-ordered measurement port, if timing
The current port state of measurement port is identical as last time port status, then continues port monitoring；Otherwise, Timer module is latched
FIFO memory module is written in timers value and current port state by timers value, and with priming system time-ordered measurement end
The current port state of mouth updates the last time port status deposited in register module；Timing is adjusted by clock frequency division module to survey
It measures the clock frequency of port, compensation is filtered by port input filter module, can arbitrarily adjust adjustment priming system timing
The measurement accuracy of time measurement device；By adjusting the timing bit wide of Timer module, it is long that timing expected from system may be implemented
Degree requires.Priming system timing sequence testing device of the invention is small in size, test is fast, precision is high, easily extension, can be directly integrated in bullet
In upper equipment.
Detailed description of the invention
The specific embodiment part provided and referring to the drawings, the features and advantages of the present invention will become more
It is readily appreciated that, in the accompanying drawings:
Fig. 1 is the structural schematic diagram of priming system timing sequence testing device in the preferred embodiment of the present invention；
Fig. 2 is the state transfer schematic diagram of FIFO writing controller in the preferred embodiment of the present invention.
Specific embodiment
Exemplary embodiments of the present invention are described in detail with reference to the accompanying drawings.Illustrative embodiments are retouched
It states merely for the sake of demonstration purpose, and is definitely not to the present invention and its application or the limitation of usage.
As shown in Figure 1, the present invention is based on sequences to trigger the priming system timing sequence testing device taken pictures, comprising: port input filter
Wave module, port take pictures sampling module, compare control logic module, register module, Timer module, FIFO and write logic mould
Block, FIFO memory module, clock frequency division module and Read-write Catrol module；Wherein,
Read-write Catrol module receives the operational order of extraneous input；Clock frequency division module will be defeated according to external operational order
Enter clock Clk_In and is divided at least two clocks；At least two clock includes Scan_Clk and Sys_Clk, and Scan_Clk is defeated
Out to port input filter module, Sys_Clk is exported to other modules in addition to the input filter module of port；
Port input filter module will take pictures sampling module output to port after the temporal filtering of each time-ordered measurement port,
Port sampling module of taking pictures obtains the current port state of the time-ordered measurement port parallel and is sent to and compares control logic mould
Block；
After comparing the current port state that control logic module receives the time-ordered measurement port, register module is inquired
The last time port status of the time-ordered measurement port of middle deposit, P_Data0 as shown in figure 1；If the time-ordered measurement port
Current port state P_Data1 is different from last time port status, latch signal is generated, by the latch signal and the timing
The current port state of measurement port is sent to FIFO and writes logic module；
FIFO writes after logic module receives the latch signal, latches the timers value of Timer module, as shown in figure 1
T_Data, the timers value and the current port state are written into FIFO memory module, and with the priming system
The current port state of time-ordered measurement port updates the last time port status deposited in register module.
The present invention can be according to institute with the state change of parallel monitoring multiple priming system time-ordered measurements port, timing number
Register resources, clock sources and the combination logic resource aggregate demand that need to be consumed are selected.It is surveyed to improve priming system timing
The measurement stability and reliability that trial assembly is set, when timing number is arranged, can making priming system timing sequence testing device, there are certain
Data surplus, such as there are at least 20% data surpluses.
Clock frequency division module can be using counting frequency dividing mode.For example, passing through read-write by host computer using the counter that subtracts one
Control module rewrites the Counter Value, realizes the multi-channel frequency division to input clock Clk_In, is formed and is filled for priming system timing sequence test
Set the clock of same-phase, different frequency that internal each functional module uses.Time-ordered measurement port is adjusted by clock frequency division module
Clock frequency, can arbitrarily adjust adjustment priming system timing sequence testing device measurement accuracy.
Sys_Clk frequency is higher, and measurement accuracy is higher, but excessive frequency not only will increase the resource consumption of device,
It also will affect the stability of reading data.Therefore, in the case where meeting the requirement of system testing precision and data reading speed, Ke Yijin
Measure the reliable crystal oscillator for selecting frequency low: 1. in terms of measuring accuracy: setting the Sys_Clk clock cycle as T1, such as require timing sequence test
Precision is not less than 0.5ms, then Test data generation time (i.e. " Timer module " elapsed time clock cycle T 1, in addition " timer mould
Block " the time lock period (containing the multilevel iudge time before locking) (n × T1), in addition writing FIFO time (m × T1)) it should be less than
0.5ms, i.e. T1+n × T1+m × T1=(1+n+m) × T1 are less than 0.5ms, and n takes 2, m to take 20 in this example, therefore T1 is less than 0.5/
23ms, i.e. frequency are higher than 46kHz；2. in terms of data access speed: such as requiring fire-working article test Data writing time (this example
In, a byte be written enter FIFO need 2 T1 periods) when being slightly above system and reading the data (i.e. reading data fifo)
Between, system take deposit test data time be 4us, then 2 × T1 be less than 4us, then T1 be less than 2us.It integrates 1., 2., and there are one
Determine surplus, can choose 1MHz has source crystal oscillator, i.e. T1 is 1us.
The period of Scan_Clk is smaller, and the test resolving power of priming system timing sequence testing device is higher, but the period is smaller, dress
The resource consumption set is higher, and the stability of reading data can also reduce.Scan_ should be determined according to timing sequence test resolving power requirement
The period of Clk.For example, then the Scan_Clk period should be less than 10us if it is desired to which timing sequence test resolving power is not less than 10us.
The Clk_In period should be not more than min { Sys_Clk period, Scan_Clk period, other clock cycle }, consider to reduce
The requirement such as type selecting and device maturity is unified in logical resource consumption, component, and the Clk_In period can set Clk_In, Scan_
The clock cycle of Clk and Sys_Clk is identical, such as is both configured to 1us, i.e., selection 1MHz's has source crystal oscillator as programmable logic
The external clock of device inputs.
In some embodiments, port input filter module uses timing filter method.If front end is worked as in time-ordered measurement port
Mouth state is different from last time port status, and control module starts the filtering counter based on Scan_Clk: filtering the first of counter
Initial value is 0；When the count value for filtering counter not up to filters setting value, port input filter module filters out the timing and surveys
Measure the port status variation of port；When the count value for filtering counter reaches filtering setting value, port input filter module is defeated
The current port state of time-ordered measurement port out.
For example, the timing bit wide of filtering counter is 8, initial value 0, timer clock is that (period is Scan_Clk
T1), it can be achieved that [0, (28- 1) × T1] filtering of duration in range, it is 127us (corresponding to count that this example, which selectes filtering time length,
127) value is).Under each sampling period of Scan_Clk, using exclusive or criterion, when discovery port status is (with " last time
(initial) port status " ratio, similarly hereinafter) variation when, starting filtering counter, when Counter Value reaches 127, confirm port status
Variation, and export the port status；If Counter Value is not up to 127, port status variation disappears, then filters out the variation,
And maintain former output state.
Timer module can be only using Sys_Clk as timer clock source.It, can by adjusting the time-count cycle of Sys_Clk
Arbitrarily to adjust the accuracy of timekeeping of Timer module；By adjusting the timing bit wide of Sys_Clk, the expected meter of system may be implemented
When length requirement.The timing bit wide M of Timer module meets following relationship:
In formula, L is timing length, unit h；TshortFor the time-count cycle of Sys_Clk, unit is μ s；Indicate upward
Bracket function.
In the present invention, at least two clock that clock frequency division module is formed be may further include: Syn_Clk_In,
And the time-count cycle of Syn_Clk_In is greater than the time-count cycle of Sys_Clk.Timer module includes two timers, one of them
Using Syn_Clk_In as timer clock source, be used for the thick timing of upper byte, another using Sys_Clk as timer clock source,
For low byte essence timing.The initial clocking value of Syn_Clk_In and Sys_Clk is 0；When the effective timing edge Syn_Clk_In
It is not timed out, the timing of low level essence is carried out by Sys_Clk clock, when the effective timing of Syn_Clk_In is along arrival, low byte essence meter
Duration clear 0, the thick clocking value of upper byte add 1.The thick timing of upper byte is carried out with Syn_Clk_In, low level is carried out with Sys_Clk
Byte essence timing can arbitrarily adjust the timing of Timer module by adjusting the time-count cycle of Syn_Clk_In and Sys_Clk
Precision；By adjusting the timing bit wide of Syn_Clk_In and Sys_Clk, timing length requirement expected from system may be implemented.It is excellent
The timing bit wide M of selection of land, Timer module meets following relationship:
M=M1+M2
In formula, L is timing length, unit h；M1For the timer bit wide of Syn_Clk_In, M2For the timing of Sys_Clk
Device bit wide；TlongFor the period of Syn_Clk_In, unit s；TshortFor the period of Sys_Clk, unit is μ s；Δ1For Syn_
The timing margins of Clk_In, unit s；Δ2For the timing margins of Sys_Clk, unit is μ s；Expression rounds up function.
In preferred embodiment shown in fig. 1, it includes: that bit wide converter unit and FIFO write control that FIFO, which writes logic module,
Device；After bit wide converter unit receives latch signal, the timers value of Timer module is latched, according to FIFO memory module
Storage bit wide Q the corresponding timers value in all time-ordered measurement ports and current port state are spliced into y byte, and will
The y byte is sent to FIFO writing controller；Wherein, y is positive integer, bit wide and the FIFO memory module of each byte
It is equal to store bit wide Q；FIFO memory module is written in the received y byte by FIFO writing controller, and when with priming system
The current port state of sequence measurement port updates the last time port status deposited in register module.
For example, when N+M=72, storage bit wide are 8, by the corresponding timers value in all time-ordered measurement ports and currently
Every 8 of port status are one group as a byte, are spliced into 9 bytes, are successively denoted as from low level to high-order each byte
Byte0, Byte1 ..., Byte8), be sent to FIFO writing controller after the completion of splicing.
It, can not be according to above-mentioned carry out data splicing when (N+M) is not the integral multiple of Q.Based on this, bit wide converter unit can
To be further used for: when (N+M) is not the integral multiple of Q, carrying out high-order benefit 0 before a splice, making (N+M) is the integral multiple of Q；Its
In, N is timing number, and M is the timing bit wide of Timer module.For example, being mended when N+M=70, storage bit wide are 8 in a high position
2 " 0 " are filled, are spliced into 72, every 8 are one group as a byte, 9 bytes can be formed, from low level to high-order each word
Section be successively denoted as Byte0, Byte1 ..., Byte8), be sent to FIFO writing controller after the completion of splicing.
FIFO writing controller may include a Moore type FIFO write state machine and (N+M) bit shift buffer stock
Device.Fig. 2 shows the states of FIFO writing controller in the preferred embodiment of the present invention to shift schematic diagram, wherein FIFO writing controller
Including a Moore type FIFO write state machine and a 72 bit shift buffer registers.Moore type FIFO write state machine, is divided into
19 states, are described as follows:
ST0-electrification reset (Rst_In) original state afterwards；
When ready invalidating signal, show data invalid, set (wherein late half of clock cycle output of Wr_En ratio Lock,
Similarly hereinafter):
When ready signal is effective, set:
ST1 --- set following state (unlisted signal keeps laststate, similarly hereinafter):
ST2 --- set following state:
ST3 --- set following state:
ST4 --- set following state:
ST5 --- set following state:
ST6 --- set following state:
ST7 --- set following state:
ST8 --- set following state:
ST9 --- set following state:
ST10 --- set following state:
ST11 --- set following state:
ST12 --- set following state:
ST13 --- set following state:
ST14 --- set following state:
ST15 --- set following state:
ST16 --- set following state:
ST17 --- set following state:
| Serial number | Signal name | Signal condition | Remarks |
| 1) | Wr_En | In vain | FIFO write control signal |
| 2) | Scan_En | Effectively | Port, which is taken pictures, samples enable signal |
| 3) | next_state | ST0 | NextState |
ST_Other --- set following state:
When Lock signal is effective, 72 bit shift buffer registers lock the data of bit wide converter unit output, lock number
Current port state data " P_Data1 " part in is sent out as last time port status simultaneously, for comparing control logic mould
Block inquiry.When Shift_En is effective, shifted: Byte0 → Byte1 → Byte2 → Byte3 → Byte4 → Byte5 →
Byte6→Byte7→Byte8→Byte0。
If programming device resource is abundant, can priming system reality timing sequence testing device intrinsic call Universal FIFO IP or
By FIFO working principle designed, designed FIFO memory, the integrated level of design is can be improved in this scheme, but provides to programming device
Source is more demanding, and design complexities are also higher.It is of course also possible to use extend out FIFO memory chip, design is simple, to can compile
Journey device resource requires low.
In the technology of priming system timing sequence testing device of the present invention, those skilled in the art can extend according to actual needs
Other logics, as shown in Figure 1, the present invention does not elaborate to this.
Although referring to illustrative embodiments, invention has been described, but it is to be understood that the present invention does not limit to
The specific embodiment that Yu Wenzhong is described in detail and shows, without departing from claims limited range, this
Field technical staff can make various changes to the illustrative embodiments.
Claims (8)
1. triggering the priming system timing sequence testing device taken pictures based on sequence, characterized by comprising: port input filter module, end
Mouth take pictures sampling module, compare control logic module, register module, Timer module, FIFO write logic module, FIFO storage
Device module, clock frequency division module and Read-write Catrol module；Wherein,
Read-write Catrol module receives the operational order of extraneous input；When clock frequency division module will be inputted according to external operational order
Clock Clk_In is divided at least two clocks；At least two clock includes Scan_Clk and Sys_Clk, Scan_Clk output
To port input filter module, Sys_Clk is exported to priming system timing sequence testing device in addition to the input filter module of port
Other modules；
Port input filter module will take pictures sampling module output to port after the temporal filtering of each time-ordered measurement port, port
Sampling module of taking pictures, which obtains the current port state of the time-ordered measurement port parallel and is sent to, compares control logic module；
After comparing the current port state that control logic module receives the time-ordered measurement port, inquires in register module and post
The last time port status for the time-ordered measurement port deposited；If the current port state of the time-ordered measurement port and last time port
State is different, generates latch signal, the current port state of the latch signal and the time-ordered measurement port is sent to
FIFO writes logic module；
FIFO writes after logic module receives the latch signal, the timers value of Timer module is latched, by the timing
FIFO memory module is written in device numerical value and the current port state, and works as front end with priming system time-ordered measurement port
Mouth state updates the last time port status deposited in register module.
2. priming system timing sequence testing device as described in claim 1, which is characterized in that clock frequency division module is using counting point
Frequently；Clk_In, Scan_Clk are identical with the clock phase of Sys_Clk.
3. priming system timing sequence testing device as described in claim 1, which is characterized in that port input filter module uses timing
Filter method；If the current port state of the time-ordered measurement port is different from last time port status, control module starting is based on
The filtering counter of Scan_Clk:
The initial value for filtering counter is 0；When the count value for filtering counter not up to filters setting value, port input filter
Module filters out the port status variation of the time-ordered measurement port；When the count value for filtering counter reaches filtering setting value,
Port input filter module exports the current port state of the time-ordered measurement port.
4. priming system timing sequence testing device as described in claim 1, which is characterized in that at least two clock further wraps
It includes: Syn_Clk_In, and the time-count cycle of Syn_Clk_In is greater than the time-count cycle of Sys_Clk；Timer module includes two
Timer, one of them is used for the thick timing of upper byte, another is with Sys_Clk using Syn_Clk_In as timer clock source
For timer clock source, it to be used for the timing of low byte essence；
The initial clocking value of Syn_Clk_In and Sys_Clk is 0；When the effective timing of Syn_Clk_In is along not timed out, by Sys_Clk
Clock carries out the timing of low level essence, when the effective timing of Syn_Clk_In is along arrival, low byte essence clocking value clear 0, and upper byte
Thick clocking value adds 1.
5. priming system timing sequence testing device as claimed in claim 4, which is characterized in that the timing bit wide M of Timer module is full
The following relationship of foot:
M=M1+M2
In formula, L is timing length, unit h；M1For the timer bit wide of Syn_Clk_In, M2For the timer position of Sys_Clk
It is wide；TlongFor the period of Syn_Clk_In, unit s；TshortFor the period of Sys_Clk, unit is μ s；Δ1For Syn_Clk_
The timing margins of In, unit s；Δ2For the timing margins of Sys_Clk, unit is μ s；Expression rounds up function.
6. priming system timing sequence testing device as described in claim 1, which is characterized in that it includes: bit wide that FIFO, which writes logic module,
Converter unit and FIFO writing controller；
After bit wide converter unit receives the latch signal, the timers value of Timer module is latched, is stored according to FIFO
The storage bit wide of device module splices the corresponding timers value in all time-ordered measurement ports and the current port state
FIFO writing controller is sent at y byte, and by the y byte；Wherein, y is positive integer, the bit wide of each byte with
The storage bit wide of FIFO memory module is equal；
FIFO memory module is written in the received y byte by FIFO writing controller, and with the priming system time-ordered measurement
The current port state of port updates the last time port status deposited in register module.
7. priming system timing sequence testing device as claimed in claim 6, which is characterized in that bit wide converter unit is further used for:
When (N+M) is not the integral multiple of Q, high-order benefit 0 is carried out before a splice, making (N+M) is the integral multiple of Q；Wherein, when N is
Sequence number, M are the timing bit wide of Timer module, and Q is the storage bit wide of FIFO memory module.
8. priming system timing sequence testing device as claimed in claim 6, which is characterized in that FIFO writing controller includes one
Moore type FIFO write state machine and (N+M) bit shift buffer register.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710005475.3A CN106886210B (en) | 2017-01-04 | 2017-01-04 | The priming system timing sequence testing device taken pictures is triggered based on sequence |
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| CN201710005475.3A CN106886210B (en) | 2017-01-04 | 2017-01-04 | The priming system timing sequence testing device taken pictures is triggered based on sequence |
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| CN109377588B (en) * | 2018-10-29 | 2021-11-12 | 百度在线网络技术（北京）有限公司 | System and method for testing system time sequence of automatic driving vehicle and vehicle |
| CN112444168B (en) * | 2019-09-05 | 2024-02-13 | 南京理工大学 | Accurate timer for preventing wiring error electric shock and tube explosion |
| CN114546030A (en) * | 2022-02-15 | 2022-05-27 | 海光信息技术股份有限公司 | Chip clock design method, chip, device and related equipment |
| CN116112627B (en) * | 2023-04-07 | 2023-06-20 | 合肥六角形半导体有限公司 | Method and circuit for video frame rate self-adaptive transformation |
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