SU1429121A1 - Device for generating tests - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase the speed of the device. The device consists of a clock generator, a pseudo-random number generator, a synchronization block, a meter for the test length, a block for setting initial data, three shift registers, two counters, a multiplexer, an And element, a group of And elements, a trigger group, a block and a switching node . The device allows for the automatic synthesis and generation of test sequences. 7 il. Yes

Description

N4

YU

YU

| seam

The invention relates to automation and computing technology and can be used in the production of control of integrated circuits, and

also nodes and blocks based on these schemes,

The purpose of the invention is to increase speed.

A: FIG. 1 is a block diagram of a device; in FIG. 2, a syncro - block: iz; in Fig. 3, a memory block and; a shift register in Fig. 4, mutually; in separate elements of the device; FIG. 5, schematic interoperable: in the blocks shown in FIG. 4, IIPH, where m is the maximum number of strokes of the test object; in Fig. 6, a meter with a variable counting module; jia fig 7 - multiplexer

I The device (Fig. 1) contains the jjaTOp 1 clock pulses, the t generator of pseudo-random numbers, the synchronization unit 3, the test length counter 4, the initial data setting unit 5, the shift data registers 6 and 7, the counter 8 (with variable counting module), counter 9, multiplexer 10, shift register P., element 12, group 13 of elements AND, group of flip-flops 14, memory block 15, switching node 16, input 17 of the device operating mode

The synchronization unit (FIG. 2) contains a register 18, a memory unit 19 (command ROM), the switch 20, the counter 21, the element AND 22, the OR element 23, the trigger 24, the display elements 25 and 26, the initial address setting unit 27 ,,

The counter (Fig. 6) contains a group of triggers 28 ,,,, 28, a group of elements 2-2И-OR 29 ,,,, 29. (-1), a group of elements OR (30.1 ,, 30,) -1).

Consider the main functions, namyaemye from the device blocks

The clock pulse generator 1 is designed to synchronize the operation of the device nodes for generating tests.

The pseudorandom number generator 2 is designed to generate a sequence of uniform binary symbols with reference statistical characteristics. The generator operation is synchronized by pulses of the clock pulse generator (GTI), the reference S-inputs of the shift register triggers are connected to the synchronization unit 3 and serve as a preliminary

setting the generator to its initial state before starting the digital unit test,

The synchronization block 3 (Fig. 7) is intended to form the control and synchronization signals necessary for the device to operate as a whole. The block consists of a microprogram control device consisting of an address register and a ROM, a block of two-input elements I, KB-trig - gera, the address counter of the memory block 15, switching and indication elements, switches serves for preliminary recording in the microcommand address register the RAM address of the microprogram recorded in the ROM. The upper position of the switch corresponds to It supplies the level of a logical unit, the lower position is a logical zero. A synchronous potential, an indexing record in the register, is supplied to the input of the synchronization C1 of the PA1CCH. The recorded information is the starting address of the firmware read from the ROM. The presence of a lit indicator reveals that the trigger on: kits in one state, i, e, a memory area is selected in which the conditional jump or stop: commands are stored.

A microcommand from a ROM read: So. It consists of two fields - the address field of the next microcommand and the field of control signals. After the address, the next microcommand has a size of 3. + 1, a control field, signals are fifteen bits, with the twelfth V; and the thirteenth At, the control signals serve to control the address counter, which is part of the synchronization unit 3, the fourteen control signal Y controls the valve allowing the supply of such pulses from unit 1 to the input C2 of the RMK. When a clock pulse is sent to this input, the address of the next microcommand is written to the register. In addition, the clock pulses arrive at the second inputs of the AND elements 13, the first inputs of which are connected to the ROM outputs. This ensures the formation of pulse control signals, which is necessary when reading a sequence of single signals. The prohibited state of the valve is indicated by the display unit 26. The control signal, Wo, connects to the 16 switching and is the source of the clock signals for the counter 8 with the variable counting module. The high potential at control input 17 corresponds to the supply of clock pulses per clock to the input of counter 8, the low potential ensures that a pseudo-random sequence from generator 2 is fed to the synchronous input of counter 8,

The control signal of the SR of the synchronization unit 3 is designed to reset to zero the stop trigger in the mode of the firmware execution. The sync signals V) VC are, respectively, for synchronizing the first register 6, synchronizing the generator 2 for setting the initial state of block 2,

 increments per counter 4, it is 2o of the first trigger, and is sync25

thirty

35

cremating the counter 9, synchronizing the register 11, resetting the registers M and 14 to zero, synchronizing the block 12, controlling the reading / writing of the memory block 15, synchronizing the second register 7,

The counter 4 is designed to generate a stop signal for the synchronization unit 3 at the end of the test. Information on the length of the test sequence is entered from block 5 by setting the appropriate code on the information inputs of the counter and setting the recording mode on the inputs S and Sj.

Vlok 5 is a set of on / off switches, as well as a driver 9 for a block reset pulse.

The first and second registers 6 and 7 are intended to supply constant logical values to the inputs of counter 8. The signals recorded in the registers contain information on the inputs / outputs of the circuit under test, as well as subsets of the set of inputs of the control object. The hardware implementation of the registers can be implemented using K 155 integrated circuits IR1.3.

Counter 8 (fig. 6) contains m DV-flip-flops with control inputs, (ia-l) OR elements and (ml) 2-2-I11I elements, with the inverse outputs of the flip-flops connected to their information gg inputs, V The trigger inputs are interconnected and interconnected and represent the permissive input of a counter with a variable counting module, in addition.

40

45

50

a variable count counter input; the R and W inputs of the flip-flops form a group of inputs of block 8, the outputs of which are the direct outputs of the D-flip-flops.

In conjunction with the drup-gmi units of the device, the counter 8 implements the specified modes of operation:

1.For1-5th sequence of equal binary symbols

with standard statistical characteristics (pseudo-random sequences).

2. Formation of a sequence of binary symbols with a variable version of their appearance.

3. Formation of logical constants.

4. The formation of the test type running code (in the particular case - a running zero and a running unit).

5. Formation of account functions.

The combination of the structural components of the counter 8 and the registers 6 and 7 allow to implement the above-mentioned types of sequences on a given set of inputs of the control object, which leads to a reduction in the total testing time.

Counter 8 operates as follows. If there are no single signals from the outputs of registers 6 and 7 on the S and R inputs of the triggers of each of the bits, then the OR elements whose inputs are connected to the S and R inputs of the triggers will generate a zero logic level that permits the signal to pass. from the output of the previous trigger to the sikhrovkhod, the control R- and S-inputs of the corresponding triggers, besides the th, are the inputs of the corresponding OR elements, the outputs of which are the control inputs of the 2-2-KPI elements, each output from which, except for (ml) -ro, is connected to syncronization im input the subsequent trigger and

the second information input of the subsequent element 2-2 and-OR, and the output (ml) -ro of the element 2-2 and-OR is connected to the synchronizing input of the m-th trigger, and the first outputs of the D-t.riggers, except for the i-th, connected to the first information inputs of the element 2-2I-ISH, in addition, the second information input of the first element 2-2I-P1TTI is connected to the synchronization input :.

five

0

five

g

0

five

0

the counter input with a variable calculus counter, the R and W inputs of the flip-flops form a group of inputs of block 8, the outputs of which are the direct outputs of the D-flip-flops.

In conjunction with the drup-gmi units of the device, the counter 8 implements the specified modes of operation:

1.For1-5th sequence of equal binary symbols

with reference statistical characteristics (pseudo-random sequences).

2. Formation of a sequence of binary symbols with a variable probability of their occurrence.

3. Formation of logical constants.

4. The formation of the test type running code (in the particular case - a running zero and a running unit).

5. Formation of account functions.

The combination of the structural components of the counter 8 and the registers 6 and 7 allow to realize the above-mentioned types of sequences on a given set of inputs of the control object, which leads to a reduction in the total testing time.

Counter 8 operates as follows. If there are no single signals from the outputs of registers 6 and 7 at the S- and R-inputs of the flip-flops of each of the bits, then the OR elements, whose inputs are connected to the S- and R-inputs of the flip-flops, will form a zero logic level that permits the passage of the signal from the output of the previous trigger to the sikhrovkhod follower) is through the corresponding input of the electrical switch, And since the triggers of the counting are in the circuit with the counting care, when blocking the logical units to their V-inputs, - block 8 represents eiT is a ha-binary binary account- Cheek. EA1 from the registers 6 or 7 on the s | din from the control inputs, a certain trigger and a group of trigger points of the count 8 comes in the level of a logical unit, the latter are set to the corresponding state O pl 1, and the corresponding elements 1С (} control signals, 1: which allow one to exclude data 1 | riggers from a chain of sequential ifH connected memory elements of the count- 8. This forms a counter (1 conversion factor. where 1. is the number of constant values on the output of the counter with a variable counting module .

 When the pseudo-random generation mode is turned on, the sync input of the block 8, through the node 16, receives a signal from the pseudo-random number generator 2, and the enabling input - a sync pulse U, {. At the same time, in the memory cells of the counter 8, modularly stored information and information j {coming from the previous bit of a chain of successively connected triggers are added modulo, which allows us to take pseudo-random sequences on the corresponding outputs of the device.

Invoice, Chick 9 is intended to form the functions of the invoice j

on the inputs of the multiplexer 10 and the group of 13 elements AND, the counter operates in. two modes - parallel recording of information from the inputs A / i ,,. ,, Ant. and incremental mode. The mode is selected by supplying the appropriate logic level to the input of the counter from block 5 of the initial data. Addition pulses are generated by block 3 synchronization.

The third register I1 is designed to record information from the output of an object of a counter or a randomly selected point of the combinational circuit using a probe. The information is recorded when the register 11 arrives at the C input and the shift from the block 3 is reset. The register is reset by filing with

ABOUT

ABOUT

five

0

five

corresponding to its impulse to the input R of the register setting to zero.

Element I 12 is designed to synchronously transfer information from the output of a combinational circuit to the inputs of group 13 of elements I. Element 12 is a standard element of Boolean algebra. .

A group of 13 elements. And contains .t two-input elements, to the first inputs. Which are connected the outputs of the binary counter 9, and the second inputs - to the output of the element And 12 for supplying a synchronizing signal at the corresponding time point. i

The display elements that can be installed on the triggers 14 are necessary for the visual personnel to read the information by the service personnel in order to form the required actions using the synchronization unit 3 and the initial data setting unit 5.

Block 15 is needed to accumulate information about the subsets of the inputs of the circuit under test, affecting the switching of the given point or the output of the cubic part of the circuit under test. The necessary information from block 15 at the appropriate time is retrieved and placed in the selected register 6 or 7. The address inputs of block 15 are connected to the outputs of the address counter of block 3, one of the control signals of which forms a recording strobe or logical read RAM level.

The device works as follows.

Information on the inputs / outputs of the monitored device (logical unit - input, logical zero - output) is typed on the switches of block 5. The said outputs are connected

with information inputs

binary counter 9, the corresponding switch of the block 5 (the second output of the fourth group of outputs), connected to the input S of the operation mode of the block 9, is set to the parallel recording mode. In this case, the binary counter performs the function of a conveyor register, which is written to by supplying a pulse from the synchronization unit 3 to the synchronous input.

Registers 11 and 14 are set to zero by a reset pulse supplied from the unit. 3 sync. After this

The first input of the block 11 is connected to the +5 V power bus to create the second register of the shift of the level of the logical unit. Feed the clock. This information is recorded in the first trigger of block 11.

From block 3 to the input of the element 12, a synchronizing pulse is supplied, which, together with the output signal Q of the multiplexer Yu (logical unit), allows information to be transmitted through a group of 13 elements I from the outputs of block 9 to the inputs of a group of trigger 14. In this case, the transmitted code goes tS to The S inputs of the group triggers, which allows for the necessary rewriting (Fig. 4).

Unit 3 sets the address of the memory block 15 with the signal Y to the 20th state, after which the write strobe Rx enters the Read-Write input of the unit 15, which initiates the recording of the inverse information from the outputs of the register 14 to the zero memory location. 25 Transmission, inverse information is necessary in order for input / output information recorded in the first or second shift registers 6 or 7, respectively, to exclude from the 30 structure of the counter 8 triggers, the outputs of which are fed to the outputs of the control object. The switching off of the corresponding trigger is carried out by the level of the logical unit, which is caused by the design of counter 8 with a variable counting module, while the initial setting of information on inputs / outputs is inverse.

The purpose of the described actions is to transfer the input / output information Q to register 6 or 7 in order to organize an exhaustive search of code combinations on the inputs of the circuit under test. The corresponding firmware is written to the dL in the form of a sequence of control signals. The structure of the readable microcommand contains the address field of the next microcommand DO ..., DQ and the control signal field of X, .e. To access this firmware on node 27 of the synchronization unit 3 its start address is dialed (in this case, zero), which leads to parallel entry of information specified on the switches into the microcommand address register and setting the stop condition to the zero state. In this case, the indicator

25 is turned off. The zero microinstruction allows the passage of synchronization pulses from the block 1 of clock pulses through the element 12 to the input C2 of the register of the address of the microcommand (signal Y,). The control signal field of this microcommand contains control signals for the AM, AM, and. Y, which allow recording information on the inputs / outputs of the circuit under test in counter 9, reset register 11 and the group of triggers 14 to zero, add the zero combination to the address counter of memory block 15, respectively. After the zero microcommand is executed, the unconditional transition to the microcommand execution, whose address is specified in the DO, field, is performed. “. , D-, In this case, the transition is made to the first microcommand containing the control signals Y - recording the logical unit in the zero trigger register 1 1, Y - the synchronization resolution. Next, the transition to the microcommand with address 2 is performed. When this microcommand is executed, the control signal Y synchronizes the 12 ft block and leads to writing the input / output information from block 9 to the triggers

14 through a group of 13 elements I. A microcommand recorded at the third address forms a recording strobe of the memory block 15. A fourth microinstruction generates a Y-sync signal for the 6-shift register master in order to reload information from the zero cell of the block.

15 Miles For this purpose, it is assumed that a combination of logic signals containing information

about parallel write to the register. The firmware is completed with the execution of the fifth microcommand containing the control signals Y, U4, UG, which allows to set the initial state of the generator of 2 pseudo-random numbers, enter information about the length of the test sequence from the outputs of the unit 5, set the initial data to the counter 4 of the test length, reset to zero register 11 and triggers 14. After this, the transition to the micro-command with address 6, which does not contain control signals, i.e. The Stop command is executed. A zero logic level (signal Y,) turns off the clock pulse generator

 9.1А

the background and operation of the device is stopped, 1) the firmware execution shutdown is generated by the B1 switch on the lU 26 indicator.

: In addition to the firmware No. 1 described above, the ROM contains another microdirectory, which allows, in a similar way, to insert the necessary information in the second shift register 7. The firmware is supposed to be executed immediately after the first microprogram (Jprograms, Stop after the first firmware is executed, due to the need to change the original data assigned to write to the shift register J7. This firmware is from the seventh to one address fbm of the PNL address. Twelve the cell | TLM contains the Stop command, which is ana logically considered,: After performing the specified microprogramming switchings of block 5, the storage mode of the shift registers 6 and 7 is set, the counting mode of the counting 9. Level The level at the control input of node 16 is set to a single value J, which corresponds to the setting of the counter counting mode, 8 with a variable counting module. The third input of the shift register i1 is connected to a given point of the control object, for which the vector - a string of binary digits,; single signals in which will; correspond to circuit inputs that affect the switching of a given point. The brute-force search code combinations at the inputs of the control object begins with the thirteenth address. At this address, the control signals are counted., U, V 1- The signal 4 is incremented by the counter 4, the signal U is the signal to write the output information of the control object to the register 11, By the signal Un1 is added, units in counter 8 with a variable counting module. The address field of the next microcommand contains the address of the current microcommand, which causes the listed operations to be performed within the time required to iterate through all the combinations at the circuit inputs. When the counter overflows 4 test lengths, the Stop signal goes to the 5 - input of the stop trigger and sets it to one. In this case, the next command is read and

0

five

0

121

25 dd 55

thirty

35

40

50

ten

ROMs with address + B (B - thirteen cells). This command allows a conditional transition to the microcommand with address 14, and, in addition, by setting the MA, set the stop trigger to the zero state. The microcommand with address 14 serves to increase the content of the counter 9 (signal) by a unit and make a transition to the microcommand with the address 15, Last, with the signals Y /) and Y performs the increment of the counter 4 and synchronize the block 12 in order to generate a permit pulse for transmitting the contents of the block 9 in reggae page 14, after which the transition to the fourteenth microcommand takes place. These two microcommands are repeated in the cycle until the test length counter 4 overflows, after which the trigger stop of the synchronization unit 3 is set to one state by the overflow signal and the transition to the micro command; with the address (C - p thirteen cell). This microinstruction resets the stop trigger to zero and performs a conditional transition to the microcommand with address 16, which is necessary to increment the contents of the block 15 address register (55g ACM) to write the generated vector line to the next free cell of the block 15. The seventeenth microcommand forms RAM write strobe and goto micro stop command 18.

If it is necessary to form other vectors (for other points of the scheme), it is necessary to carry out nepeKOi i-tation of the input of the third shift register 11 and re-access the microprogram, starting from the thirteenth address of the ROM.

After the completion of the formation of all the specified rows, you can go to the test mode of control objects. The testing firmware is located, starting with the nineteenth address of the ROM, Preset is set to parallel write register 6, the test length information is entered in block 4, the test length information for the selected point (or circuit output) can be determined by the operator when building the corresponding vector line . This requires a binary

Combine counting with register indicators 14.

Appeal to the nineteenth microcommand ROM allows you to set the zero code in the address counter of block 15 (signal Xg. Go to the twentieth command. This microinstruction generates a pulse to record the necessary information in counter 4 10 test length and add one to the address counter of block 15. A microcommand located at address 21 is needed to form a write signal to one of registers 6 or 7 (for example, 15 register 6) and go to micro stop command 22. This is necessary to set the counting modes 4 and

storage mode shift register 6. Thereafter, control 20 is transferred to the twenty-third cell.

ROM, control signals in which V4 and V are designed to increment counters 4 and 8. Twenty-third command A repeats until 25

until counter-4 overflows and the conditional transition to the stop command with address 2 occurs ({, + A. While testing the specified

point, or circuit output is completed. 30 In order to continue testing the other points of the circuit, it is necessary to set the desired operation modes of counter 4 and register 6 and refer to the twentieth microcommand ROM. 35

Claims (1)

Invention Formula A device for generating tests that contains a clock pulse generator 40, a pseudo-random number generator, a synchronization unit, a test length counter, a source data setting unit, two shift registers, a first counter, and the output of the generator also takes 45 synchronous pulses , the first group of input data assignment unit blocks is connected to the information inputs of the first shift register, and the third group of output data blocks of the source data set block are connected respectively to the information inputs the second shift register and the test length counter, the overflow output of which is connected to the stop input of the synchronization unit, the first output of which is connected to the synchronous input of the first shift register, the second, third and fourth outputs of the synchronization unit are connected to the installation Wlod of the pseudo-random number generator and counting input counter dpina test, respectively, the information inputs of which are connected to the fourth group of outputs of the initial data task block, which differs in that, in order to improve speed, a second counter, multiplexer, third shift register, AND element, AND group, trigger group, memory block and switching node are entered into the device, moreover, the fifth group of outputs of the initial data setting block is connected to the group of information inputs of the second counter, and the pole group of outputs of the initial data setting block is connected to the inputs of setting the mode and resetting the second counter, the direct count input of which is In addition, the group of t-bit outputs of the second counter (where m is the device test word width) is connected to the first group of control inputs of the multiplexer, the group of information inputs of which is connected to the group of bit outputs of the third shift register, the output of the second counting () is connected to the first input of the i-ro element And the group of elements And, the second inputs of which are connected to the output of the element And, the first input of which is the output of the multiplexer, and the second input of the element AND is connected to the sixth output of the synchronization unit, the outputs of the AND elements of the group are connected to the input CI of the installation of the corresponding group triggers, the reset inputs of which are connected to the seventh output of the synchronization unit and the reset input of the third shift register , the outputs of the group triggers are connected to the information inputs of the memory unit, the group of address inputs of which is connected to the group of outputs of the synchronization unit, the output of the clock generator is connected to ne vym information input switching node, a second data input connected to the output of pseudorandom number generator, a control input Wela switch connected to a first input of th ustroy- specifying the operating mode. facilities, the first and second outputs of the switching node are connected to the enable and counting inputs of the first counter respectively, and the outputs of the memory block are connected: to the information inputs of the first and second shift registers, in addition, the eighth output of the synchronization block is connected to the synchronous input of the second shift register, the nine output of the synchronization unit, to the third input of the third shift register is the second input of the OcmaH0S-device operation mode setting. from d / rof a JH by SnoKu 1 The bit outputs of the first counter are the outputs of the device, the bit outputs of the first shift register are connected to the set inputs to the zero state of the corresponding bits of the first counter, the set inputs in single state of which are connected to the corresponding bit outputs of the second shift register. 1g} CUZHQ / IH To address tires loky P5 fuz.2 From SaoKtLS OHI / Moisl OmfmaS Urn iff bullpen Bxoi 0Ht // iei (u3 From yomZ : m-j From and, g. 5 " one I Jff 7G X .. days |  CpCiC CjCifCs From ffloKa i1 9ll2, l IB KfflOKij 2 t