SU991397A1 - Multi-function binary train generator - Google Patents

Description

one

The invention relates to a decisive technique and is based on HcnonbaojeaHo to form test sequences in devices verified by logic circuits.

A binary sequence generator is known that forms a pseudo-random sequence of maximum length, which contains a clock pulse generator, a sequence storage unit in the form of a register whose outputs are generator outputs, and a modulo two whose inputs are connected to some outputs through a switching circuit. register, and is connected to the inputs of the register Cl3.

However, a tax generator has little flexibility and can change its configuration (the number of bits, numbers and the number of bits connected to the inputs of the adder, etc.) only to a limited extent.

The most powerful is the generator, in which the storage unit is designed as a storage device with a volume of N words, each word of which imitates a bit of an N bit shift register. In this case, the generator includes an instruction generator — a program sensor and a device for modifying the drive's address — the adder, because to simulate a left-shift, the drive's executive address in the next tick must be increased by 2 compared to the same address in the previous tick, summation is performed over N.

In this case, the generator forms a pseudo-random sequence of programmable connection of bits with the inputs of the modulo two t. .

For limestone generators, the following drawbacks are characteristic of their use as sensors of test sequences:

39913974

- the impossibility without an additional is connected to the second output of the generator of equipment for obtaining several times-pulses, the third output of gene-generators of pseudo-random and / or regular sequences with given numbers of bits and given laws for the formation of feedback; - impossibility without additional equipment to obtain several dependent generators of the above sequences. The purpose of the invention is to extend the functionality by partitioning the accumulator into a number of sections simulating the required number of shift registers. In this case, for correct modification of the address, it is necessary to have data on the addresses of the first bits, on the number of bits, and on the current value of the modification of the addresses of the bits of the simulated shift registers. The goal is achieved by the fact that a multifunctional binary sequence generator containing a clock pulse generator, the first output of which is connected to the counting input of an address counter, the first installation input of which is connected to the first control input of the generator, the second installation input - with the output of the last generation Yes register, a-output - with the address input of the program memory block, the information and control inputs of which are connected to the first information and second control inputs, respectively, of the generator The second output of the clock generator is connected to the recording input of the program memory, the outputs of the sign code and the register bit code are respectively connected with the first input of the first modulo-two adder and the decoder leaving the output connected to the information input of the register The input of which is connected to the output of the first adder in 1 1 module two, the second input of which is connected to the output of the first memory block, the address and information inputs of which are connected respectively to the output (M of the first and second meters Only the typelexers, the information inputs of which are connected to the first rei epaTQpa address input, the second information input of the second multiplexer are connected from the second modulo two information inputs. Which are connected to the outputs of the first group register, the outputs of the second group are connected to the generator, and the clock pulses register clock input is connected to the recording input of the first memory block, the output of the first digit of the decoder is connected to the first input of the third multiplexer, the second input connected to the input of the logical unit of the generator, the control inputs of the clock pulse generator of the third multiplexer are connected to the second control input of the generator, the fourth and fifth multiplexers are added, the second and third memory blocks, the counter set by the module and the address generator, the control inputs of the third and fourth multiplexers and the third memory block are connected to the second control input of the {5ator gene, the output of the code code of the simulating register of the program memory block is connected to the first data input of a fourth multiplexer, a second information You are a. the course of which is connected to the second address generator of the generator, the logical input of the generator is connected to the first information input of the fifth multiplexer, the second information input of which is connected to the output of the counter modulo, the installation input of which is connected to the first input of the address generator and the output of the third memory block, information the input of which is connected to the output of the fifth multiplexer, the address input to the address input of the second memory block and the output of the fourth multiplexer, the control input of the third memory block from connected to the counting input of the counter for a given module, with the control input of the first memory block and the output of the third multiplexer, the output code of the relative address is connected to the second input of the address generator, the third input of which is connected to the input of the counter module for a given module and with the output of the digit code The second memory block, the output of the code address of the first bits of which is connected to the fourth input of the address generator, the output of which is connected to the second information input of the first multiplexer, the information input of the second The second memory input is connected to the second information input of the generator, the recording inputs of the second and third memory blocks and the synchronous input of the counter in a given module are connected to the first, fourth, and second outputs of the clock generator, respectively. :(

At the same time, the Apres co-driver is three adders and a multiplexer, the output of which is connected to the first input of the first adder, which is connected to the fourth input of the imaging unit, and the output of the second adder is connected to the first information input of the multiplexer, the second information input BXCNI which is connected to the first input of the second adder and the output of the third adder, the first and second inputs of which are connected to the first and second inputs of the imaging device, the third input of which is connected to the second input of the second adder, carry output Kogoro connected to the control input of the multiplexer.

FIG. 1 shows a functional diagram of the generator} in FIG. 2 is a functional diagram of the address driver.

The generator contains (FIG. 1) a clock pulse generator 1, a program sensor 2 comprising a counter 3 addresses a program memory block 4, a modifier

5 addresses containing multiplexers

6 and 7, blocks 8 and 9 of memory, counter

10 according to the specified module, driver

11 addresses, drive 12 of simulated registers containing multiplexers 13 and 14, memory block 15, adder 16

modulo two, block 17 simulated registers containing decoder 18, register 19, adder2O, modulo two, multiplexer21, first control / generator input 22, second generator control input 23, first generator information input 24, first and second address inputs 25 and 26 of the generator, the second information input 27 of the generator, the output 28 of the generator. .

The address generator 11 (FIG. 2) contains adders 29-31 and a multiplexer 32.

. The principle of operation of the generator is as follows.

Block 15 is divided into P groups with consecutive addresses in each group, so that the total number of words in all groups does not exceed the amount of RAM. Each of these groups simulates the corresponding shift register of the sequence generator, the cell with the lowest address in the group simulates the first register bit. The address of this cell 8 will be the base against which the addresses of all subsequent cells in the group will be counted.

And. The number of cells in the group L.- corresponds to the selected length of the shift register. Thus, to simulate a shift in each group, it is necessary that in the nth cycle the executive address supplied to block 15 should be related to the address in the preceding n – 1 cycle by

A. G. 8y t () by (i) or

 gi

;.) nx, dL.; (2,

. (n-1)

where M y is the current value of the modifier j of the group in the n-1 takte,

(h) modU; (B)

In block 4 a command of the generator operation program is written in the form of words of the following format: the first group of bits contains the binary code of the generator number, the second - the binary code of the relative bit address of the register of this generator, the character bit, and the last group of bits contains the binary code output register number 19. Let us need to organize a pseudo-random sequence generator for 16 bits with feedbacks from O, 3 and 5 bits. Place it in the cells of block 15 with addresses from 1 to 16, assign number 1 to this generator and write block 1 to block 8 at address 1, and t 16 ,. and in block 9 at O. Then the program in block 4 has the form shown in the table; one.

In the column Perform operations of the table 1 A, B, C, D means the inputs of the adder 2O, - 6 means the contents of the cells of block 15 with addresses 1-6.

Claims (2)

The command number 3 at the output of the decoder 18 generates a control signal which, having passed through multiplexer 21, will cause the appearance of the permissive signal at its output, and in the cell 15 of the unit 15 at address 1 will write the sum modulo two soda of rented cells 1, 3, 4 and f67, the counter 10 will add to the address modifier M unit, after which the new value of the modifier will be written in RAM 9 at address 1. In order to repeat the process it is sufficient in the next word of block 4 in the group of bits to be written. To set the code of the number of the last register size 19. Then the signal will appear, setting the 7Q9 injecting counter 3 to O, and the process will be repeated cyclically. This signal is a sign of the end of the generator clock, and, if necessary, counting the number of clock cycles, it can be used as the input clock counter for the clock counter. In order for the inputs of the adder 2O to be set to a certain position, the cell 07 of block 15 and the zero word of block 8 with the initial filling are written O. This cell should not be used during the generation of generator registers, therefore all generators should have numbers / 1. Similarly, you can organize a ring shift register, Johnson counter, and m; n. register schemes, So, in order to implement, in addition to the nei th register of the solder register with the unit running, located in block 15 in the cells with headers 17–33, assign number 2 to this generator at block 2 in block 8 we write 82 17 and L2 I in block 9 - O. As the initial setup of the register in cells 17 - 2, we write O, in cell 33-1. Then, after the program of work of the first register in block 4 there will be a program of work of the register, is given in Table. 2 To organize Johnson's counter instead of a ring register in the last command, it is enough to write down the table in the preceding command. If necessary, you can organize a number of dependencies using the program. myh registers. So, for example, if in addition to the first two registers we want to organize a 20-bit shift register, whose input must be equal to the injected sum modulo two, the 6th bit of generator number 1 and the 9th bit of generator number 2, then assign number 3 to this register and place it in cells 34 - 53 of block 15, and address 3 in block 8, power on 34, U3 2O, block 9 - O. Then the continuation of the program in block 4 will look like . 3. Similarly, the others are implemented above the denoted generator capabilities. It is noteworthy that the use of modulo-two summation functions for the paTojpa gene is not fundamental, and other suitable combinational schemes can be selected for the organization of nonlinear feedback 78. Thus, the generator has color mode operation. In the first mode, the program is recorded in block 4 of the initial data in blocks 8, 9 and 15. To do this, a control signal is supplied to input 23, which allows writing to blocks 4 and 8, connects the address inputs of blocks 8 and 9 through multiplexer 6, and address inputs block 15 through multiplexer 13. At the same time, multiplexer 21 generates a write enable signal in block 9, and multiplexer 21 produces a write enable signal in block 9, and multiplexers 7 and 14 connect the data inputs of blocks 9 and 15 to logical inputs Oh and addresses respectively. External devices are used to synchronize the recording of the program in 6rtoK 4, while a start signal is given at input 22, and data is received at input 24. At the same time, addresses and data are received to fill in blocks 8, 9, and 15, respectively. At the end of the recording, all the accumulators are transferred to the operating mode. For this, the control signal is removed from 23, a start signal is supplied from input 22 and the first command is set from sensor 2 of the programs. The first group of bits of the command word gives out the register number register to the input of multiplexer 6 and to the address inputs of blocks 8 and 9. According to this number, the first group of bits of block 8 gives the code from the address of the base cell of this register B to the first input of the former 11, second group bits gives the code of the number of bits of this register L, to the second input and to the input of the reception of the counter module Y. To the third input, the code 11 receives the code of the relative address of the selected bit in this generator AOTN. and the fourth input and the input of the one-to-one setting of the counter 1O receive the code of the value of the modifier of addresses of this register M in this cycle, i.e. All O. Fo {liramer 11 forms the executive address for the RAM 15 in accordance with expression (2), i.e. AISP 2 AOTN + M at M U + (M) - (, at + M L, the portable address is given to the input of the mule of the typelexer 13 and then from its output goes to the address input of block 15. A output of block 15 appears recorded in the cell imitating the selected bit of the register. This information is fed to the second input of the adder 16, If the value of the sign server is 0, then the output of the adder 16 does not invert the signal, otherwise the signal is inverted and goes to the D inputs of the triggers register 19. One time from the fourth output of the sensor 2 programs to the input d encoder 18 is supplied. parallel code of the register bit number 19. The outputs of the decoder 18 are connected to the control inputs of the register 19 triggers, so that the signal is written only in that register register whose number corresponds to the code on the input of the decoder 18. This bit can either a trigger connected to the generator outputs, or a trigger connected to one of the inputs of the adder 2O, or a trigger generating a program end signal (the end of the clock), whose input is connected to the opr) 1M (in this proposed device, him) output decoder. According to the SI2 sync pulse, this trigger receives information, and on the falling edge of the next SI1 sync pulse, counter 3 displays the address of the next program word in block 4, if there was no indication of the end of tact in the previous command. Thus, at the beginning of the program, register bits 19 are filled, associated with the inputs of the adder 20, until the program has access to the first register bit 19. In this call, a logical 1 signal is generated, which, passing through multiplexer 21 It generates a control signal to enable writing to block 9 and to enable the counting of the counter 1O. Thus, by the time the front edge of the SI 4 arrives, a new current value of the address modifier of this register is formed at the data input of block 9, and by the beginning of the PPE the data input of block 15 has been received from the output of the adder 2O. the value of the feedback function of this register. After that, on the leading edge of the PPE, the data will be recorded in block 15 and on the leading edge of SI 4, the new modifier value will be written in block 9. Now, if in the next words of the program sensor there are commands to insert cells that simulate this register, the addresses of these cells in block 15 will be modified the new value of M, which is equivalent to shifting this register one digit to the left. Further analogy occurs in the other registers of the required set. One more possibility should be noted, allowing to expand the scope of the proposed generator. If a piece of the program i describing the formation of the feedback function of a given register is repeated several times as compared with the description of the feedback functions of other registers, this will mean that several changes have occurred in this register compared with the rest of the registers. to imitate the registers operating at different clock speeds. All this essentially expands the possibilities of the pre-oscillator generator in comparison with the howling of the generator. Using the generator does not require cumbersome technology. To form N registers with each one of the bits of each register, 4N + N 5N words are required in the drive, a program datapad. With N 16, their placement requires a storage capacity of 81 words (1 word as a program end command). At the same time, if the maximum length of registers does not exceed 27 bits, then the number of bits in a word will be 4 + 7 + 1 + 5 17 bits. If generator 1 is performed on the IC10O element base, then it is permissible to choose the period of the following pulses SI1 - SI4 in 10O NS, which will be between the shifts of simulated registers of magnitude .y approximately 8 ISS. This is an acceptable value to use, for example, in functional control devices of logical nodes. Table P The claims of the invention 1. A multi-functional avoic sequence generator containing a clock pulse generator, the first output of which is connected to the counting input of the address counter, the first installation input of which is connected to the first control input of the generator, the second setting input - with the output of the last register bit and output - with the address input of the program memory block, the information and control inputs of which are connected respectively to the first information and second control inputs of the generator, The second output of the clock pulse generator is connected to the input of the recording of the program memory, the outputs of the character code and the register bit code are connected respectively to the first modulo two first input and the descriptor input, the output of which is connected to the information input of the register whose control input connected to the output of the first modulo adder two, the second input of which is connected to the output of the first memory block, the address and information inputs of which are connected respectively to the outputs of the first and second multiplex The exora, the first information inputs of which are connected to the first address input of the generator, the second information input of the second multiplexer is connected to the output of the second modulo two adder, the information inputs of which are connected to the outputs of the first register group, the outputs of the second group of which are connected to the generator output, and the register clock pulses connected to the second output of the clock generator, the third output of the clock generator is connected to the recording input of the first memory block, output of the first bit eshifratora connected to the first input of the third multiplexer, the second input of which is connected to the input logic generator unit controlling $ poschie input clock generator of the third multiplexer connected to a second input of a control generator distinguishing - in that, for the purpose Rasschirennaya function. capabilities by generating pseudo-random and / or regular sequences with a given number of bits and laws for generating feedback, it additionally contains the fourth and fifth multiplexers, the second and third memory blocks, a counter according to a given module, and an acres generator, And the manager. the inputs of the third and fourth multiplexer and the third block of memory are connected to the second control input of the generator, the output of the code number of the simulated register of the program memory block is connected to the first information input of the fourth multiplexer, the second information output of which is connected to the second address of the generator the generator zero is connected to the first information input of the fifth multiplexer, the second information input of which is connected to the output of the counter in a given module the input of which is connected to the first input of the address resolver and the output of the third memory block, the information input of the co-horns is connected to the output of the fifth multiplexer, the address input to the address input of the second memory block and the output of the fourth multiplexer, the control input of the third memory block 1Ти is connected to counting: the input of the counter according to a given module, with the control input of the first memory block and the output of the third multiplexer, the code output of the relative address is connected to the second input of the address generator, the third input of which En with the input of the counter module according to a given module and with the output of the code of the number of bits of the second memory block, the output of the code of the address of the first bits of which is connected to the quad input of the address generator, the output of which is connected to the second information input of the first multiplexer, the information input of the second the memory unit is connected to the second information input of the generator, the write inputs of the second and third memory blocks and the synchronous input of the counter in a given module are connected to the first, fourth and second outputs of the clock generator, respectively in-.DC pulses. 2. The driver of claim 1, characterized in that the address driver contains three adders and a multiplexer, whose input is connected to the first input of the first adder, the second input is connected to the fourth input of the driver, and the output is connected to the driver, the output of the second adder connected to the first information input of the multiplexer, the second information input of which is connected to the first 4 input of the second adder and the output of the third adder, the first and second inputs of which are connected to the first and second {and 1m inputs of the imager, mp Tille input coupled to a second input of the second adder, whose carry output is connected to the control input of the multiplexer. Sources of information taken BOi attention in the examination 1. Pseudo-random sequences and tables. TIIER, t. 64, 1976 ,. № 12, p. 8O-95. 2.US Patent rit 4О470О8, cl. 235-152, published. 1977 (prototype) 0ut.Z