US3806884A - Logic circuit arrangement for the generation of coded signals of characters - Google Patents

Abstract

This invention is concerned with logic circuit arrangement intended to generate coded signals of characters or functions, capable of being associated with external circuit controlled for example by a character keyboard. Said arrangement is associated with an external fixed matrix memory defining addresses of characters. Said arrangement further comprises an internal memory scoring characters and two dynamic counters which scan cyclically said external memory for transferring the selected address in address registers which control the transfer of characters located in said internal memory.

Description

United States Patent [191 Glay 1 LOGIC CIRCUIT ARRANGEMENT FOR THE GENERATION OF CODED SIGNALS OF CHARACTERS [75] lnventor: Guy-Paul Glay, Argenteuil, France [73] Assignee: Societe DApplications Generales DElectricite Et De Mecanique, Paris, France 22 Filed: Dec. 19, 1972 21 AppL No.: 316,462

[30] Foreign Application Priority Data Jan. 6, 1972 France 72.00326 [52] US. Cl. 340/1725 [51] Int. Cl Gllc 7/00, G1 1c 9/00 [58] Field of Search 340/1725 56] References Cited UNITED STATES PATENTS 3,341,817 9/1967 Smeltzer 340/1725 [451 Apr. 23, 1974 3,344,403 9/1967 Foulger et al 340/1725 3,570,006 3/197] Hoff et a1 .1 340/1725 3,434,112 3/1969 Yen 1 340/1725 3,541,518 11/1970 Bell et a1 340/1725 Primary Examiner-Gareth D. Shaw [57] ABSTRACT 5 Claims, 8 Drawing Figures i oivmou u T M r1 w I mmmmnwm1 806, 884

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GENERATION OFA (HAQMTER m REPETITiOH (CHARACTER mmmrso AT THE ADDRESS 87) GENERATION OFA CHARACTER RESTINQ EPETI on P SH H F DYNAMIC I 01 o as 01 o as u o as a! o COUNTER n, (yum N. (70.5% CYCLE r4- CYCLE$ (BE-A 10 ESE-L "MEL (L E- A BSEL HBIE-L LOGIC CIRCUIT ARRANGEMENT FOR THE GENERATION OF CODED SIGNALS OF CHARACTERS The present invention provides an assembly logic cir cuits arrangement intended to generate coded signals of characters or functions, capable of being associated with external circuits controlled for example by a character keyboard.

Integrated circuits, and especially integrated circuits in technology called metal-oxide-semiconductors or MOS, permit to store the important data and to transfer them rapidly from one circuit to another. Such circuits may therefore be associated with a character keyboard not only to generate coded character signals, but also to generate functions referring to these characters which, in practice, are not realisable with known electro-mechanical devices.

The present invention therefore provides logic circuits permitting the generating of coded signals of characters as well as functions associated with these characters which will be given hereinafter.

The invention will be better understood by referring to the following description and the attached drawings in which:

FIG. 1 shows a plurality of elementary logic circuits used in the arrangement of the invention;

FIG. 2 shows diagrammatically in the form of a block, the circuit according to the invention and a plurality of input and output signals;

FIGS. 30 and 31) show the logic diagram, in the form of blocks, of the arrangement according to the invention;

FIGS. 40, 4b and 5a, 5b show diagrams of signals useful for understanding the operation ofthe arrangement of the invention.

FIG. I shows, in binary logic, a certain number ofdiagrams each corresponding to a logic function. From top to bottom are shown the function of inversion, the function AND, the function OR, the function counting and the function "comparison. The corresponding circuits are therefore an inverter circuit (noted by a small circle), an AND gate, an OR gate, a counter and a comparator. The counter shown a shifting registcr having a plurality of flip-flops mounted in series. The diagram of a single flip-flop is similar but the corre' sponding rectangle has a lesser area. The comparator compares in general two binary numbers and generates an output signal when these two numbers are equal or become equal.

The thick connection of FIG. 1 represents a line transmitting several binary figures or bits" in parallel whilst the thin connection line of FIG. 1 represents a line transmitting a single bit.

FIG, 2 represents, in the symbolic form of a rectangle, the logic circuit LGCl according to the invention and all the signals capable of entering into this circuit or leaving it. These signals have a mnemonic form. All the signals beginning with the letter N (which corresponds to NO") are exchanged with the circuit in the form of their complement. The signal N (EA7) for example is identical with the signal EA7 which in usual notation is the complement or the reverse of EA7. The signals N (EAO) to N (EAIO) are addresses input signals coming from an external memory (exterior to the circuit) the signals N (SAO) to N(SA7) are the output signals providing the addresses of the external memory,

the signals N(SDO) to N(SD7) are output signals or results and, in particular, the coded signals of selected characters. The other signals are the following:

a) Incoming signals:

Clock N (NI I) Selecuon ol the levels of the internal memory N (NI 2) N (AT) Waiting N (AN) Cancellation N (RE) Repetition N (SE) Sequence b) Outgoing signals:

N (PC) Character presence CA Cancelled circuit.

The significance of these signals will be indicated further on.

FIGS. 30 and 3b represent the circuits arrangement according to the invention, on the inside of the rectangle in broken lines. In the chosen example, the number of characters provided is 3X88. The arrangement is controlled by a pulse generator or external clock which generates the signal HO (see FIGS. 50 and Sb) and the different base times. This clock is associated with an external memory Me of 88 binary bits which may be. for example, a read-only memory and which provides the addresses of the 88 characters which are themselves recorded in a read-only internal memory Mi comprising 3 sections or levels Mi], Mi Mi;,, each compartment recording the 88 character codes, each character code comprising 10 binary figures or bits.

This arrangement comprises essentially the readonly memory Mi of 3X88 characters, counters or shift regis ters CNI, CSEA, CDEA, CSSA, CDSA, RD88, a logic selection" circuit LS, flip-flops MC, BSE, BSC, MBSEL, BAT, CAI, CA2, compartors and OR and AND gates. These circuits have the following organisation and functions:

Level counter (CNI): It has 3 flip-flops and permits of addressing one of the three sections or levels of the memory;

Static counter address input (CSEA): It is constituted by l l flip-flops and it permits of addressing one axis, that is to say, one column, of a plane of the memory (each level of the internal memory Mi of 3 X 88 characters is in effect a plane matrix memory of II columns and 8 lines of characters);

Dynamic counter address input (CDEA): It has 1 flip-flops and it provides the first part of the address of the character to be selected, according to the position of a dynamic register;

Static counter address output (CSSA): It has 8 flip flops and it permits of addressing the second axis, that is to say, a line of a plane of the memory Mi;

Dynamic counter address output (CDSA): It has 8 flip-flops and it provides the second part of the address of the character to be selected, according to the position of a dynamic register;

Logic of selection" block (LS): It selects a bit of the word generated by the external memory according to the contents of the counter CDEA;

Register (R088): This is a dynamic shift register of 88 bits.

Further there is provided logic comparison circuits detecting the coincidence of the static and dynamic counters. The dynamic counters are timed by the clock and scan permanently the external memory. When the coincidence of the static and dynamic counters is obtained the static counters (taken together) store the ad- I 1 Selected level Level Level I Level 2 Level 2 NI 2 N 0. Signal Waiting AT This signal, when it is present, prevents any character generation, (1. Signal Cancellation" AN This signal, when it is present, which corresponds to AN 1, controls the initiation of the arrangement and prevents any output of information. 2. Signal "Repetition" RE The presence of this signal (RE=l permits of generating in a repeated manner the code of the selected character after the appearance of this signal. This signal is taken into account if it is applied to the arrangement a short time before the disappearance of the signal PC. f. Signal Sequence" SE The presence of this signal after the disappearance of the signal PC controls the generation of the character contained in the following address of the internal memoryv This signal is taken into account if it is present a short time before the disappearance of the signal PC.

g. Address Input" Signals EAO to EAltl These are signals coming from the external memory Me, this memory being addressed by the signals 8A0 to SA7. In other words, the dynamic counter CDSA deter mine the address of one of the 8 numbers of I 1 bits of the external memory, and this number is then transferred into the logic selection circuit in the form of one of the signals EAO to EAlO.

2/ Output Signals a. Signal Character Presence" PC:

This signal, for PC=l, indicates that a character has been transferred to the output terminals of the data through the channel Ca b. Signals Output Data" SDO to SD8:

These are the character code signals coming from the internal memory Mi and which are applied in parallel on nine outputs for each character through the outlet channel Ca 0. Signal "Cancelled Circuit" CA:

This signal is generated in response to a cancellation control (AN=I The presence of this signal (CA=I) indicates that the signals SD and PC are zero.

d. Signals Output Addressing" SA!) to SA7:

These signals control the addressing of the external memory. The said signals correspond to the contents of the counter CDSA.

It must be pointed out that the signals EAO to EAHI are transferred into the logic selection circuit only when the signals SAD to SA7 correspond to the number (one number among eight) which it is desired to select in the external memory and which corresponds in its turn to the address of the character which it is desired to select in the internal memory of characters.

The operation of the logic arrangement of the invention will now be described. Said arrangement comprises individual mode which are the following: Initiating (or starting), rest, generation of a character, generation of a character by repetition, generation of a sequence of characters, waiting.

In each mode, the operation is determined by a sequence of phases p (see above) each composed of four time bases t to 1, corresponding to:

r, Rest I, Test of the selected bit T of the external memory t Beginning of the signal Character presence, if a character must be selected I, End of the signal Character presence, incre mentation of the counters and shifting of the register at the time of disappearance of I, (see FIG. 4, signal HO).

These modes take place in one or several periods P, each equal to 88 phases p.

The logic operations effected in these modes are the following:

Initiation The system is in course of initiation when the signal AN is present and has been taken into account by the logic.

The list of operations effected during each phase is the following:

I. Control of setting then blocking of the flip-flops MC, BSE and BSC.

2. Introduction of an 0 state in the registers and counters (RD88, CDEA, CSEA, CDSA and CSSA).

The last phase of the initiation is effected when the signal AN=0 is recorded in CA1.

At the end of this phase:

a state 0 is introduced in RD88 a state 1 is introduced in CDEA, CSEA, CDSA and CSSA.

Rest

This method of operation is permanent when BSELNSR 0 (it is assumed that AT=O), therefore when EAO to EAIO 0 permanently.

The flip-flops MC, BSE and BSC are in the state 0.

Contents of the counter CDEA Selected CDEA CDEA 8 CDEA CDEA CDEA blt I m cos. 2 1 0 n u 00 1 EA 0 o u 01 0 m n on 0 EA 9 (J (N) 0 EA [0 Character Generation In order that a character generation phase may be carried out, it is necessary for BSELN SR 1 (it is assumed that AT=0).

The listing of controls effected during the character generation phase is as follows:

1. At time the filling of CNI according to the signals Ni 1 and N1 2 is interrupted when CMCl l. The filling is effected according to the following table:

NI! Nll CNIZ CNll CNI!) (l D 0 U l O l 0 l D l X l U D CNI 0, CNI l and CNl 2 being the three flip-flops of the counter CNI.

2. At the time of disappearance of T (end of 1 the flipflops MC and BSC are set up in the state 1 (that is to say, brought or kept at the state I).

3. At the time of disappearance of HC (end of t the flip-flops MC and BSC are set up in the state 0 the counters CDEA, CSEA, CDSA and CSSA are incremented the contents of MBSEL (l logic) is introduced into the dynamic register (RD88).

Generation of a Character in Repetition In order that this mode of operation may be effective, it is necessary for the signal RE to be present at the time of the end ofa character generation. In this case, at the time of the disappearance of the signal HC of a character generation phase, the following logic operations are effected:

only the flip-flops BSC is set up in the state 0 the dynamic counters CDEA and CDSA are incremented (CSEA and CSSA are stable) the contents of MBSEL (l logic) is introduced into the dynamic register RD88.

The next character will only be able to be generated when the counters CDEA and CSEA as well as CDSA and CSSA are in coincidence (88th phase after the initial character generation phase).

During this 88th phase the following logic operations are effected:

i. Generation of a character 2. Not resetting of MC at the time of the disappearance of HC 3. Continuation of this mode of operation If RE 0:

1. Character generation step 2. Resetting of MC at the time of the disappearance of HC 3. Passing to a different method of operation.

Generation of a Sequence of Characters This mode of operation is effective when the signal SE is present at the time of the ending of a character generation. It has a priority with regard to the mode of generation of a character in repetition according to the following table:

SF. RH Method of operation [1 (l Generation of a character 0 l Generation of a character In repetition l X Generation of a sequence of characters If SE is present at the end ofthe time 1 ofa character generation phase: the flip-flop BSC is set up in the state 0 the flip-flop BSE is set up in the state I the dynamic counters are incremented the static counters are incremented, and in addition l. If CNI 2 0 incrementation of CNI, only 2. If CNl 2 l incrementation of CNI, CSEA and CSSA the contents of MBSEL is introduced into the dynamic register.

The next character will only be able to be generated when the counters CDEA and CSEA as well as CDSA and CSSA are in coincidence during a phase.

The generation of another method of operation (rest or character generation) will take place when SE is absent at the time of disappearance of HC of a character generation phase.

Waiting This mode of operation is effective when the signal AT is present.

The operating characteristics of this mode are the following:

i. The flip-flops MC, BSE and BSC are maintained in their state 2. The dynamic counters are incremented at the time of the end of each phase 3. The static counters CSEA and CSSA are incremented at the time of the end of each phase if MC 4. The dynamic register is closed (introduction of SR to each phase in the register) The generation of another mode of operation is effective at the time of the end of the phase following the disappearance of the signal AT.

What we claim is:

l. A logic circuit for generating coded signals con trolled by a pulse synchronization generator and by external signals, comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal read-only matrix memory having at least p multiple lines and q multiple columns and storing pq characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and q columns of said internal memory, and two dynamic counters having the structure of shift registers connected to said external memory which scan cylically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qt of the selected address (pi, qi) in said address registers which control the transfer of the selected character of the internal memory to an output line when the contents of said address registers are equal to the contents of said dynamic counters.

2. A logic circuit according to claim 1, wherein an external repetition signal having the vinary value I emitted during several periods P controls the transfer of the selected character outside the internal memory all the periods P,

3. A logic circuit according to claim 1, wherein an exterior signal applied to the two dynamic counters controls their blocking, preventing any transfer ofinformation outside the internal memory.

4. A logic circuit for generating coded signals controlled by a pulse synchronization generator and by external signals, comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal readonly matrix memory having at least p multiple lines and q multiple columns and storing pq characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and the q columns of said internal memory. and two dynamic counters having the structure of shift registers connected to said external memory which scan cyclically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qi of the selected address (pi, qi) in said address registers, and comparator circuits which compare the contents of the dynamic counters and of the corresponding address registers, the output signals of these comparators controlling the generation of a character presence signal when the said contents are equal and consequently when the character signals are transferred to the outside of said arrangement.

5. A logic circuit for generating coded signals controlled by a pulse synchronization generator and by external signals, comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal read-only matrix memory storing characters and having supplementary binary positions storing a sequence of determined characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and q columns of said internal memory, and two dynamic counters having the structure of shift registers connected to said external memory which scan cyclically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qi of the selected address (pi, qi) in said address registers, an external signal controlling the successive transfers of the characters of said sequence outside of said arrangement, each character of this sequence being transferred during one period P.

a: 1: a: a

Claims (5)

1. A logic circuit for generating coded signals controlled by a pulse synchronization generator and by external signals, comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal read-only matrix memory having at least p multiple lines and q multiple columns and storing pq characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and q columns of said internal memory, and two dynamic counters having the structure of shift registers connected to said external memory which scan cylically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qi of the selected address (pi, qi) in saId address registers which control the transfer of the selected character of the internal memory to an output line when the contents of said address registers are equal to the contents of said dynamic counters.

2. A logic circuit according to claim 1, wherein an external repetition signal having the vinary value 1 emitted during several periods P controls the transfer of the selected character outside the internal memory all the periods P.

3. A logic circuit according to claim 1, wherein an exterior signal applied to the two dynamic counters controls their blocking, preventing any transfer of information outside the internal memory.

4. A logic circuit for generating coded signals controlled by a pulse synchronization generator and by external signals, comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal read-only matrix memory having at least p multiple lines and q multiple columns and storing pq characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and the q columns of said internal memory, and two dynamic counters having the structure of shift registers connected to said external memory which scan cyclically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qi of the selected address (pi, qi) in said address registers, and comparator circuits which compare the contents of the dynamic counters and of the corresponding address registers, the output signals of these comparators controlling the generation of a character presence signal when the said contents are equal and consequently when the character signals are transferred to the outside of said arrangement.

5. A logic circuit for generating coded signals controlled by a pulse synchronization generator and by external signals, comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal read-only matrix memory storing characters and having supplementary binary positions storing a sequence of determined characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and q columns of said internal memory, and two dynamic counters having the structure of shift registers connected to said external memory which scan cyclically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qi of the selected address (pi, qi) in said address registers, an external signal controlling the successive transfers of the characters of said sequence outside of said arrangement, each character of this sequence being transferred during one period P.

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