SU1239833A1 - Synthesizer of frequency-modulated signals - Google Patents

Abstract

The invention relates to the field of radio engineering. The frequency grid step decreases and the frequency change rate increases. The device comprises a frequency code generation unit 1, a drive of 2 codes, a memory block 3, registers 4 and 5 of the frequency code, a nickname 7 clock frequency. The goal is achieved by the introduction of a digital comparator 6 and a control unit 8, including generators 9, 16 pulses, counters 10 and 11, triggers 12 and 13, keys 14 and 15, switch 17, EL or 18. The device operates in 2- x modes: 1) the mode of generating control signals and recording them in block 3 is carried out at a low clock frequency specified from generator 9; 2) the mode of reading signals from block 3 occurs at a high frequency specified from source 7. The unit 8 coordinates the operation of the device. 1 Cp f-ly, 1 ill. with "(L Vytod tc with with 00 with with

Description

. one

The invention relates to radio engineering and can be used to synthesize frequency modulated (FM) signals.

The purpose of the invention is to reduce the step of the frequency grid and to increase the rate of change of the frequency.

The drawing shows a structural electrical circuit of a synthesizer of frequency-modulated signals.

The circuit contains a frequency code generation unit 1, a storage drive 2 codes memory unit 3, first register 4 frequency codes, second register 5 frequency codes, digital comparator 6, clock frequency source 7, control unit 8. In this case, control unit 8 includes the first 9 pulse generator, the first Yu and second 11 counters, the first 12 and second 13 triggers, the first 14 and second 15 keys, the second generator 16 pulses, the switch 17 and the element OR 18,

The FM signal synthesizer works as follows. .

An FM synthesizer is designed to generate FM signals with an initial frequency f, a rate of change of frequency V and a duration determined by pulses coming in and from the second generator 16 pulses. The immediate formation of FM signals with the proposed execution of control block 8 is preceded by the time, where N is the counting coefficient of the first counter 11, f. - the frequency of the clock source 7, during which the codes generated by the synthesizer of the frequency-modulated signals correspond to the signal of the fixed frequency f,. This section is usually required based on the processing conditions and also to minimize the transients at the beginning forming the actual FM signal. This circumstance is largely and determines the structure of the control unit 8,

The FM signal synthesizer operates in two modes: generation of control signals and their recording into memory block 3 and control signal reading mode from memory block 3.

The formation and recording of control signals in memory block 3 is carried out at a low clock frequency, for 39ВЗЗ ..2

9 impulses given from the first-about generator. The readout of the control signaling signals from memory 3 occurs at a high frequency set from source 7, with a pulse postullency from the second generator of 16 pulses determining the length of the guest generated by the FM signals. The operation of the signal synthesizer in two modes 0 is coordinated by the control unit 8.

At the moment the initial frequency code V. f changes in the first register 4 or the FM speed code K in the second register 5, a command pulse is generated in the general comparator 6, which

puts the device in the mode of forming y right signals and recording them in block 3. This impulse sets the zero on the kopitel 2 codes of the first counter 10 through the OR 18 element of the second counter 1 1 and through the first trigger 12, the block 1 of forming the frequency code, the output of which at the same time contains the initial frequency code Kg, In addition, this pulse changes the state of the second trigger 13, resulting in the passage of clock pulses from the output of the first 30 generator 9 pulses to the counting inputs of the first 10 and second 11 counters, as well as to the clock inputs of the first register 4, the second register 6 , b lock 1 formation, accumulator 2 codes and to the input of the recording resolution

35

3 memory blocks „

With the arrival of these clocks at the first 10 and second 11 counters, their contents begin to increase and in block 3 of the memory at the address generated in the second counter 11, the current frequency code K j is recorded on the information input. K j. and the phase code K from the output of the drive 2 codes. When a pulse arrives at the input of the first counter 10, it overflows, the first trigger. 12 changes its state and the command is removed from the formation block 1

setting zero,. In this case, at the output of the formation unit 1, the code Kg K + i- 1, 2, 3 begins to form ...,,,, Capacity N of the second counter 11 and coinciding with

its number of addresses of the memory block 3 is chosen so as to ensure the formation of linear FM signals of the maximum necessary length

T. „КС (Na Ч) .ц Overall the maximum duration of the signal, taking into account the time during which

memory block 3 K codes are recorded

t.

and K, formed on a plot with a fixed frequency, is equal to

.Max.

when the second counter 11 overflows, coming from the first generator 9 pulses H and the clock pulse, the second trigger 13 changes its state, as a result of which the first key 14 blocks the flow of pulses to the counting input of the first counter GO, switch 17 connects the counting input The second counter 11 to the source 7, the second key 15 is opened, the second counter 11 through the OR element 18 is set to the zero state, which ensures that the device is switched to the control signal readout mode from the memory block 3.

The readout of the control signals from the memory block 3 is carried out at the time of the appearance of gates with a duration T ,,,; .

At the same time, the content of the second counter 11 begins to increase with the arrival of each pulse from the source 7, as a result of which the control codes K and K recorded in it from block 3 are retrieved. At the end of the gates, the second counter 11 is each time set to the zero state of the JBoe. Device operation, c. This mode continues until at least one of the input codes K. or K;,.

The digital comparator 6 is designed to form a command pulse that translates the synthesizer into the formation mode, the control codes and their recording in the memory block 3. This mode is switched every time when one of the K and / or K codes changes. Digital comparator 6 has two inputs, one of which receives the K and K codes from the signal synthesizer input to the other via the parallel buses — the same codes , but after a delay of their -start in the first 4 and second 5 registers. A command pulse in digital comparator 6 is generated each time at least one of the bits of the Kj or Ku codes undergo a change. Technically such a digital comparator

can be implemented on typical microchips, and the number of bits to be analyzed can be increased.

The second generator of 16 pulses - 5 is a normal pulse generator,

the duration of which determines the duration of the generated FM signals. The output of the proposed signal synthesizer can be used to access a permanent memory device (ROM), which contains a table of values of the sinusoidal function for controlling the phase shifter to control the operation of a fractional divider with a variable division factor (not shown) .

The use of the proposed device 2Q allows the formation of time-limited signals with high resolution in frequency and frequency modulation rate.

25 Formula of invention

one . A frequency modulator-.i synthesizer of a single signal containing serially connected first frequency code registrar, a frequency code generation unit and a code accumulator, the code output of which is connected to the first group of information inputs of the memory unit, second frequency code register, output which is connected to the second code input of the frequency code generating unit, and the source of the clock frequency, characterized in that, in order to reduce the frequency grid step and increase the speed of the frequency change, a digital comparator is entered into it and lock control, the inputs of the first and second frequency sub-code registers. kaocheny to p. the first input of the digital 5 comparator, to the second input of which the outputs of the first and second frequency code registers are connected, the input of the zero setting of the code accumulator is combined with the installation input of the zero of the control unit 50 and connected to the output of the digital comparator, the output of the clock frequency source is connected to the clock the input of the control unit, the first output of which is connected to the input of the setup 55 of the frequency code generation unit, clock inputs of the first and second frequency code registers, the frequency code generation unit, accumulator

40

The code bodies and the memory block are combined and connected to the second output of the control unit, the code output of which is connected to the address input of the memory unit, the second group of information inputs of which are connected to the output of the frequency code generation unit.

.2. Synthesizer 1, characterized in that the control unit comprises a first pulse generator connected in series, a first key, a first counter and a first. vm trigger, the output of which is the first output of the control unit, successively connected to the second pulse generator, the second key, the OR element, the second counter, the second trigger and the switch, with. This yQTa is the new input of the first counter, second- Editor A. Shandor Order 3407/55

Compiled by Y. Kovalev-.

Tehred O. Sopko Corrector-E. Sirohman

ZGirazh 816.Subscription

VNIZhSH State Committee of the USSR.

on business from acquisitions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5

. Production and printing company, Uzhgorod, Projecto st., 4.

The first input of the first trigger, the second input of the second trigger and the second input of the I.PI element are combined and are the input of the zero setting of the control unit, the second input of the first key is connected. dinene with the first output of the second trigger, the second output of which is connected to the second input of the second key, the output of the first pulse generator is also connected to the first signal input of the switch, the second signal input of which. is the clock input of the control unit, the output of the switch is connected to the counting input of the second counter, the serial outputs of which are the code output, the control unit, and the output of the first switch - the second output of the control unit.

Claims (3)

Claim 1 . A synthesizer of frequency-modulated signals containing the first register of the frequency code in series, a frequency code generation unit and a code store, the code output of which is connected to the first group of information inputs of the memory block, the second frequency code register, the output of which is connected to the second code the input of the frequency code generating unit, and the clock source, characterized in that, in order to reduce the frequency grid spacing and increase the rate of frequency change, a digital comparator and unit at the same time, the inputs of the first and second 'frequency code registers are connected to the first input of the digital comparator, to the second input of which the outputs of the first and second code' frequency registers are connected, the zero setting input of the code drive is combined with the zero setting input of the control unit and connected to the output of the digital comparator, the output of the clock source is connected to the clock input of the control unit, the first output of which is connected to the zero setting input of the frequency code generation unit, clock inputs of the first and second register frequency code ditch, block for generating a frequency code, store s The code and memory unit are combined and connected to the second output of the control unit, the code output of which is connected to the address input of the memory unit, the second group of information inputs of which are connected to the output of the frequency code generating unit. .2. Synthesizer pop. 1, characterized in that the control unit comprises a first pulse generator, a first key, a first counter, a first counter and a first trigger, the output of which is the first output of the control unit, a second pulse generator connected in series, a second key, an OR element, a second counter, a second trigger and switch, when. In this case, the input of the first counter, the second input of the first trigger, the second input of the second trigger and the second input of the OR element are combined and are 5 input control unit zero, the second input of the first key soy-. dinen with the first output of the second trigger, the second output of which is connected to the second input of the second key, 10, the output of the first pulse generator is also connected to the first signal input of the switch, the second signal input of which is the clock input of the control unit, the output of the switch 15 is connected to the counting input of the second counter, the bit outputs of which are the code output of the control unit, and the output of the first key is the second control unit output.