JP2924968B2 - Time interactive simulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a time bidirectional simulation method for verifying a past logical value, a time bidirectional simulation method that can not only advance the circuit operation in the time direction but also go back to the past. A simulation device for converting a logic circuit into a simulation model and simulating the logic circuit using the simulation model, wherein each register in the logic circuit to be originally simulated is provided. Unit for converting a simulation start clock time into a simulation model including a memory, a counter for measuring a clock time, and a control means for controlling the memory and the counter. Initialize the counter and set the clock time to the While the timer is counting, the value to be taken by each of the register units at the clock time is changed, and the state to be taken by each of the register units at each clock time T counted by the counter is written into the address T of the memory. The memory has a configuration capable of reading an arbitrary specified address content of the memory, and reading a simulation result of each of the register units at an arbitrary clock time N from an address N of the memory, thereby obtaining the logic. Verifying the simulation result of the circuit at an arbitrary clock time at random, verifying the simulation result of the logic circuit in a forward direction from the arbitrary clock time, and reversing the simulation result of the logic circuit in the reverse of the simulation flow. To verify while going back to To.

[Industrial applications]

The present invention relates to a logic simulation method for realizing the operation of a logic circuit on a computer, and more particularly, to a time bidirectional simulation method for verifying a past logic value.

Logic simulation is a technique for realizing a designed logic circuit on a computer before realizing the function on an integrated circuit.

In general, a logic circuit is a sequential circuit including a combinational circuit and a register unit for holding a result of the combinational circuit. A logic simulation is performed at a logic state at an arbitrary time generated in the circuit, that is, a logic state set in each register unit. Verify the state. Logic simulation that faithfully represents the target circuit is used to find and correct circuit design errors, but good inspection in the process of finding a malfunction during the simulation and then extracting the cause is important. . Therefore, a demand for a time bidirectional simulation method capable of advancing or returning a circuit operation in the time direction is extremely important.

[Conventional technology]

The logic simulation method includes a compilation method and an event drive method. The compile method is a method in which the instruction code of the operation for each element is sequentially generated by assigning the level of the execution order of the elements, and the event drive method is based on a set in which the signal value changes at the present time and the influence of the set. Then, a set of pairs of signal lines and signal values of changing signals is faithfully represented in the computer including the connection state of the logic circuit.

In event-driven system, there is representation of the data structure of the memory for describing the structure of the target circuit in the simulation, an event when the signal value obtained at time T ₀ is different from the value obtained before that As occurrence, the occurrence of the event is described in time. For this purpose, an event list is created in the memory in which a series of events occurring at each time is linked by a pointer.

However, in the conventional method, a logic simulator that advances the circuit operation in the time direction is used, and since the contents of the registers in the circuit store only the contents set at each time, the simulation does not go back to the time. For example,
Even if it is desired to return to time 99 at the point of time 100, it is necessary to re-execute the simulation from time 0 to time 99.

[Problems to be solved by the invention]

Therefore, the conventional method has a problem that it takes much time when the target logic circuit becomes large-scale and the input sequence becomes long. Even in the method in which most of the circuit operation is stored for all times by the event list, the circuit operation is only advanced in the time direction, so that not only a very large capacity storage device is required, but also the circuit There has been a problem that it takes a lot of time to search and find design errors.

The present invention not only advances the circuit operation in the time direction,
It aims at a time bidirectional simulation method that can go back to the past.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

The conversion unit 12 converts each register unit 11 in the logic circuit 10 to be originally simulated from the memory 2, the counter 1 that measures clock time, and the control unit 6 that controls the memory 2 and the counter 1. Into a simulation model.

The control means 6 initializes an arbitrary simulation start clock time in the counter 1 and changes the value to be taken by each of the register units 11 at the clock time while causing the counter 1 to time the clock time. The state to be taken by each of the register sections 11 at each clock time T counted by the counter 1 is written and stored in an address T of the memory 2 and the contents of a specified arbitrary address in the memory 2 are read out. Has a possible configuration.

Then, by reading the simulation result of each register unit 11 at an arbitrary clock time N from the address N of the memory 2, the simulation result of the logic circuit 10 at an arbitrary clock time is randomly verified. It is possible to verify the simulation result of the logic circuit 10 in the forward direction from an arbitrary clock time and to verify the simulation result of the logic circuit 10 while going back in the direction opposite to the flow of the simulation.

[Action]

In the present invention, each register unit 11 in the logic circuit 10 to be originally simulated is converted by the conversion unit 12 into a memory 2, a counter 1 for measuring clock time, and a control for controlling the memory 2 and the counter 1. It is converted into a simulation model comprising the means 6. Then, the control means 6 initializes an arbitrary simulation start clock time in the counter 1 and causes the counter 1 to count the clock time while determining the value to be taken by each of the register units 11 at the measured clock time. The state to be taken by each register section 11 at each clock time T counted by the counter 1 is written and stored in an address T of the memory 2, and the content of a specified arbitrary address in the memory 2 is changed. Is controlled to be read. Then, by reading the simulation result of each register unit 11 at an arbitrary clock time N from the address N of the memory 2, the simulation result of the logic circuit 10 at an arbitrary clock time is randomly verified. It is possible to verify the simulation result of 10 in the forward direction from an arbitrary clock time and to verify the simulation result of the logic circuit 10 while going back in the direction opposite to the flow of the simulation.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is an embodiment diagram for explaining the concept of the present invention. In the figure, (a) shows a register included in a target circuit for performing a logic simulation, and (b) shows a register model when the register is modeled. The register is a register for setting N-bit data D _in 1, D _in 2,..., D _in N at the rising edge of the clock, and outputs D _out 1, D _out 2 _,. Expressed by N. Bit i
D _in i is the D type flip-flop DFFi Di
Connected to the input, the clock signal is input to clk and the output signal D _out i is output from Qi. When the clock signal input to clk rises, the input signal D _in i at that time is set in the flip-flop DFFi, is outputted as the descriptions D _out i is set. As described above, the n-bit register composed of the D-type flip-flop is actually designed, and is a register to be simulated in the logic simulation. In the present invention, this register is modeled on the register model shown in FIG. (B) The register model shown in the figure comprises a counter 1, a memory 2, and a random circuit 6. The counter 1 is an address counter for the memory 2, the counter output D 0 is connected to the memory ADRS, and the memory 2 writes or reads to an address specified by the contents of the counter 1. That is,
If the write enable (WE) is enabled at the address specified by the counter contents, the input signals D _in 1 to D _in N are written to that address. If the write enable is disabled and in the read state, the contents of the address specified by the contents of the counter 1 are output to the outputs D _out 1 to D _out N of the memory 2. However, it is assumed that the memory is in a readable or writable state when the chip selector terminal CS is 1.

As described above, in the present invention, the register part of the synchronous circuit inside the target circuit is modeled by the memory 2 and the counter 1 representing the clock time as shown in FIG. Then, an operation is performed so that the state at a certain clock time T is stored in the address T of the memory 2. In other words, when proceeding in the time direction,
The counter 1 is incremented by 1 according to the clock, and the content of the counter is used as an address to write the input value into the memory when WE = 1, and to output it to the output when WE = 0. That is, the counter 1
Since the clock of the CLOCK is input to the clk terminal of the counter, if the clock is input, the counter is incremented by 1 when the clock is input, the content is output via D0, and the content is output to the ADRS terminal of the memory 2. Given. After the clock rises, an inverted signal of the clock signal is generated at the output of the inverting circuit 4 after a delay time. If the output of the inverting circuit 3 is 1, the clock signal itself is also input to the input terminal of the AND circuit 5, and the inverted output is also input to the AND circuit 5, so that the output of the AND circuit 5 is written. The enable signal WE generates a positive pulse and enters a write enable state. Thus, the counter is incremented by one by the clock, D _in N it from D _in 1 as an address
Is written into the memory 2 when WE = 1. Then, since the first period of the line enable WE is a small pulse width, the contents of the memory 2 from D _out 1 becomes WE = 0 to D _out N is released after the pulse generator.

To return to an arbitrary clock time, use the counter 1
Input the T of the set time to D1. By setting the time setting signal 7 input to the MOD terminal to 1 and setting the counter 1 to the set mode, the contents of the set time T are written in the counter. When the time setting signal 7 is 1, the output of the inverting circuit 3 becomes 0 and the output of the AND circuit 5 also becomes 0, and WE = 0, that is, the read mode is set. Therefore, the address of the memory 2 is addressed by the address T of counter 1 which represent the time T set, the contents of which are read out from the D _out 1 to D _out N. This means that it is possible to return to an arbitrary clock time, which means that the contents of the register at time T are read from the memory 2. That is, by outputting the contents of the time T from the memory 2, it is possible to perform a logic simulation for the built-in combination circuit connected to the output of the register in FIG. The result of the logic simulation at the time T is output, which makes it possible to easily return to the state at the time T in the past.

FIG. 3 (a) is an embodiment diagram of a target circuit used in the logic simulation method of the present invention, and FIG. 3 (b) is an implementation of a time bidirectional simulation model for the embodiment diagram of FIG. 3 (a). It is an example figure. In the circuit of FIG. 3 (a), DFF1, DFF2, and DFF3 are D-type flip-flops and constitute a 3-bit register as a whole. CL
The OCK signal is a clock signal input to clk of each flip-flop. D1, D2, and D3 are input terminals of which D2 and D3 receive externally input signals * ENABLE and DATA-IN. The signal input to D1 is a signal called DATA-OUT, which is the output of the NAND gate g4. The input of the lower random circuit 8 is connected to the output of the register, and its output is the input of the first DFF1 of the same register. The input of the inverting circuit g1 is Q2, which is connected to one terminal of the NAND gate g2, and the other input of g2 is Q3. The NAND gate g3 is connected to the output of g1 and Q1. The outputs of g2 and g3 are the inputs of the NAND gate g4, and the output of g4 is the input of DFF1 in the form of being fed back as DATA-OUT. The sequential circuit provided in this manner is composed of the random circuit 8, that is, g1, g2, g3, and g4, which are combination circuits, and a register of a synchronous circuit connected to the combination circuit.

FIG. 3 (b) shows a model when such a sequential circuit uses the time bidirectional simulation of the present invention. G1, g2, g3, g of the combinational circuit originally included in the target circuit
4 is mapped as it is, but 3 included in the target circuit
The two D-type flip-flops, ie, registers, are replaced by the register model shown in FIG. The input of the memory 20 is 3 bits and is D1, D2, D3. The input D1 is connected to the output line of g4 which is the output of the combinational circuit, and the inputs D2 and D3 are * ENABLE and DATA-IN which are external inputs of the target circuit. Since the outputs of the target circuit are Q1, Q2, and Q3, the outputs of the memory 20 are correspondingly Q1, Q2, and Q3.
That is, Q1 is the input of g3, Q2 is the input of g1 and g2, and Q3 is the other input of g2. The outputs Q1, Q2, and Q3 of the memory 20 correspond to the outputs Q1, Q2, and Q3 of the D-type flip-flop in FIG. The counter 19 gives the address of the memory 20.
What controls it is the inverting circuits 22, 22 and AND gate 2.
4 The set time is input to the D1 terminal of the counter 19 and the MOD
Is a time setting terminal. The memory 20 operates to store the state at the clock time T at the address T. When proceeding in the time direction, the time setting mode is 0, and therefore,
1 is input to the center terminal of the AND gate 24. At this time, the counter 19 cannot set the set time,
Each time a clock is input, it counts up. When the clock rises, the clock signal is directly input to the ant gate 24, and its inverted output is input to the same AND gate 24.
That is, a pulse of WE = 1 corresponding to the delay time of the inversion circuit 23 is input to the write enable signal. At this time,
The output of g4 and the signals of * ENABLE and DATA-IN, which are external inputs, are written into the inputs D1, D2, and D3 of the memory 20, respectively. This corresponds to a set of the DATA-OUT signal, the ENABLE signal, and the DATA-IN signal input to the register when the clock signal rises in the circuit of FIG. In the target circuit, these set contents are output to Q1, Q2, and Q3. Similarly, FIG. 3 (b)
In this circuit, the contents from the memory 20 are given as Q1, Q2, and Q3. In this case, the delay time of the register corresponds to the delay time of the memory. In the target circuit, the output of the D-type flip-flop is input to the random circuit 8, and Q1, Q
2, The logic corresponding to the logic state of Q3 is output from the NAND gate g4. Similarly, in FIG. 3B, the contents determined by the logic states of Q1, Q2, and Q3 output from the memory 20 are output to the output terminal of g4. The output states Q1, Q2,
Since Q3 has the same logical state as Q1, Q2, and Q3 of the target circuit, g4
Is also the same as the output of the target circuit. The output of g4 is input to D1 in the target circuit. Correspondingly, the output of FIG. 3B is input to the D1 terminal of the memory 20. In the target circuit, the logical state of D1 is set to DFF1 at the next rising edge of the clock, and the contents of the previous DFF1 are erased. However, in the time bidirectional simulation model of FIG. 3B, the value of the counter 19 is incremented by 1 as the address count. That is, since the clock rises again and the write enable is output as a pulse, the contents of D1 are written to the address counted up at the rise of the clock, that is, the address incremented by one from the previous address. At this time, if the external input DATA-IN or * ENAB
If the LE signal has also been updated, new contents are written to the counted up address. Of the previous clock state
D1, D2, and D3 disappear from the D-type flip-flop in the target circuit, but remain at the previous address because the memory 20 is used in the model. Therefore, if the content of the counter 19 is reset to the value before updating, the register content of the target circuit at the past time can be set again. That is, if an arbitrary value T is set as the set time in the counter 19, the content corresponding to the set time T can be output from the memory 20. That is, if the time setting terminal is set to 1 and the set time at that time is set from D1, the set contents are given to the memory address from D0, and the contents at that time are output from the outputs Q1, Q2, Q3 of the memory 20. You. When the time setting terminal is 1, the output of the inverting circuit 22 is 0, so that WE = 0 and the read mode is set.

As described above, in the present invention, it is possible to advance the simulation of the target logic circuit in the time direction, or to set the time T back to an arbitrary time T, and to output the contents at that time T from the memory 20. . Since this output becomes the input of the combination circuit g1, g2, g3, g4 in the same logic circuit, the output state at that time can be generated from the combination circuit. This means that the logic state of the target circuit at any time can be reproduced. That is, in the present invention, when it is desired to return to time 99 at time 100, the time can be easily returned to time 99 by setting the time to the set time 99 and inserting 1 into the time setting signal. Unlike the conventional case, there is no need to re-execute the simulation that advances the time direction from time 0 to 99 again.

As described above, in the present invention, all the registers in the logic circuit are modeled by the connection between the counter and the memory, and the contents of the register are stored at the address of the memory addressed by the counter content of the clock time.
It enables realization of simulation in both directions.

〔The invention's effect〕

According to the present invention, not only the circuit operation is advanced in the time direction but also the state can be easily returned to the past state by forming the register of the target circuit as a model and cascading the counter and the memory. Therefore, when a circuit design error is found and corrected by logic simulation, the malfunction can be easily found at the time of correction, and the operability in the process of extracting the specific design error that causes the error is extremely good, and the time bidirectional simulation is easy, and Can be fast.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 (a) is a circuit diagram of a register to be simulated by the present invention, FIG. 2 (b) is a circuit diagram of a register model of the present invention, FIG. FIG. 3A is a block diagram of one embodiment of the present invention, and FIG. 3B is a circuit diagram of a bidirectional time simulation model according to the present invention. 1 ... Counter 2 ... Memory 6 ... Control means 10 ... Logic circuit 11 ... Register unit 12 ... Exchange means

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50

Claims (5)

(57) [Claims] 1. A simulation apparatus for converting a logic circuit into a simulation model and simulating the logic circuit using the simulation model, wherein each register unit in the logic circuit to be originally simulated includes a memory, A conversion unit configured to convert into a simulation model including a counter that measures a clock time and a control unit that controls the memory and the counter; the control unit initializes an arbitrary simulation start clock time in the counter; While the clock time is being counted by the counter, the value to be taken by each of the register units at the counted clock time is changed, and the state to be taken by each of the register units at each clock time T counted by the counter is determined by Write / write to memory address T And at the same time, has a configuration capable of reading an arbitrary specified address content of the memory, and by reading a simulation result of each register unit at an arbitrary clock time N from the address N of the memory, Verifying a simulation result at an arbitrary clock time at random, verifying a simulation result of the logic circuit in a forward direction from an arbitrary clock time, and verifying a simulation result of the logic circuit in a direction opposite to the flow of the simulation. Time bidirectional simulation device that enables verification while going back to 2. In the simulation model, a data write signal and a data read signal line of the memory correspond to a data input signal line and a data output signal line of each of the register units, respectively, and the output signal of the counter is 2. The time bidirectional simulation apparatus according to claim 1, wherein the time bidirectional simulation apparatus is input to a memory as an address signal. 3. The simulation model, wherein the counter inputs a clock signal synchronized with the clock time, a set value signal, and a mode setting signal for designating the presence / absence of a time setting mode. When the mode is not the setting mode, the number of input pulses of the clock signal is counted, and the counted value is output to the memory as a write address signal. When the time setting mode is set, the count value is designated by the setting value signal. The time bidirectional simulation apparatus according to claim 1, wherein a value is set, and the set value is output to a memory as a read address signal. 4. When the mode setting signal is not the time setting mode, the control means generates a pulse from the clock signal and its delayed inverted signal, and outputs the pulse to the memory as a write enable signal. 4. The time bidirectional simulation according to claim 3, wherein the memory is set to a read mode, and control is performed so that a value stored at an address indicated by the read signal can be read from the memory. apparatus. 5. A simulation apparatus for converting a logic circuit into a simulation model and simulating the logic circuit using the simulation model, wherein each register in the logic circuit to be simulated includes a memory, a clock A counter that measures
A conversion unit configured to convert into a simulation model including the memory and a control unit configured to control the counter, wherein the control unit initializes an arbitrary clock time of a simulation start in the counter, and sets the clock time to the The value of each of the register units at a certain clock time is changed while the counter is counting time, and the value of each of the register units at each clock time T counted by the counter is written and stored in an address T of the memory. An input signal at each clock time T of the memory is supplied as an input signal to a combinational circuit unit which is a part of the logic circuit, and an output signal of the combinational circuit unit is stored at an address (T + 1) of the memory. So that the counter can be set to an arbitrary clock. By setting N, the value of each register unit at the arbitrary clock time N stored in the address N of the memory is input to the combinational circuit unit, and the arbitrary clock time is supplied to the combinational circuit unit. N by re-simulating the operation of N to randomly verify a simulation result of the logic circuit at an arbitrary clock time, verify a simulation result of the logic circuit in a forward direction from an arbitrary clock time, and A time bidirectional simulation apparatus that enables a simulation result of the logic circuit to be verified from an arbitrary clock time while going back in a direction opposite to the flow of the simulation.