JPS6441975A - Simulator - Google Patents

Simulator

Info

Publication number
JPS6441975A
JPS6441975A JP62197659A JP19765987A JPS6441975A JP S6441975 A JPS6441975 A JP S6441975A JP 62197659 A JP62197659 A JP 62197659A JP 19765987 A JP19765987 A JP 19765987A JP S6441975 A JPS6441975 A JP S6441975A
Authority
JP
Japan
Prior art keywords
event
main body
output
inputs
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62197659A
Other languages
Japanese (ja)
Other versions
JPH0535909B2 (en
Inventor
Masahiko Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62197659A priority Critical patent/JPS6441975A/en
Publication of JPS6441975A publication Critical patent/JPS6441975A/en
Publication of JPH0535909B2 publication Critical patent/JPH0535909B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To constitute a high-speed simulator by making respective cycles execute simultaneously the processing of the condition reproducing of a necessary IC in parallel with a simulation main body. CONSTITUTION:When a setting part 4 inputs an event 100 from a simulation main body 10, the setting part 4 outputs a setting event 102. An IC 1 inputs a supplying event 104 from a vector memory 2, executes a prescribed action and outputs an output 105. When a control circuit 3 inputs a starting signal 101 of a clock to simulate from the simulation main body 10, the control circuit 3 starts immediately the supplying of a sweeping-out clock 103. As a result of executing a prescribed inside processing by the IC 1, when the IC 1 outputs the output 105, an event output part 5 senses the output and returns it as a response event 106 to the simulator main body 10.
JP62197659A 1987-08-07 1987-08-07 Simulator Granted JPS6441975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62197659A JPS6441975A (en) 1987-08-07 1987-08-07 Simulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62197659A JPS6441975A (en) 1987-08-07 1987-08-07 Simulator

Publications (2)

Publication Number Publication Date
JPS6441975A true JPS6441975A (en) 1989-02-14
JPH0535909B2 JPH0535909B2 (en) 1993-05-27

Family

ID=16378184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62197659A Granted JPS6441975A (en) 1987-08-07 1987-08-07 Simulator

Country Status (1)

Country Link
JP (1) JPS6441975A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352037A (en) * 1989-07-20 1991-03-06 Fujitsu Ltd Time two-way simulation system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352037A (en) * 1989-07-20 1991-03-06 Fujitsu Ltd Time two-way simulation system

Also Published As

Publication number Publication date
JPH0535909B2 (en) 1993-05-27

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees