JPS5472643A - Processing system for different speed multi-input operation - Google Patents

Processing system for different speed multi-input operation

Info

Publication number
JPS5472643A
JPS5472643A JP14050977A JP14050977A JPS5472643A JP S5472643 A JPS5472643 A JP S5472643A JP 14050977 A JP14050977 A JP 14050977A JP 14050977 A JP14050977 A JP 14050977A JP S5472643 A JPS5472643 A JP S5472643A
Authority
JP
Japan
Prior art keywords
input
processing
program
speed
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14050977A
Other languages
Japanese (ja)
Other versions
JPS6134181B2 (en
Inventor
Tsutomu Hosokawa
Kenji Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14050977A priority Critical patent/JPS5472643A/en
Publication of JPS5472643A publication Critical patent/JPS5472643A/en
Publication of JPS6134181B2 publication Critical patent/JPS6134181B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To enable to process in real time synchronously 2 and over information with differnt synchronization in the operational circuit controlled by a program by equipping buffer memories in both I/O sides.
CONSTITUTION: In the operation processing circuit constituted by operation circuit 1 with a microprocessor, program memory element 2 consisting of ROM and buffer memories 3 and 4, a processing program of input A is executed by 1 time within the execution processing time required for input A. On the other hand, if information is entered by a signal of connection 8 which indicates the existence of information in memory 3 is case of input B processing, the processing program for input B is executed (if no information, the processing programe is jumped). If the speed of input A is completely the same as that of input B, the processing program of input B is executed by one time during one program period but, when the speed of input A is slower than that of input B, the processing program of input B is executed by 2 times during one program period, so that real-time processing for both input A and B is available within the speed that the speed of input B is less then twice the speed of input A.
COPYRIGHT: (C)1979,JPO&Japio
JP14050977A 1977-11-21 1977-11-21 Processing system for different speed multi-input operation Granted JPS5472643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14050977A JPS5472643A (en) 1977-11-21 1977-11-21 Processing system for different speed multi-input operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14050977A JPS5472643A (en) 1977-11-21 1977-11-21 Processing system for different speed multi-input operation

Publications (2)

Publication Number Publication Date
JPS5472643A true JPS5472643A (en) 1979-06-11
JPS6134181B2 JPS6134181B2 (en) 1986-08-06

Family

ID=15270294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14050977A Granted JPS5472643A (en) 1977-11-21 1977-11-21 Processing system for different speed multi-input operation

Country Status (1)

Country Link
JP (1) JPS5472643A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258284U (en) * 1988-10-18 1990-04-26

Also Published As

Publication number Publication date
JPS6134181B2 (en) 1986-08-06

Similar Documents

Publication Publication Date Title
EP0126163A4 (en) Controller with status display unit.
JPS5436138A (en) Direct memory access system
JPS53108254A (en) Information processor
JPS57182257A (en) Data interchange system of data processing system
JPS5293243A (en) Data processing unit performing preceding control
JPS5472643A (en) Processing system for different speed multi-input operation
JPS545343A (en) Micro program processing system
JPS5427740A (en) Information processing unit
JPS5222844A (en) Control method to control other unit in the multiple data processing system
JPS5445550A (en) Digital protection control unit
JPS5440538A (en) Multiple data processor
JPS5439541A (en) Data processor
JPS52129252A (en) Program processing unit
JPS55146559A (en) Data processing unit
JPS5427737A (en) Bus control system
JPS5421229A (en) Data fetch system
JPS5427738A (en) Bus stall processing system
JPS542634A (en) Address fault processing system
JPS5430753A (en) Micro-progran control system
JPS5419622A (en) Control system for response confirmation
JPS53139443A (en) Circuit control system
JPS5523563A (en) Computer system
JPS53143367A (en) Electronic watch
JPS5346243A (en) Processor control system
JPS51144137A (en) Input/output data control unit