JPH0352037A - Time two-way simulation system - Google Patents

Abstract

PURPOSE:To not only advance circuit operation with time, but also easily put the operation back to a past state by cascading a counter and a memory by making the register of an object circuit into a model. CONSTITUTION:A converting means 12 converts the contents of the register part 11 of a logic circuit 10 into the contents of a memory 2 and a counter 1 which counts a clock. A control means 6 set an optional time T in the counter, writes the logic of clock time T for setting in the register part 11 of a logic circuit 10 into an address T of the memory 2, and then reads the contents set in the register part 11 out of the address of the memory 2. The simulation signal of a logic simulation part for the logic circuit 10 in the actual object circuit is advanced with time or put back to the past to obtain the contents of the register 11 at optional time. Consequently, the circuit operation is not only advanced with time, but also traced back to the past.

Description

[Detailed Description of the Invention] [Summary] Regarding the time-bidirectional simulation method for verifying past logical values, it is possible to not only advance the circuit operation in the time direction but also to go back in time. The purpose of the present invention is to provide a conversion means for converting a register section of a logic circuit into a counter that ticks memory and clock time, and an arbitrary time T is set in the counter, and an arbitrary time T is set in the register section of the logic circuit. a control means for writing the logic of a clock time T to be set into an address T of the memory, and then reading out the contents set in the register part from the address T of the memory, advancing the simulation signal of the logic circuit in the time direction; Alternatively, the register contents at an arbitrary time T can be obtained by going backwards in the time direction.

[Industrial application field]

The present invention relates to a logic simulation method for realizing the operation of a logic circuit on a computer, and more particularly to a time-direction simulation method for verifying past logic values.

Logic simulation is a technology that realizes the functions of a designed logic circuit on a computer before implementing it on an integrated circuit.

In general, a logic circuit is a sequential circuit consisting of a combinational circuit and a register section that holds the results of the combinational circuit, and logic simulation is based on the logic state that occurs in the circuit at any time, that is, the logic state set in each register section. It verifies the logical state. Logic simulation that faithfully represents the target circuit can discover circuit design errors,
Although it is used for making corrections, it is important to have good inspections in the process of discovering malfunctions during simulation and then identifying the cause. Therefore, there is an extremely important need for a time-bidirectional simulation method that allows circuit operations to move forward and backward in time.

[Conventional technology]

Logic simulation methods include a compilation method and an event-driven method. The compilation method is a method in which the instruction code for the operation is generated for each element in order by leveling the execution order of the elements, and the event-driven method is a method in which the instruction code for the operation is generated for each element in order. This method faithfully represents the set of signal line and signal value pairs of the next changing signal in a computer, including the connection state of the logic circuit.

In the event-driven method, there is a representation of the memory data structure in the simulation to describe the structure of the target circuit, and an event occurs when the signal value obtained at time To differs from the value obtained before that. describes the occurrence of the event in time. For this purpose, an event list is created in memory, in which the connections of events that occur at each time are linked using pointers.

However, the conventional method uses a logic simulator that advances the circuit operation in the time direction, and the contents of the registers inside the circuit only store the contents set at each time, so the simulation does not go back in time. For example, even if you want to return to time 99 from time 100, it is necessary to re-execute the simulation from time O to time 99.

[Problem to be solved by the invention]

Therefore, in the conventional method, the target logic circuit becomes large-scale,
If the input sequence becomes long, there is a problem that it takes a lot of time. Even if an event list is used to store most of the circuit's operations at all times, it only advances the circuit's operations in the time direction, which not only requires a very large capacity storage device, but also A problem has arisen in that it takes a very long time to search for and correct design flaws.

The object of the present invention is to provide a time-bidirectional simulation method that not only allows circuit operations to proceed in the time direction, but also allows the circuit operations to be traced back in time.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

The conversion means l2 converts the contents of the register section 1 of the logic circuit 10 into
Convert to the contents of memory 2 and counter 1 that ticks the clock.

The control stage 6 sets an arbitrary time T in a counter, writes the logic of the clock time T to be set in the register section 11 of the logic circuit 10 to the address T of the memory 2, and then writes the contents set in the register section 11. Read from memory 2 address.

Advancing the simulation signal of the logic simulation unit for the logic circuit 10 in the actual target circuit in the time direction,
Alternatively, by going backward in time, the contents of the register 11 at an arbitrary time can be set.

[For production]

In the present invention, all registers inside the logic circuit are modeled by connecting counters and memories, and the contents of the registers are stored in the memory address addressed by the contents of the counter at the clock time, thereby realizing bidirectional time simulation. It makes it possible.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is an embodiment diagram illustrating the concept of the present invention. In the figure, (a) is a register included in a circuit to be subjected to logic simulation, and (a) in the figure is a register model when the register is modeled. The register stores N-bit data Dtfi1, Di, 12, . . .
, DtfiN are set at the rising edge of the clock, and its outputs are D out1, Dot 2,'
・・・． It is expressed as DoutN.

The data Dini of bit i is connected to the Di input of the D-type flip-flop DFFi, and the clock signal is c
It is input to lk and output from Dout and Qi signals. When the clock signal input to clk rises,
Human power signal D. at that point. ,,i is a flip-flop D
FFi is set, and D outi is output as the set content. In this way, the n-bit register constructed from a D-type flip-flop is actually designed, and even on the logic scale
This is the register to be urated. In the present invention, this register is modeled in the register model shown in Figure 1. (c) The register model shown in the figure consists of a counter 1, a memory 2, and a random circuit 6. Counter 1 is an address counter for memory 2, and counter output Do is connected to ADRS of the memory.
Writing to or reading from the memory 2 is performed with respect to an address specified by the contents of . That is, if write enable (WE) is enabled at the address specified by the counter contents, the input signals Difi1 to Dt-N are written to that address. If the write enable is disabled and in the read state, the contents of the address specified by the contents of the counter l are output D of the memory IJ2. ut
1 to D. , N. However, it is assumed that the memory is in a readable or writable state when the chip select terminal CS is I.

In this manner, the present invention models the register portion of the synchronous circuit inside the target circuit using the memory 2 and the counter l representing the clock time, as shown in (b).

Then, it operates so that the state at a certain clock time T is stored in the address T of the memory 2. That is, when advancing in the time direction, the counter 1 is incremented by 1 by the clock, and the input value is written into the memory when WE=1 using the contents as an address, and is released to the output when WE=O. In other words, the counter l has the CLOCK clock input to the elk terminal of the counter, so when advancing in the time direction, when the clock is input manually, the counter is incremented by l, and the contents are output via Do and stored in the memory. 2 ADR
It is given to the S terminal. An inverted signal of the clock signal is generated at the output of the inverting circuit 4 after a delay time after the clock rises. If the output of the inverting circuit 3 is 1, the clock signal itself is also input to the input terminal of the AND circuit 5, and its inverted output is also input to the AND circuit 5. A positive pulse is generated in the output write enable signal WE, and the write enable signal enters the write enable state. Therefore, the counter is incremented by l by the clock, and this is used as the address for Di. t to D. ．． The value of N is written to the memory 2 when WE=1. Then, since the write enable WE period of 1 has a small pulse width, WE becomes O after the pulse is activated and D. uL
1 to D. The contents of counter 1 are released to utN.

If it is desired to return to an arbitrary clock time, the DI manually sets the set time T to the counter 1. Then, by setting the time setting signal 7 input to the MOD terminal to 1 and putting the counter 1 into the set mode, the contents of the set time T are written into the counter. When the time setting signal 7 is 1,
The output of the inverting circuit 3 becomes O, and the output of the AND circuit 5 also becomes 0.
Therefore, WE=O, that is, the read mode is set.

Therefore, the address of the memory 2 is addressed by the address T of the counter 1 representing the set time T, and its contents are D. ut 1 to D. l, utN. This means that it is possible to return to any clock time, and the contents of the register at time T are
means that it is read from. That is, by outputting the contents of time T from the memory 2, logic simulation can be performed for the embedded circuit connected to the output of the register shown in (a). The logic simulation result at time T is output, which makes it possible to easily return to the state at time T in the past. FIG. 3(a) is an example diagram of a target circuit used in the logic simulation method of the present invention, and FIG. 3(c) is an implementation diagram of a time bidirectional simulation model for the example diagram of FIG. 3(a). This is an example diagram. In the circuit shown in Fig. 3(a), DFFI, DFF2, and DFF3 are D-type flip-flops that collectively constitute a 3-bit register.The CLOCK signal is the CLK of each flip-flop.
This is the clock signal input to the Di, D2, and D3 are its input terminals, among which D2 and D3 receive signals input from the outside, ENABLE and DATA-IN. The signal input to D1 is a signal called DATA-01JT, and this signal is the output of NAND gate g4. The lower random circuit 8 has an input connected to the output of a register, and its output is connected to the first DFF1 of the same register.
is the input. The input of the inverting circuit g1 is Q2, which is connected to one terminal of the NAND gate g2, and the other input of g2 is Q3.

Also, NAND gate g3 is connected to the output of g1 and Q1. The outputs of g2 and g3 are the inputs of the NAND gate g4, and the output of g4 is fed back as DATA-OUT and becomes the input of the DFFI. The sequential circuit thus given is a random circuit 8, that is, gl. which is a combinational circuit. It is constructed from the registers of the synchronous circuit connected to g2, g3, g4 and their combination circuit.

A model of such a sequential circuit using the time bidirectional simulation of the present invention is shown in FIG. 3(b). gl. of the combinational circuit originally included in the target circuit. g2,
g3 and g4 are mapped as they are, but the three D-type flip-flops, ie, registers, included in the target circuit are replaced with the register model shown in (c) and converted into a counter-memory connection. The input to the memory 20 is 3 bits: DI, D2, and D3. Input DI
is connected to the output line of g4, which is the output of the combinational circuit, and inputs D2 and D3 are external inputs of the target circuit, *ENABLE and DATA-IN, respectively. Also, the output of the target circuit is Ql. Q2, Q3, the output of the memory 20 is also Ql, Q2 . It is Q3. That is, Ql becomes the input of g3, and Q2 becomes the input of g
1 and g2, and Q3 is the other input of g2. The outputs Ql, Q2, Q3 of the memory 20 are the outputs of the D-type flip-flops Ql. Q2. It corresponds to Q3. And this memory 2
It is the counter 19 that gives the address of 0, and what controls it is the inverting circuit 22, 23 and the AND gate 2.
It is 4. The D1 terminal of the counter 19 inputs the set time, and MOD is the time setting terminal. Memo I720 operates to store the state of clock time T at address T. To advance in the time direction, set the time setting mode to O.
Therefore, the central terminal of the AND gate 24 has l
is input. At this time, the counter 19 is in a state in which the set time cannot be set, and is in a state of counting up every time a clock is input. When the clock rises, the clock signal is input as is to the AND gate 24, and its inverted output is input to the same AND gate 24. Therefore, the WE signal of the memory 20, that is, the write enable signal, has the delay time of the inverting circuit 23. WE= corresponding to
1 pulse is manually applied. At this time, the output of g4 and the *ENABLE and DATA-IN signals, which are external inputs, are written to DI, D2, and D3, which are the inputs of the memory 20, respectively.

This is exactly the same as the DA input to the register when the clock signal is rising in the circuit of Figure 3(a).
TA-OUT signal, ENABLE signal and DATA-I
corresponds to a set of N signals. In the target circuit, these set contents are output to Ql, Q2, and Q3.

Similarly, in the circuit of FIG. 3(b), the contents from the memory 20 are Ql, Q2 . Given as Q3.

In this case, the delay time of the register corresponds to the delay time of the memory. In the target circuit, the output of the D type flip-flop is input to the random circuit 8, and Ql. Q2
．． The logic corresponding to the logic state of Q3 is output from NAND game g4. Similarly, in Figure 3 (b), g
Ql and Q2 outputted from the memory 20 are output to the output terminal of 4.
．． The content determined by the logic state of Q3 is output. memory 2
0 output states Ql, Q2, Q3 are Ql. Q2
, Q3, the logic state output from g4 is also the same as the output of the target circuit. The output of g4 is input to D1 in the target circuit. Correspondingly, the output shown in FIG. 3(c) is input to the D1 terminal of the memory 20. In the target circuit, this D
A logic state of 1 is set in DFF1, and the contents of the previous DFFI are erased. However, in the time bidirectional simulation model shown in Figures 3-), the value of the counter 19 is incremented by 1 as the address count. That is, since the clock rises again and the write enable is output as a pulse, the contents of DI are written to the address counted up at the rise of the clock, that is, an address incremented by 1 from the previous address. At this time, if the external input DATA-IN
or* If the ENABLE signal is also updated, new contents are written to the incremented address. The previous clock states DI, D2, and D3 disappear from the D-type flip-flop in the target circuit, but since the memory 20 is used in the model, they remain at the previous address. Therefore, if the contents of the counter 19 are reset to the value before updating, the register contents of the target circuit at a past time can be set again. That is, by setting an arbitrary value T as the set time in the counter 19, it becomes possible to output the contents corresponding to the set time T from the memory 20. That is, when the time setting terminal is set to 1, the set time at that time is D.
If it is set from 1, the set contents are given to the memory address from Do, and the contents at that time are outputted to the memory 20 outputs Ql, Q2 . Output from Q3. Note that when the time setting terminal is 1, the output of the inverting circuit 22 is O, so WE=O, and the read mode is entered.

As described above, in the present invention, it is possible to advance the simulation of the target logic circuit in the time direction or to set the time to an arbitrary time T, and the contents at that time T can be output from the memory 20. ．． This output is generated by the combinational circuits gl, g2, g3, which are inside the same logic circuit.
Since it becomes the input of g4, the output state at that time can be predicted from the combinational circuit. This indicates that it is possible to reproduce the logic state of the target circuit at any time. That is, in the present invention, if you want to return to time 99 at time 100, set the set time to 99,
By putting 1 in the time setting signal, you can easily set the time to 99.
It is possible to return to

There is no need to re-execute the simulation of advancing the time direction from time 0 to 99 as in the conventional case.

In this way, in the present invention, all the registers inside the logic circuit are modeled by connecting counters and memories, and the contents of the registers are stored in the memory address addressed by the contents of the counter at the clock time. This makes it possible to perform forward-looking simulations.

〔Effect of the invention〕

In the present invention, by using the register of the target circuit as a model and creating a cascade combination of a counter and a memory, it is possible not only to advance the circuit operation in the time direction but also to easily return it to the past state.

Therefore, it is easy to discover circuit design errors and malfunctions when they are discovered and corrected through logic simulation, and the process of identifying the specific design errors that cause them is extremely easy to operate, and time-directional simulation is possible. Easy and fast.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 (a) is a circuit diagram of a register that is the target of the algorithm of the present invention, Fig. 2 (b) is a circuit diagram of a register model of the present invention, and Fig. 3
Figure (a) is a block diagram of one embodiment of the present invention, Figure 3 (b)
) is a circuit diagram of a bidirectional time simulation model according to the present invention. 1 ... Counter 2 ... Memory 6 ... Control means 10 ... Logic circuit 1 ... Register section 12 ... Exchange means

Claims (1)

[Claims] 1) The register section (11) of the logic circuit (10) is connected to the memory (
2) a conversion means (12) for converting a clock time into a counter (1) that ticks clock time; and a conversion means (12) for setting an arbitrary time T in the counter (1) and setting it in the register section (11) of the logic circuit (10). The state (or contents) of the clock time T that should be performed is stored in the memory (2
), and then write to the address T of the register section (1
1) has a control means (6) for reading out the contents set in the memory (2) from the address T, and by advancing the simulation signal of the logic circuit (10) in the time direction or going back in the time direction. , a time bidirectional simulation method that allows register contents at any time T. 2) The memory (2) of the conversion means (12) is connected to write signal lines and read signal lines corresponding to the input/output signal lines of the register section (11) of the target logic circuit (10), and receives address signals. 2. The time bidirectional simulation method according to claim 1, wherein is an output signal of the counter (1). 3) The counter (1) of the converting means (12) has an output connected to the address of the memory (2), and when not in a time setting mode, counts the address of the memory every time a clock signal is input; The time according to claim 1, characterized in that when in the time setting mode, a set time input to the counter (1) is set, and an address corresponding to the set time is given to the memory (2). Bidirectional simulation method. 4) When the control means (6) is not in the time setting mode, the control means (6) applies a pulse formed from a clock signal and its inverted signal to the memory (2) as a write enable signal; 2. The time bidirectional simulation method according to claim 1, wherein: is set to read mode. 5) The register section (11) of the logic circuit (10) is connected to the memory (
2), a conversion means (12) for converting the clock time into a counter (1), and a clock time T of the logic circuit (10).
means for writing and retaining the state of the register section (11) in the address T of the memory (2), means for setting a counter at an arbitrary time T, and a logic circuit (10) according to the output of the memory (2). A time bidirectional simulation method that has means for simulating a combinational circuit section of the logic circuit (10), and enables the simulation of the logic circuit (10) to be advanced in the time direction, backward in time, or skipped to an arbitrary time.