JPS59188753A - Parity generating method - Google Patents

Abstract

PURPOSE:To generate the integrated parity bit of a group of data by generating corresponding parity bits for every data received following to a clock by taking their previous record into consideration storing the generated parity bits in a register and collating the previous parity bit at every time. CONSTITUTION:This device is composed of a data outputting section 1 and parity generating section 2 and a data controlling circuit 12 sends a data sending start signal ST by one clock. A data outputting circuit 11 sends four-bit data. Therefore, the exclusive OR signal of the four-bit data inputted into a parity generating circuit 21 is obtained and a data parity signal DPG is outputted at each time. Since the output OGC of a register 22 is ''0'' at the 1st time, the signal DPG is stored in the register 22 as an output integrated parity signal PG as it is. On and after the 2nd time, a new parity signal PG is generated by taking the exclusive OR of the previous parity signal PGC and the parity signal DPG of that time.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for generating parity in a data processing system.

(b) Background of the Technology A data processing system is usually constructed based on operations using a binary system using logic circuits of semiconductor devices.

Conventionally, logic circuits include combinational circuit elements such as NAND and NOR circuits, registers, and flip-flop circuits (FF).
It is equipped with a large number of sequential circuits, and is connected to each other to function as a data block consisting of various registers, FFs, etc. for storing data, and data transmission paths connecting these, and a data block within the data block. various registers that control the transfer sequence, the type of operation in each operation step, the operation execution sequence, etc., and the parity bit that manages the high level of the control blower bits, such as 1'', to odd or even parity. A parity check is used to check the final bit of a binary number and improve the reliability of the logic circuit. To do this, determine the number of "1" bits and generate a parity bit.To add it, confirm reception of the last byte of data and generate parity, so processing is concentrated in a short time, and all data must be held and stored once. 0(d) Purpose of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks by increasing the circuit size in proportion to the amount of data.
To generate a group of parity bits, the present invention aims to provide a means for finally processing input data without providing a large number of registers, and ensuring that necessary parity bits are always generated when the reception of all data for one group is completed. (e) Structure of the Invention The object of the present invention is to provide a means for generating a parity bit corresponding to each data received in accordance with a clock while taking into account the previous history in a data processing system consisting of a plurality of bits. The device is equipped with a means for storing a parity bit in a register, and stores the generated parity bit obtained by the parity generating means in the register upon the first data reception, and receives the nth data from the second time onwards. The n-th generated parity pin obtained by comparing the n-th stored parity bit stored in the register to generate the n-th accumulated parity bit, and replace it with the stored parity bit. This can be achieved by providing a parity generation method characterized in that the accumulated parity bits are updated and stored in the register, and the accumulated parity bits according to the n-th received data are always held in the register.

(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a parity generation method in an embodiment of the present invention, and FIG. 2 is a time chart thereof.
In the figure, 1 is a data output section, 2 is a parity generation section, 1
1 is a data output circuit, 12 is a data control circuit, 21 is a parity generation circuit, 22 is a register, and E-OR1~,
is an exclusive OR circuit and AND is an OR circuit 0
Each functional circuit operates according to the clock CLK, but the data control circuit 12 sends out the data transmission start signal ST for one clock, and the data output circuit 11 outputs data consisting of multiple bits, data #0 Dino consisting of 4 bits.
~#3 Send Din3 at every clock timing,
Therefore, D in input to the parity generation circuit 21
o to 3 obtain an exclusive OR signal by E-OR, and output a data parity signal DPG each time. On the other hand, at the first data input, register 22 is 5TO)
A parity bit is generated from only data bits due to the 0 level, and the output signals PGO and ST are input.
The output parity control signal PGC is O and E-OR.
, so that both DPG and PGC are O, and the output integrated parity signal PG of E-OR has the θ level shown in ■.0 This O level is set as ■ in the register at the next clock. . Note that the shaded area shown in the time chart in Figure 2 is an uncertain area of "0" and 1.Next, in the second input, 1 is output from the DPG 5 by data input.On the other hand, ST is 1 .PGO outputs 0 according to the previous ■, and PGC becomes 01. Therefore, PC becomes 1 of ■, and in this case, 1 of ■ is stored in the register 22. 0 Data is input in this way, and the DPG and register are The previous PG and ST stored in
) is exclusive-ORed using E-OR and stored in place of the previous PG. In this way, the fourth ■
is stored as ■ by the next clock. As described above, each time data is input, PG is stored in the register 22.
Therefore, parity for one group of data from the start of data transmission to the final data can be easily obtained as PGO. In the above explanation, the data structure is 4 bits and has even parity, but it goes without saying that one word can be structured as any number of bits, and odd parity can also be easily created if necessary. (g) Detailed Description of the Invention As described above, according to the present invention, there is no need for large-capacity registers corresponding to the number of bits in one group of data as in the conventional case, and the circuit structure is simple and one clock after receiving the final data. This is useful because it provides a means for generating parity bits for a group of data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a parity generation method according to an embodiment of the present invention, and FIG. 2 is a time chart thereof. In the figure, 1 is a data output section, 2 is a parity generation section, 2
1 is a parity generation circuit and 22 is a register.

Claims (1)

[Claims] A system for processing data consisting of a plurality of bits, comprising means for generating a parity bit corresponding to each data received in accordance with a clock while taking into account previous history, and means for storing the parity bit in a register; The generated parity bit obtained by the parity generation means upon the first data reception is stored in the register, and from the second time onward, the nth generated parity bit obtained by receiving the nth data is stored in the register. The stored parity bits up to the IEn time are collated to generate the accumulated parity bits up to the IEn time, and the accumulated parity bits are updated and stored in the register in place of the stored parity bits. Parity generation method 0 characterized by holding accumulated parity bits from received data up to now in a register